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charset="UTF-8" Content-Transfer-Encoding: quoted-printable On Thu, Mar 21, 2024 at 12:15=E2=80=AFAM Thomas Richter wrote: > > On s390 z/VM virtual machines command perf list also displays metrics: > > # ./perf list | grep -A 20 'Metric Groups:' > Metric Groups: > > No_group: > cpi > [Cycles per Instruction] > est_cpi > [Estimated Instruction Complexity CPI infinite Level 1] > finite_cpi > [Cycles per Instructions from Finite cache/memory] > l1mp > [Level One Miss per 100 Instructions] > l2p > [Percentage sourced from Level 2 cache] > l3p > [Percentage sourced from Level 3 on same chip cache] > l4lp > [Percentage sourced from Level 4 Local cache on same book] > l4rp > [Percentage sourced from Level 4 Remote cache on different book] > memp > [Percentage sourced from memory] > .... > # > > The command > > # ./perf stat -M cpi -- true > event syntax error: '{CPU_CYCLES/metric-id=3DCPU_CYCLES/.....' > \___ Bad event or PMU > > Unable to find PMU or event on a PMU of 'CPU_CYCLES' > > event syntax error: '{CPU_CYCLES/metric-id=3DCPU_CYCLES/...' > \___ Cannot find PMU `CPU_CYCLES'. > Missing kernel support? > # > > fails. Perf stat should not fail on metrics when the referenced > CPU Counter Measurement PMU is not available. > > Output after: > # ./perf stat -M est_cpi -- sleep 1 > > Performance counter stats for 'sleep 1': > > 1,000,887,494 ns duration_time # 0.00 est_cpi > > 1.000887494 seconds time elapsed > > 0.000143000 seconds user > 0.000662000 seconds sys > > # > > Fixes: 7f76b3113068 ("perf list: Add IBM z16 event description for s390") > Signed-off-by: Thomas Richter > Suggested-by: Ian Rogers Reviewed-by: Ian Rogers Thanks, Ian > --- > .../arch/s390/cf_z16/transaction.json | 28 +++++++++---------- > 1 file changed, 14 insertions(+), 14 deletions(-) > > diff --git a/tools/perf/pmu-events/arch/s390/cf_z16/transaction.json b/to= ols/perf/pmu-events/arch/s390/cf_z16/transaction.json > index ec2ff78e2b5f..3ab1d3a6638c 100644 > --- a/tools/perf/pmu-events/arch/s390/cf_z16/transaction.json > +++ b/tools/perf/pmu-events/arch/s390/cf_z16/transaction.json > @@ -2,71 +2,71 @@ > { > "BriefDescription": "Transaction count", > "MetricName": "transaction", > - "MetricExpr": "TX_C_TEND + TX_NC_TEND + TX_NC_TABORT + TX_C_TABORT_S= PECIAL + TX_C_TABORT_NO_SPECIAL" > + "MetricExpr": "TX_C_TEND + TX_NC_TEND + TX_NC_TABORT + TX_C_TABORT_S= PECIAL + TX_C_TABORT_NO_SPECIAL if has_event(TX_C_TEND) else 0" > }, > { > "BriefDescription": "Cycles per Instruction", > "MetricName": "cpi", > - "MetricExpr": "CPU_CYCLES / INSTRUCTIONS" > + "MetricExpr": "CPU_CYCLES / INSTRUCTIONS if has_event(INSTRUCTIONS) = else 0" > }, > { > "BriefDescription": "Problem State Instruction Ratio", > "MetricName": "prbstate", > - "MetricExpr": "(PROBLEM_STATE_INSTRUCTIONS / INSTRUCTIONS) * 100" > + "MetricExpr": "(PROBLEM_STATE_INSTRUCTIONS / INSTRUCTIONS) * 100 if = has_event(INSTRUCTIONS) else 0" > }, > { > "BriefDescription": "Level One Miss per 100 Instructions", > "MetricName": "l1mp", > - "MetricExpr": "((L1I_DIR_WRITES + L1D_DIR_WRITES) / INSTRUCTIONS) * = 100" > + "MetricExpr": "((L1I_DIR_WRITES + L1D_DIR_WRITES) / INSTRUCTIONS) * = 100 if has_event(INSTRUCTIONS) else 0" > }, > { > "BriefDescription": "Percentage sourced from Level 2 cache", > "MetricName": "l2p", > - "MetricExpr": "((DCW_REQ + DCW_REQ_IV + ICW_REQ + ICW_REQ_IV) / (L1I= _DIR_WRITES + L1D_DIR_WRITES)) * 100" > + "MetricExpr": "((DCW_REQ + DCW_REQ_IV + ICW_REQ + ICW_REQ_IV) / (L1I= _DIR_WRITES + L1D_DIR_WRITES)) * 100 if has_event(DCW_REQ) else 0" > }, > { > "BriefDescription": "Percentage sourced from Level 3 on same chip ca= che", > "MetricName": "l3p", > - "MetricExpr": "((DCW_REQ_CHIP_HIT + DCW_ON_CHIP + DCW_ON_CHIP_IV + D= CW_ON_CHIP_CHIP_HIT + ICW_REQ_CHIP_HIT + ICW_ON_CHIP + ICW_ON_CHIP_IV + ICW= _ON_CHIP_CHIP_HIT) / (L1I_DIR_WRITES + L1D_DIR_WRITES)) * 100" > + "MetricExpr": "((DCW_REQ_CHIP_HIT + DCW_ON_CHIP + DCW_ON_CHIP_IV + D= CW_ON_CHIP_CHIP_HIT + ICW_REQ_CHIP_HIT + ICW_ON_CHIP + ICW_ON_CHIP_IV + ICW= _ON_CHIP_CHIP_HIT) / (L1I_DIR_WRITES + L1D_DIR_WRITES)) * 100 if has_event(= DCW_REQ_CHIP_HIT) else 0" > }, > { > "BriefDescription": "Percentage sourced from Level 4 Local cache on = same book", > "MetricName": "l4lp", > - "MetricExpr": "((DCW_REQ_DRAWER_HIT + DCW_ON_CHIP_DRAWER_HIT + DCW_O= N_MODULE + DCW_ON_DRAWER + IDCW_ON_MODULE_IV + IDCW_ON_MODULE_CHIP_HIT + ID= CW_ON_MODULE_DRAWER_HIT + IDCW_ON_DRAWER_IV + IDCW_ON_DRAWER_CHIP_HIT + IDC= W_ON_DRAWER_DRAWER_HIT + ICW_REQ_DRAWER_HIT + ICW_ON_CHIP_DRAWER_HIT + ICW_= ON_MODULE + ICW_ON_DRAWER) / (L1I_DIR_WRITES + L1D_DIR_WRITES)) * 100" > + "MetricExpr": "((DCW_REQ_DRAWER_HIT + DCW_ON_CHIP_DRAWER_HIT + DCW_O= N_MODULE + DCW_ON_DRAWER + IDCW_ON_MODULE_IV + IDCW_ON_MODULE_CHIP_HIT + ID= CW_ON_MODULE_DRAWER_HIT + IDCW_ON_DRAWER_IV + IDCW_ON_DRAWER_CHIP_HIT + IDC= W_ON_DRAWER_DRAWER_HIT + ICW_REQ_DRAWER_HIT + ICW_ON_CHIP_DRAWER_HIT + ICW_= ON_MODULE + ICW_ON_DRAWER) / (L1I_DIR_WRITES + L1D_DIR_WRITES)) * 100 if ha= s_event(DCW_REQ_DRAWER_HIT) else 0" > }, > { > "BriefDescription": "Percentage sourced from Level 4 Remote cache on= different book", > "MetricName": "l4rp", > - "MetricExpr": "((DCW_OFF_DRAWER + IDCW_OFF_DRAWER_IV + IDCW_OFF_DRAW= ER_CHIP_HIT + IDCW_OFF_DRAWER_DRAWER_HIT + ICW_OFF_DRAWER) / (L1I_DIR_WRITE= S + L1D_DIR_WRITES)) * 100" > + "MetricExpr": "((DCW_OFF_DRAWER + IDCW_OFF_DRAWER_IV + IDCW_OFF_DRAW= ER_CHIP_HIT + IDCW_OFF_DRAWER_DRAWER_HIT + ICW_OFF_DRAWER) / (L1I_DIR_WRITE= S + L1D_DIR_WRITES)) * 100 if has_event(DCW_OFF_DRAWER) else 0" > }, > { > "BriefDescription": "Percentage sourced from memory", > "MetricName": "memp", > - "MetricExpr": "((DCW_ON_CHIP_MEMORY + DCW_ON_MODULE_MEMORY + DCW_ON_= DRAWER_MEMORY + DCW_OFF_DRAWER_MEMORY + ICW_ON_CHIP_MEMORY + ICW_ON_MODULE_= MEMORY + ICW_ON_DRAWER_MEMORY + ICW_OFF_DRAWER_MEMORY) / (L1I_DIR_WRITES + = L1D_DIR_WRITES)) * 100" > + "MetricExpr": "((DCW_ON_CHIP_MEMORY + DCW_ON_MODULE_MEMORY + DCW_ON_= DRAWER_MEMORY + DCW_OFF_DRAWER_MEMORY + ICW_ON_CHIP_MEMORY + ICW_ON_MODULE_= MEMORY + ICW_ON_DRAWER_MEMORY + ICW_OFF_DRAWER_MEMORY) / (L1I_DIR_WRITES + = L1D_DIR_WRITES)) * 100 if has_event(DCW_ON_CHIP_MEMORY) else 0" > }, > { > "BriefDescription": "Cycles per Instructions from Finite cache/memor= y", > "MetricName": "finite_cpi", > - "MetricExpr": "L1C_TLB2_MISSES / INSTRUCTIONS" > + "MetricExpr": "L1C_TLB2_MISSES / INSTRUCTIONS if has_event(L1C_TLB2_= MISSES) else 0" > }, > { > "BriefDescription": "Estimated Instruction Complexity CPI infinite L= evel 1", > "MetricName": "est_cpi", > - "MetricExpr": "(CPU_CYCLES / INSTRUCTIONS) - (L1C_TLB2_MISSES / INST= RUCTIONS)" > + "MetricExpr": "(CPU_CYCLES / INSTRUCTIONS) - (L1C_TLB2_MISSES / INST= RUCTIONS) if has_event(INSTRUCTIONS) else 0" > }, > { > "BriefDescription": "Estimated Sourcing Cycles per Level 1 Miss", > "MetricName": "scpl1m", > - "MetricExpr": "L1C_TLB2_MISSES / (L1I_DIR_WRITES + L1D_DIR_WRITES)" > + "MetricExpr": "L1C_TLB2_MISSES / (L1I_DIR_WRITES + L1D_DIR_WRITES) i= f has_event(L1C_TLB2_MISSES) else 0" > }, > { > "BriefDescription": "Estimated TLB CPU percentage of Total CPU", > "MetricName": "tlb_percent", > - "MetricExpr": "((DTLB2_MISSES + ITLB2_MISSES) / CPU_CYCLES) * (L1C_T= LB2_MISSES / (L1I_PENALTY_CYCLES + L1D_PENALTY_CYCLES)) * 100" > + "MetricExpr": "((DTLB2_MISSES + ITLB2_MISSES) / CPU_CYCLES) * (L1C_T= LB2_MISSES / (L1I_PENALTY_CYCLES + L1D_PENALTY_CYCLES)) * 100 if has_event(= CPU_CYCLES) else 0" > }, > { > "BriefDescription": "Estimated Cycles per TLB Miss", > "MetricName": "tlb_miss", > - "MetricExpr": "((DTLB2_MISSES + ITLB2_MISSES) / (DTLB2_WRITES + ITLB= 2_WRITES)) * (L1C_TLB2_MISSES / (L1I_PENALTY_CYCLES + L1D_PENALTY_CYCLES))" > + "MetricExpr": "((DTLB2_MISSES + ITLB2_MISSES) / (DTLB2_WRITES + ITLB= 2_WRITES)) * (L1C_TLB2_MISSES / (L1I_PENALTY_CYCLES + L1D_PENALTY_CYCLES)) = if has_event(DTLB2_MISSES) else 0" > } > ] > -- > 2.44.0 >