* [PATCH 1/2 v2] perf report: Fix PAI counter names for s390 virtual machines
@ 2024-03-21 7:15 Thomas Richter
2024-03-21 7:15 ` [PATCH 2/2 v2] perf stat: do not fail on metrics on s390 zvm systems Thomas Richter
2024-03-25 16:01 ` [PATCH 1/2 v2] perf report: Fix PAI counter names for s390 virtual machines Ian Rogers
0 siblings, 2 replies; 4+ messages in thread
From: Thomas Richter @ 2024-03-21 7:15 UTC (permalink / raw)
To: linux-kernel, linux-perf-users, acme, irogers
Cc: svens, gor, sumanthk, hca, Thomas Richter
s390 introduced Processor Activity Instrumentation (PAI) counter
facility on LPAR and virtual machines z/VM for models 3931 and 3932.
These counters are stored as raw data in the perf.data file and are
displayed with command
# ./perf report -i /tmp//perfout-635468 -D | grep Counter
Counter:007 <unknown> Value:0x00000000000186a0
Counter:032 <unknown> Value:0x0000000000000001
Counter:032 <unknown> Value:0x0000000000000001
Counter:032 <unknown> Value:0x0000000000000001
#
However on z/VM virtual machines, the counter names are not retrieved
from the PMU and are shown as '<unknown>'.
This is caused by the CPU string saved in the mapfile.csv for this
machine:
^IBM.393[12].*3\.7.[[:xdigit:]]+$,3,cf_z16,core
This string contains the CPU Measurement facility first and second
version number and authorization level (3\.7.[[:xdigit:]]+).
These numbers do not apply to the PAI counter facility.
In fact they can be omitted.
Shorten the CPU identification string for this machine to manufacturer
and model. This is sufficient for all PMU devices.
Output after:
# ./perf report -i /tmp//perfout-635468 -D | grep Counter
Counter:007 km_aes_128 Value:0x00000000000186a0
Counter:032 kma_gcm_aes_256 Value:0x0000000000000001
Counter:032 kma_gcm_aes_256 Value:0x0000000000000001
Counter:032 kma_gcm_aes_256 Value:0x0000000000000001
#
Fixes: b539deafbadb ("perf report: Add s390 raw data interpretation for PAI counters")
Signed-off-by: Thomas Richter <tmricht@linux.ibm.com>
Acked-by: Sumanth Korikkar <sumanthk@linux.ibm.com>
---
tools/perf/pmu-events/arch/s390/mapfile.csv | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/tools/perf/pmu-events/arch/s390/mapfile.csv b/tools/perf/pmu-events/arch/s390/mapfile.csv
index a918e1af77a5..b22648d12751 100644
--- a/tools/perf/pmu-events/arch/s390/mapfile.csv
+++ b/tools/perf/pmu-events/arch/s390/mapfile.csv
@@ -5,4 +5,4 @@ Family-model,Version,Filename,EventType
^IBM.296[45].*[13]\.[1-5].[[:xdigit:]]+$,1,cf_z13,core
^IBM.390[67].*[13]\.[1-5].[[:xdigit:]]+$,3,cf_z14,core
^IBM.856[12].*3\.6.[[:xdigit:]]+$,3,cf_z15,core
-^IBM.393[12].*3\.7.[[:xdigit:]]+$,3,cf_z16,core
+^IBM.393[12].*$,3,cf_z16,core
--
2.44.0
^ permalink raw reply related [flat|nested] 4+ messages in thread* [PATCH 2/2 v2] perf stat: do not fail on metrics on s390 zvm systems 2024-03-21 7:15 [PATCH 1/2 v2] perf report: Fix PAI counter names for s390 virtual machines Thomas Richter @ 2024-03-21 7:15 ` Thomas Richter 2024-03-25 16:02 ` Ian Rogers 2024-03-25 16:01 ` [PATCH 1/2 v2] perf report: Fix PAI counter names for s390 virtual machines Ian Rogers 1 sibling, 1 reply; 4+ messages in thread From: Thomas Richter @ 2024-03-21 7:15 UTC (permalink / raw) To: linux-kernel, linux-perf-users, acme, irogers Cc: svens, gor, sumanthk, hca, Thomas Richter On s390 z/VM virtual machines command perf list also displays metrics: # ./perf list | grep -A 20 'Metric Groups:' Metric Groups: No_group: cpi [Cycles per Instruction] est_cpi [Estimated Instruction Complexity CPI infinite Level 1] finite_cpi [Cycles per Instructions from Finite cache/memory] l1mp [Level One Miss per 100 Instructions] l2p [Percentage sourced from Level 2 cache] l3p [Percentage sourced from Level 3 on same chip cache] l4lp [Percentage sourced from Level 4 Local cache on same book] l4rp [Percentage sourced from Level 4 Remote cache on different book] memp [Percentage sourced from memory] .... # The command # ./perf stat -M cpi -- true event syntax error: '{CPU_CYCLES/metric-id=CPU_CYCLES/.....' \___ Bad event or PMU Unable to find PMU or event on a PMU of 'CPU_CYCLES' event syntax error: '{CPU_CYCLES/metric-id=CPU_CYCLES/...' \___ Cannot find PMU `CPU_CYCLES'. Missing kernel support? # fails. Perf stat should not fail on metrics when the referenced CPU Counter Measurement PMU is not available. Output after: # ./perf stat -M est_cpi -- sleep 1 Performance counter stats for 'sleep 1': 1,000,887,494 ns duration_time # 0.00 est_cpi 1.000887494 seconds time elapsed 0.000143000 seconds user 0.000662000 seconds sys # Fixes: 7f76b3113068 ("perf list: Add IBM z16 event description for s390") Signed-off-by: Thomas Richter <tmricht@linux.ibm.com> Suggested-by: Ian Rogers <irogers@google.com> --- .../arch/s390/cf_z16/transaction.json | 28 +++++++++---------- 1 file changed, 14 insertions(+), 14 deletions(-) diff --git a/tools/perf/pmu-events/arch/s390/cf_z16/transaction.json b/tools/perf/pmu-events/arch/s390/cf_z16/transaction.json index ec2ff78e2b5f..3ab1d3a6638c 100644 --- a/tools/perf/pmu-events/arch/s390/cf_z16/transaction.json +++ b/tools/perf/pmu-events/arch/s390/cf_z16/transaction.json @@ -2,71 +2,71 @@ { "BriefDescription": "Transaction count", "MetricName": "transaction", - "MetricExpr": "TX_C_TEND + TX_NC_TEND + TX_NC_TABORT + TX_C_TABORT_SPECIAL + TX_C_TABORT_NO_SPECIAL" + "MetricExpr": "TX_C_TEND + TX_NC_TEND + TX_NC_TABORT + TX_C_TABORT_SPECIAL + TX_C_TABORT_NO_SPECIAL if has_event(TX_C_TEND) else 0" }, { "BriefDescription": "Cycles per Instruction", "MetricName": "cpi", - "MetricExpr": "CPU_CYCLES / INSTRUCTIONS" + "MetricExpr": "CPU_CYCLES / INSTRUCTIONS if has_event(INSTRUCTIONS) else 0" }, { "BriefDescription": "Problem State Instruction Ratio", "MetricName": "prbstate", - "MetricExpr": "(PROBLEM_STATE_INSTRUCTIONS / INSTRUCTIONS) * 100" + "MetricExpr": "(PROBLEM_STATE_INSTRUCTIONS / INSTRUCTIONS) * 100 if has_event(INSTRUCTIONS) else 0" }, { "BriefDescription": "Level One Miss per 100 Instructions", "MetricName": "l1mp", - "MetricExpr": "((L1I_DIR_WRITES + L1D_DIR_WRITES) / INSTRUCTIONS) * 100" + "MetricExpr": "((L1I_DIR_WRITES + L1D_DIR_WRITES) / INSTRUCTIONS) * 100 if has_event(INSTRUCTIONS) else 0" }, { "BriefDescription": "Percentage sourced from Level 2 cache", "MetricName": "l2p", - "MetricExpr": "((DCW_REQ + DCW_REQ_IV + ICW_REQ + ICW_REQ_IV) / (L1I_DIR_WRITES + L1D_DIR_WRITES)) * 100" + "MetricExpr": "((DCW_REQ + DCW_REQ_IV + ICW_REQ + ICW_REQ_IV) / (L1I_DIR_WRITES + L1D_DIR_WRITES)) * 100 if has_event(DCW_REQ) else 0" }, { "BriefDescription": "Percentage sourced from Level 3 on same chip cache", "MetricName": "l3p", - "MetricExpr": "((DCW_REQ_CHIP_HIT + DCW_ON_CHIP + DCW_ON_CHIP_IV + DCW_ON_CHIP_CHIP_HIT + ICW_REQ_CHIP_HIT + ICW_ON_CHIP + ICW_ON_CHIP_IV + ICW_ON_CHIP_CHIP_HIT) / (L1I_DIR_WRITES + L1D_DIR_WRITES)) * 100" + "MetricExpr": "((DCW_REQ_CHIP_HIT + DCW_ON_CHIP + DCW_ON_CHIP_IV + DCW_ON_CHIP_CHIP_HIT + ICW_REQ_CHIP_HIT + ICW_ON_CHIP + ICW_ON_CHIP_IV + ICW_ON_CHIP_CHIP_HIT) / (L1I_DIR_WRITES + L1D_DIR_WRITES)) * 100 if has_event(DCW_REQ_CHIP_HIT) else 0" }, { "BriefDescription": "Percentage sourced from Level 4 Local cache on same book", "MetricName": "l4lp", - "MetricExpr": "((DCW_REQ_DRAWER_HIT + DCW_ON_CHIP_DRAWER_HIT + DCW_ON_MODULE + DCW_ON_DRAWER + IDCW_ON_MODULE_IV + IDCW_ON_MODULE_CHIP_HIT + IDCW_ON_MODULE_DRAWER_HIT + IDCW_ON_DRAWER_IV + IDCW_ON_DRAWER_CHIP_HIT + IDCW_ON_DRAWER_DRAWER_HIT + ICW_REQ_DRAWER_HIT + ICW_ON_CHIP_DRAWER_HIT + ICW_ON_MODULE + ICW_ON_DRAWER) / (L1I_DIR_WRITES + L1D_DIR_WRITES)) * 100" + "MetricExpr": "((DCW_REQ_DRAWER_HIT + DCW_ON_CHIP_DRAWER_HIT + DCW_ON_MODULE + DCW_ON_DRAWER + IDCW_ON_MODULE_IV + IDCW_ON_MODULE_CHIP_HIT + IDCW_ON_MODULE_DRAWER_HIT + IDCW_ON_DRAWER_IV + IDCW_ON_DRAWER_CHIP_HIT + IDCW_ON_DRAWER_DRAWER_HIT + ICW_REQ_DRAWER_HIT + ICW_ON_CHIP_DRAWER_HIT + ICW_ON_MODULE + ICW_ON_DRAWER) / (L1I_DIR_WRITES + L1D_DIR_WRITES)) * 100 if has_event(DCW_REQ_DRAWER_HIT) else 0" }, { "BriefDescription": "Percentage sourced from Level 4 Remote cache on different book", "MetricName": "l4rp", - "MetricExpr": "((DCW_OFF_DRAWER + IDCW_OFF_DRAWER_IV + IDCW_OFF_DRAWER_CHIP_HIT + IDCW_OFF_DRAWER_DRAWER_HIT + ICW_OFF_DRAWER) / (L1I_DIR_WRITES + L1D_DIR_WRITES)) * 100" + "MetricExpr": "((DCW_OFF_DRAWER + IDCW_OFF_DRAWER_IV + IDCW_OFF_DRAWER_CHIP_HIT + IDCW_OFF_DRAWER_DRAWER_HIT + ICW_OFF_DRAWER) / (L1I_DIR_WRITES + L1D_DIR_WRITES)) * 100 if has_event(DCW_OFF_DRAWER) else 0" }, { "BriefDescription": "Percentage sourced from memory", "MetricName": "memp", - "MetricExpr": "((DCW_ON_CHIP_MEMORY + DCW_ON_MODULE_MEMORY + DCW_ON_DRAWER_MEMORY + DCW_OFF_DRAWER_MEMORY + ICW_ON_CHIP_MEMORY + ICW_ON_MODULE_MEMORY + ICW_ON_DRAWER_MEMORY + ICW_OFF_DRAWER_MEMORY) / (L1I_DIR_WRITES + L1D_DIR_WRITES)) * 100" + "MetricExpr": "((DCW_ON_CHIP_MEMORY + DCW_ON_MODULE_MEMORY + DCW_ON_DRAWER_MEMORY + DCW_OFF_DRAWER_MEMORY + ICW_ON_CHIP_MEMORY + ICW_ON_MODULE_MEMORY + ICW_ON_DRAWER_MEMORY + ICW_OFF_DRAWER_MEMORY) / (L1I_DIR_WRITES + L1D_DIR_WRITES)) * 100 if has_event(DCW_ON_CHIP_MEMORY) else 0" }, { "BriefDescription": "Cycles per Instructions from Finite cache/memory", "MetricName": "finite_cpi", - "MetricExpr": "L1C_TLB2_MISSES / INSTRUCTIONS" + "MetricExpr": "L1C_TLB2_MISSES / INSTRUCTIONS if has_event(L1C_TLB2_MISSES) else 0" }, { "BriefDescription": "Estimated Instruction Complexity CPI infinite Level 1", "MetricName": "est_cpi", - "MetricExpr": "(CPU_CYCLES / INSTRUCTIONS) - (L1C_TLB2_MISSES / INSTRUCTIONS)" + "MetricExpr": "(CPU_CYCLES / INSTRUCTIONS) - (L1C_TLB2_MISSES / INSTRUCTIONS) if has_event(INSTRUCTIONS) else 0" }, { "BriefDescription": "Estimated Sourcing Cycles per Level 1 Miss", "MetricName": "scpl1m", - "MetricExpr": "L1C_TLB2_MISSES / (L1I_DIR_WRITES + L1D_DIR_WRITES)" + "MetricExpr": "L1C_TLB2_MISSES / (L1I_DIR_WRITES + L1D_DIR_WRITES) if has_event(L1C_TLB2_MISSES) else 0" }, { "BriefDescription": "Estimated TLB CPU percentage of Total CPU", "MetricName": "tlb_percent", - "MetricExpr": "((DTLB2_MISSES + ITLB2_MISSES) / CPU_CYCLES) * (L1C_TLB2_MISSES / (L1I_PENALTY_CYCLES + L1D_PENALTY_CYCLES)) * 100" + "MetricExpr": "((DTLB2_MISSES + ITLB2_MISSES) / CPU_CYCLES) * (L1C_TLB2_MISSES / (L1I_PENALTY_CYCLES + L1D_PENALTY_CYCLES)) * 100 if has_event(CPU_CYCLES) else 0" }, { "BriefDescription": "Estimated Cycles per TLB Miss", "MetricName": "tlb_miss", - "MetricExpr": "((DTLB2_MISSES + ITLB2_MISSES) / (DTLB2_WRITES + ITLB2_WRITES)) * (L1C_TLB2_MISSES / (L1I_PENALTY_CYCLES + L1D_PENALTY_CYCLES))" + "MetricExpr": "((DTLB2_MISSES + ITLB2_MISSES) / (DTLB2_WRITES + ITLB2_WRITES)) * (L1C_TLB2_MISSES / (L1I_PENALTY_CYCLES + L1D_PENALTY_CYCLES)) if has_event(DTLB2_MISSES) else 0" } ] -- 2.44.0 ^ permalink raw reply related [flat|nested] 4+ messages in thread
* Re: [PATCH 2/2 v2] perf stat: do not fail on metrics on s390 zvm systems 2024-03-21 7:15 ` [PATCH 2/2 v2] perf stat: do not fail on metrics on s390 zvm systems Thomas Richter @ 2024-03-25 16:02 ` Ian Rogers 0 siblings, 0 replies; 4+ messages in thread From: Ian Rogers @ 2024-03-25 16:02 UTC (permalink / raw) To: Thomas Richter Cc: linux-kernel, linux-perf-users, acme, svens, gor, sumanthk, hca On Thu, Mar 21, 2024 at 12:15 AM Thomas Richter <tmricht@linux.ibm.com> wrote: > > On s390 z/VM virtual machines command perf list also displays metrics: > > # ./perf list | grep -A 20 'Metric Groups:' > Metric Groups: > > No_group: > cpi > [Cycles per Instruction] > est_cpi > [Estimated Instruction Complexity CPI infinite Level 1] > finite_cpi > [Cycles per Instructions from Finite cache/memory] > l1mp > [Level One Miss per 100 Instructions] > l2p > [Percentage sourced from Level 2 cache] > l3p > [Percentage sourced from Level 3 on same chip cache] > l4lp > [Percentage sourced from Level 4 Local cache on same book] > l4rp > [Percentage sourced from Level 4 Remote cache on different book] > memp > [Percentage sourced from memory] > .... > # > > The command > > # ./perf stat -M cpi -- true > event syntax error: '{CPU_CYCLES/metric-id=CPU_CYCLES/.....' > \___ Bad event or PMU > > Unable to find PMU or event on a PMU of 'CPU_CYCLES' > > event syntax error: '{CPU_CYCLES/metric-id=CPU_CYCLES/...' > \___ Cannot find PMU `CPU_CYCLES'. > Missing kernel support? > # > > fails. Perf stat should not fail on metrics when the referenced > CPU Counter Measurement PMU is not available. > > Output after: > # ./perf stat -M est_cpi -- sleep 1 > > Performance counter stats for 'sleep 1': > > 1,000,887,494 ns duration_time # 0.00 est_cpi > > 1.000887494 seconds time elapsed > > 0.000143000 seconds user > 0.000662000 seconds sys > > # > > Fixes: 7f76b3113068 ("perf list: Add IBM z16 event description for s390") > Signed-off-by: Thomas Richter <tmricht@linux.ibm.com> > Suggested-by: Ian Rogers <irogers@google.com> Reviewed-by: Ian Rogers <irogers@google.com> Thanks, Ian > --- > .../arch/s390/cf_z16/transaction.json | 28 +++++++++---------- > 1 file changed, 14 insertions(+), 14 deletions(-) > > diff --git a/tools/perf/pmu-events/arch/s390/cf_z16/transaction.json b/tools/perf/pmu-events/arch/s390/cf_z16/transaction.json > index ec2ff78e2b5f..3ab1d3a6638c 100644 > --- a/tools/perf/pmu-events/arch/s390/cf_z16/transaction.json > +++ b/tools/perf/pmu-events/arch/s390/cf_z16/transaction.json > @@ -2,71 +2,71 @@ > { > "BriefDescription": "Transaction count", > "MetricName": "transaction", > - "MetricExpr": "TX_C_TEND + TX_NC_TEND + TX_NC_TABORT + TX_C_TABORT_SPECIAL + TX_C_TABORT_NO_SPECIAL" > + "MetricExpr": "TX_C_TEND + TX_NC_TEND + TX_NC_TABORT + TX_C_TABORT_SPECIAL + TX_C_TABORT_NO_SPECIAL if has_event(TX_C_TEND) else 0" > }, > { > "BriefDescription": "Cycles per Instruction", > "MetricName": "cpi", > - "MetricExpr": "CPU_CYCLES / INSTRUCTIONS" > + "MetricExpr": "CPU_CYCLES / INSTRUCTIONS if has_event(INSTRUCTIONS) else 0" > }, > { > "BriefDescription": "Problem State Instruction Ratio", > "MetricName": "prbstate", > - "MetricExpr": "(PROBLEM_STATE_INSTRUCTIONS / INSTRUCTIONS) * 100" > + "MetricExpr": "(PROBLEM_STATE_INSTRUCTIONS / INSTRUCTIONS) * 100 if has_event(INSTRUCTIONS) else 0" > }, > { > "BriefDescription": "Level One Miss per 100 Instructions", > "MetricName": "l1mp", > - "MetricExpr": "((L1I_DIR_WRITES + L1D_DIR_WRITES) / INSTRUCTIONS) * 100" > + "MetricExpr": "((L1I_DIR_WRITES + L1D_DIR_WRITES) / INSTRUCTIONS) * 100 if has_event(INSTRUCTIONS) else 0" > }, > { > "BriefDescription": "Percentage sourced from Level 2 cache", > "MetricName": "l2p", > - "MetricExpr": "((DCW_REQ + DCW_REQ_IV + ICW_REQ + ICW_REQ_IV) / (L1I_DIR_WRITES + L1D_DIR_WRITES)) * 100" > + "MetricExpr": "((DCW_REQ + DCW_REQ_IV + ICW_REQ + ICW_REQ_IV) / (L1I_DIR_WRITES + L1D_DIR_WRITES)) * 100 if has_event(DCW_REQ) else 0" > }, > { > "BriefDescription": "Percentage sourced from Level 3 on same chip cache", > "MetricName": "l3p", > - "MetricExpr": "((DCW_REQ_CHIP_HIT + DCW_ON_CHIP + DCW_ON_CHIP_IV + DCW_ON_CHIP_CHIP_HIT + ICW_REQ_CHIP_HIT + ICW_ON_CHIP + ICW_ON_CHIP_IV + ICW_ON_CHIP_CHIP_HIT) / (L1I_DIR_WRITES + L1D_DIR_WRITES)) * 100" > + "MetricExpr": "((DCW_REQ_CHIP_HIT + DCW_ON_CHIP + DCW_ON_CHIP_IV + DCW_ON_CHIP_CHIP_HIT + ICW_REQ_CHIP_HIT + ICW_ON_CHIP + ICW_ON_CHIP_IV + ICW_ON_CHIP_CHIP_HIT) / (L1I_DIR_WRITES + L1D_DIR_WRITES)) * 100 if has_event(DCW_REQ_CHIP_HIT) else 0" > }, > { > "BriefDescription": "Percentage sourced from Level 4 Local cache on same book", > "MetricName": "l4lp", > - "MetricExpr": "((DCW_REQ_DRAWER_HIT + DCW_ON_CHIP_DRAWER_HIT + DCW_ON_MODULE + DCW_ON_DRAWER + IDCW_ON_MODULE_IV + IDCW_ON_MODULE_CHIP_HIT + IDCW_ON_MODULE_DRAWER_HIT + IDCW_ON_DRAWER_IV + IDCW_ON_DRAWER_CHIP_HIT + IDCW_ON_DRAWER_DRAWER_HIT + ICW_REQ_DRAWER_HIT + ICW_ON_CHIP_DRAWER_HIT + ICW_ON_MODULE + ICW_ON_DRAWER) / (L1I_DIR_WRITES + L1D_DIR_WRITES)) * 100" > + "MetricExpr": "((DCW_REQ_DRAWER_HIT + DCW_ON_CHIP_DRAWER_HIT + DCW_ON_MODULE + DCW_ON_DRAWER + IDCW_ON_MODULE_IV + IDCW_ON_MODULE_CHIP_HIT + IDCW_ON_MODULE_DRAWER_HIT + IDCW_ON_DRAWER_IV + IDCW_ON_DRAWER_CHIP_HIT + IDCW_ON_DRAWER_DRAWER_HIT + ICW_REQ_DRAWER_HIT + ICW_ON_CHIP_DRAWER_HIT + ICW_ON_MODULE + ICW_ON_DRAWER) / (L1I_DIR_WRITES + L1D_DIR_WRITES)) * 100 if has_event(DCW_REQ_DRAWER_HIT) else 0" > }, > { > "BriefDescription": "Percentage sourced from Level 4 Remote cache on different book", > "MetricName": "l4rp", > - "MetricExpr": "((DCW_OFF_DRAWER + IDCW_OFF_DRAWER_IV + IDCW_OFF_DRAWER_CHIP_HIT + IDCW_OFF_DRAWER_DRAWER_HIT + ICW_OFF_DRAWER) / (L1I_DIR_WRITES + L1D_DIR_WRITES)) * 100" > + "MetricExpr": "((DCW_OFF_DRAWER + IDCW_OFF_DRAWER_IV + IDCW_OFF_DRAWER_CHIP_HIT + IDCW_OFF_DRAWER_DRAWER_HIT + ICW_OFF_DRAWER) / (L1I_DIR_WRITES + L1D_DIR_WRITES)) * 100 if has_event(DCW_OFF_DRAWER) else 0" > }, > { > "BriefDescription": "Percentage sourced from memory", > "MetricName": "memp", > - "MetricExpr": "((DCW_ON_CHIP_MEMORY + DCW_ON_MODULE_MEMORY + DCW_ON_DRAWER_MEMORY + DCW_OFF_DRAWER_MEMORY + ICW_ON_CHIP_MEMORY + ICW_ON_MODULE_MEMORY + ICW_ON_DRAWER_MEMORY + ICW_OFF_DRAWER_MEMORY) / (L1I_DIR_WRITES + L1D_DIR_WRITES)) * 100" > + "MetricExpr": "((DCW_ON_CHIP_MEMORY + DCW_ON_MODULE_MEMORY + DCW_ON_DRAWER_MEMORY + DCW_OFF_DRAWER_MEMORY + ICW_ON_CHIP_MEMORY + ICW_ON_MODULE_MEMORY + ICW_ON_DRAWER_MEMORY + ICW_OFF_DRAWER_MEMORY) / (L1I_DIR_WRITES + L1D_DIR_WRITES)) * 100 if has_event(DCW_ON_CHIP_MEMORY) else 0" > }, > { > "BriefDescription": "Cycles per Instructions from Finite cache/memory", > "MetricName": "finite_cpi", > - "MetricExpr": "L1C_TLB2_MISSES / INSTRUCTIONS" > + "MetricExpr": "L1C_TLB2_MISSES / INSTRUCTIONS if has_event(L1C_TLB2_MISSES) else 0" > }, > { > "BriefDescription": "Estimated Instruction Complexity CPI infinite Level 1", > "MetricName": "est_cpi", > - "MetricExpr": "(CPU_CYCLES / INSTRUCTIONS) - (L1C_TLB2_MISSES / INSTRUCTIONS)" > + "MetricExpr": "(CPU_CYCLES / INSTRUCTIONS) - (L1C_TLB2_MISSES / INSTRUCTIONS) if has_event(INSTRUCTIONS) else 0" > }, > { > "BriefDescription": "Estimated Sourcing Cycles per Level 1 Miss", > "MetricName": "scpl1m", > - "MetricExpr": "L1C_TLB2_MISSES / (L1I_DIR_WRITES + L1D_DIR_WRITES)" > + "MetricExpr": "L1C_TLB2_MISSES / (L1I_DIR_WRITES + L1D_DIR_WRITES) if has_event(L1C_TLB2_MISSES) else 0" > }, > { > "BriefDescription": "Estimated TLB CPU percentage of Total CPU", > "MetricName": "tlb_percent", > - "MetricExpr": "((DTLB2_MISSES + ITLB2_MISSES) / CPU_CYCLES) * (L1C_TLB2_MISSES / (L1I_PENALTY_CYCLES + L1D_PENALTY_CYCLES)) * 100" > + "MetricExpr": "((DTLB2_MISSES + ITLB2_MISSES) / CPU_CYCLES) * (L1C_TLB2_MISSES / (L1I_PENALTY_CYCLES + L1D_PENALTY_CYCLES)) * 100 if has_event(CPU_CYCLES) else 0" > }, > { > "BriefDescription": "Estimated Cycles per TLB Miss", > "MetricName": "tlb_miss", > - "MetricExpr": "((DTLB2_MISSES + ITLB2_MISSES) / (DTLB2_WRITES + ITLB2_WRITES)) * (L1C_TLB2_MISSES / (L1I_PENALTY_CYCLES + L1D_PENALTY_CYCLES))" > + "MetricExpr": "((DTLB2_MISSES + ITLB2_MISSES) / (DTLB2_WRITES + ITLB2_WRITES)) * (L1C_TLB2_MISSES / (L1I_PENALTY_CYCLES + L1D_PENALTY_CYCLES)) if has_event(DTLB2_MISSES) else 0" > } > ] > -- > 2.44.0 > ^ permalink raw reply [flat|nested] 4+ messages in thread
* Re: [PATCH 1/2 v2] perf report: Fix PAI counter names for s390 virtual machines 2024-03-21 7:15 [PATCH 1/2 v2] perf report: Fix PAI counter names for s390 virtual machines Thomas Richter 2024-03-21 7:15 ` [PATCH 2/2 v2] perf stat: do not fail on metrics on s390 zvm systems Thomas Richter @ 2024-03-25 16:01 ` Ian Rogers 1 sibling, 0 replies; 4+ messages in thread From: Ian Rogers @ 2024-03-25 16:01 UTC (permalink / raw) To: Thomas Richter Cc: linux-kernel, linux-perf-users, acme, svens, gor, sumanthk, hca On Thu, Mar 21, 2024 at 12:15 AM Thomas Richter <tmricht@linux.ibm.com> wrote: > > s390 introduced Processor Activity Instrumentation (PAI) counter > facility on LPAR and virtual machines z/VM for models 3931 and 3932. > These counters are stored as raw data in the perf.data file and are > displayed with command > > # ./perf report -i /tmp//perfout-635468 -D | grep Counter > Counter:007 <unknown> Value:0x00000000000186a0 > Counter:032 <unknown> Value:0x0000000000000001 > Counter:032 <unknown> Value:0x0000000000000001 > Counter:032 <unknown> Value:0x0000000000000001 > # > > However on z/VM virtual machines, the counter names are not retrieved > from the PMU and are shown as '<unknown>'. > This is caused by the CPU string saved in the mapfile.csv for this > machine: > > ^IBM.393[12].*3\.7.[[:xdigit:]]+$,3,cf_z16,core > > This string contains the CPU Measurement facility first and second > version number and authorization level (3\.7.[[:xdigit:]]+). > These numbers do not apply to the PAI counter facility. > In fact they can be omitted. > Shorten the CPU identification string for this machine to manufacturer > and model. This is sufficient for all PMU devices. > > Output after: > # ./perf report -i /tmp//perfout-635468 -D | grep Counter > Counter:007 km_aes_128 Value:0x00000000000186a0 > Counter:032 kma_gcm_aes_256 Value:0x0000000000000001 > Counter:032 kma_gcm_aes_256 Value:0x0000000000000001 > Counter:032 kma_gcm_aes_256 Value:0x0000000000000001 > # > > Fixes: b539deafbadb ("perf report: Add s390 raw data interpretation for PAI counters") > > Signed-off-by: Thomas Richter <tmricht@linux.ibm.com> > Acked-by: Sumanth Korikkar <sumanthk@linux.ibm.com> Reviewed-by: Ian Rogers <irogers@google.com> Thanks, Ian > --- > tools/perf/pmu-events/arch/s390/mapfile.csv | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/tools/perf/pmu-events/arch/s390/mapfile.csv b/tools/perf/pmu-events/arch/s390/mapfile.csv > index a918e1af77a5..b22648d12751 100644 > --- a/tools/perf/pmu-events/arch/s390/mapfile.csv > +++ b/tools/perf/pmu-events/arch/s390/mapfile.csv > @@ -5,4 +5,4 @@ Family-model,Version,Filename,EventType > ^IBM.296[45].*[13]\.[1-5].[[:xdigit:]]+$,1,cf_z13,core > ^IBM.390[67].*[13]\.[1-5].[[:xdigit:]]+$,3,cf_z14,core > ^IBM.856[12].*3\.6.[[:xdigit:]]+$,3,cf_z15,core > -^IBM.393[12].*3\.7.[[:xdigit:]]+$,3,cf_z16,core > +^IBM.393[12].*$,3,cf_z16,core > -- > 2.44.0 > ^ permalink raw reply [flat|nested] 4+ messages in thread
end of thread, other threads:[~2024-03-25 16:02 UTC | newest] Thread overview: 4+ messages (download: mbox.gz follow: Atom feed -- links below jump to the message on this page -- 2024-03-21 7:15 [PATCH 1/2 v2] perf report: Fix PAI counter names for s390 virtual machines Thomas Richter 2024-03-21 7:15 ` [PATCH 2/2 v2] perf stat: do not fail on metrics on s390 zvm systems Thomas Richter 2024-03-25 16:02 ` Ian Rogers 2024-03-25 16:01 ` [PATCH 1/2 v2] perf report: Fix PAI counter names for s390 virtual machines Ian Rogers
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