* [PATCH v1 0/3] Update Alderlake and IcelakeX events
@ 2023-02-23 5:53 Ian Rogers
2023-02-23 5:53 ` [PATCH v1 1/3] perf vendor events intel: Update alderlake to v1.19 Ian Rogers
` (3 more replies)
0 siblings, 4 replies; 5+ messages in thread
From: Ian Rogers @ 2023-02-23 5:53 UTC (permalink / raw)
To: Peter Zijlstra, Ingo Molnar, Arnaldo Carvalho de Melo,
Mark Rutland, Alexander Shishkin, Jiri Olsa, Namhyung Kim,
Ian Rogers, Zhengjun Xing, Kan Liang, linux-perf-users,
linux-kernel, Edward Baker
Update Alderlake and IcelakeX events to v1.19.
Developed on the perf-tools-next branch of:
git://git.kernel.org/pub/scm/linux/kernel/git/acme/linux.git
Ian Rogers (3):
perf vendor events intel: Update alderlake to v1.19
perf vendor events intel: Update alderlaken to v1.19
perf vendor events intel: Update icelakex to v1.19
.../pmu-events/arch/x86/alderlake/memory.json | 8 +++++
.../arch/x86/alderlake/pipeline.json | 10 ++++++
.../arch/x86/alderlaken/memory.json | 7 +++++
.../pmu-events/arch/x86/icelakex/cache.json | 8 +++++
.../arch/x86/icelakex/floating-point.json | 31 +++++++++++++++++++
.../arch/x86/icelakex/pipeline.json | 10 ++++++
tools/perf/pmu-events/arch/x86/mapfile.csv | 6 ++--
7 files changed, 77 insertions(+), 3 deletions(-)
--
2.39.2.637.g21b0678d19-goog
^ permalink raw reply [flat|nested] 5+ messages in thread
* [PATCH v1 1/3] perf vendor events intel: Update alderlake to v1.19
2023-02-23 5:53 [PATCH v1 0/3] Update Alderlake and IcelakeX events Ian Rogers
@ 2023-02-23 5:53 ` Ian Rogers
2023-02-23 5:53 ` [PATCH v1 2/3] perf vendor events intel: Update alderlaken " Ian Rogers
` (2 subsequent siblings)
3 siblings, 0 replies; 5+ messages in thread
From: Ian Rogers @ 2023-02-23 5:53 UTC (permalink / raw)
To: Peter Zijlstra, Ingo Molnar, Arnaldo Carvalho de Melo,
Mark Rutland, Alexander Shishkin, Jiri Olsa, Namhyung Kim,
Ian Rogers, Zhengjun Xing, Kan Liang, linux-perf-users,
linux-kernel, Edward Baker
Update alderlake perf json from v1.18 to v1.19.
Based on:
https://github.com/intel/perfmon/pull/58
perf json files created using:
https://github.com/intel/perfmon/blob/main/scripts/create_perf_json.py
Signed-off-by: Ian Rogers <irogers@google.com>
---
tools/perf/pmu-events/arch/x86/alderlake/memory.json | 8 ++++++++
tools/perf/pmu-events/arch/x86/alderlake/pipeline.json | 10 ++++++++++
tools/perf/pmu-events/arch/x86/mapfile.csv | 2 +-
3 files changed, 19 insertions(+), 1 deletion(-)
diff --git a/tools/perf/pmu-events/arch/x86/alderlake/memory.json b/tools/perf/pmu-events/arch/x86/alderlake/memory.json
index 37f3d062a788..55827b276e6e 100644
--- a/tools/perf/pmu-events/arch/x86/alderlake/memory.json
+++ b/tools/perf/pmu-events/arch/x86/alderlake/memory.json
@@ -24,6 +24,14 @@
"UMask": "0xf4",
"Unit": "cpu_atom"
},
+ {
+ "BriefDescription": "Counts the number of cycles that the head (oldest load) of the load buffer and retirement are both stalled due to a DL1 miss.",
+ "EventCode": "0x05",
+ "EventName": "LD_HEAD.L1_MISS_AT_RET",
+ "SampleAfterValue": "1000003",
+ "UMask": "0x81",
+ "Unit": "cpu_atom"
+ },
{
"BriefDescription": "Counts the number of cycles that the head (oldest load) of the load buffer and retirement are both stalled due to other block cases.",
"EventCode": "0x05",
diff --git a/tools/perf/pmu-events/arch/x86/alderlake/pipeline.json b/tools/perf/pmu-events/arch/x86/alderlake/pipeline.json
index 2dba3a115f97..f848530fbf07 100644
--- a/tools/perf/pmu-events/arch/x86/alderlake/pipeline.json
+++ b/tools/perf/pmu-events/arch/x86/alderlake/pipeline.json
@@ -361,6 +361,16 @@
"UMask": "0xeb",
"Unit": "cpu_atom"
},
+ {
+ "BriefDescription": "Miss-predicted near indirect branch instructions retired (excluding returns)",
+ "EventCode": "0xc5",
+ "EventName": "BR_MISP_RETIRED.INDIRECT",
+ "PEBS": "1",
+ "PublicDescription": "Counts miss-predicted near indirect branch instructions retired excluding returns. TSX abort is an indirect branch.",
+ "SampleAfterValue": "100003",
+ "UMask": "0x80",
+ "Unit": "cpu_core"
+ },
{
"BriefDescription": "Counts the number of mispredicted near indirect CALL branch instructions retired.",
"EventCode": "0xc5",
diff --git a/tools/perf/pmu-events/arch/x86/mapfile.csv b/tools/perf/pmu-events/arch/x86/mapfile.csv
index 1c6eef118e61..e69b29123327 100644
--- a/tools/perf/pmu-events/arch/x86/mapfile.csv
+++ b/tools/perf/pmu-events/arch/x86/mapfile.csv
@@ -1,5 +1,5 @@
Family-model,Version,Filename,EventType
-GenuineIntel-6-(97|9A|B7|BA|BF),v1.18,alderlake,core
+GenuineIntel-6-(97|9A|B7|BA|BF),v1.19,alderlake,core
GenuineIntel-6-BE,v1.18,alderlaken,core
GenuineIntel-6-(1C|26|27|35|36),v4,bonnell,core
GenuineIntel-6-(3D|47),v26,broadwell,core
--
2.39.2.637.g21b0678d19-goog
^ permalink raw reply related [flat|nested] 5+ messages in thread
* [PATCH v1 2/3] perf vendor events intel: Update alderlaken to v1.19
2023-02-23 5:53 [PATCH v1 0/3] Update Alderlake and IcelakeX events Ian Rogers
2023-02-23 5:53 ` [PATCH v1 1/3] perf vendor events intel: Update alderlake to v1.19 Ian Rogers
@ 2023-02-23 5:53 ` Ian Rogers
2023-02-23 5:53 ` [PATCH v1 3/3] perf vendor events intel: Update icelakex " Ian Rogers
2023-02-27 21:42 ` [PATCH v1 0/3] Update Alderlake and IcelakeX events Arnaldo Carvalho de Melo
3 siblings, 0 replies; 5+ messages in thread
From: Ian Rogers @ 2023-02-23 5:53 UTC (permalink / raw)
To: Peter Zijlstra, Ingo Molnar, Arnaldo Carvalho de Melo,
Mark Rutland, Alexander Shishkin, Jiri Olsa, Namhyung Kim,
Ian Rogers, Zhengjun Xing, Kan Liang, linux-perf-users,
linux-kernel, Edward Baker
Update alderlaken perf json from v1.18 to v1.19.
Based on:
https://github.com/intel/perfmon/pull/58
perf json files created using:
https://github.com/intel/perfmon/blob/main/scripts/create_perf_json.py
Signed-off-by: Ian Rogers <irogers@google.com>
---
tools/perf/pmu-events/arch/x86/alderlaken/memory.json | 7 +++++++
tools/perf/pmu-events/arch/x86/mapfile.csv | 2 +-
2 files changed, 8 insertions(+), 1 deletion(-)
diff --git a/tools/perf/pmu-events/arch/x86/alderlaken/memory.json b/tools/perf/pmu-events/arch/x86/alderlaken/memory.json
index f84bf8c43495..37259d38a222 100644
--- a/tools/perf/pmu-events/arch/x86/alderlaken/memory.json
+++ b/tools/perf/pmu-events/arch/x86/alderlaken/memory.json
@@ -13,6 +13,13 @@
"SampleAfterValue": "1000003",
"UMask": "0xf4"
},
+ {
+ "BriefDescription": "Counts the number of cycles that the head (oldest load) of the load buffer and retirement are both stalled due to a DL1 miss.",
+ "EventCode": "0x05",
+ "EventName": "LD_HEAD.L1_MISS_AT_RET",
+ "SampleAfterValue": "1000003",
+ "UMask": "0x81"
+ },
{
"BriefDescription": "Counts the number of cycles that the head (oldest load) of the load buffer and retirement are both stalled due to other block cases.",
"EventCode": "0x05",
diff --git a/tools/perf/pmu-events/arch/x86/mapfile.csv b/tools/perf/pmu-events/arch/x86/mapfile.csv
index e69b29123327..1c5776e37120 100644
--- a/tools/perf/pmu-events/arch/x86/mapfile.csv
+++ b/tools/perf/pmu-events/arch/x86/mapfile.csv
@@ -1,6 +1,6 @@
Family-model,Version,Filename,EventType
GenuineIntel-6-(97|9A|B7|BA|BF),v1.19,alderlake,core
-GenuineIntel-6-BE,v1.18,alderlaken,core
+GenuineIntel-6-BE,v1.19,alderlaken,core
GenuineIntel-6-(1C|26|27|35|36),v4,bonnell,core
GenuineIntel-6-(3D|47),v26,broadwell,core
GenuineIntel-6-56,v7,broadwellde,core
--
2.39.2.637.g21b0678d19-goog
^ permalink raw reply related [flat|nested] 5+ messages in thread
* [PATCH v1 3/3] perf vendor events intel: Update icelakex to v1.19
2023-02-23 5:53 [PATCH v1 0/3] Update Alderlake and IcelakeX events Ian Rogers
2023-02-23 5:53 ` [PATCH v1 1/3] perf vendor events intel: Update alderlake to v1.19 Ian Rogers
2023-02-23 5:53 ` [PATCH v1 2/3] perf vendor events intel: Update alderlaken " Ian Rogers
@ 2023-02-23 5:53 ` Ian Rogers
2023-02-27 21:42 ` [PATCH v1 0/3] Update Alderlake and IcelakeX events Arnaldo Carvalho de Melo
3 siblings, 0 replies; 5+ messages in thread
From: Ian Rogers @ 2023-02-23 5:53 UTC (permalink / raw)
To: Peter Zijlstra, Ingo Molnar, Arnaldo Carvalho de Melo,
Mark Rutland, Alexander Shishkin, Jiri Olsa, Namhyung Kim,
Ian Rogers, Zhengjun Xing, Kan Liang, linux-perf-users,
linux-kernel, Edward Baker
Update icelakex perf json from v1.18 to v1.19.
Based on:
https://github.com/intel/perfmon/pull/58
perf json files created using:
https://github.com/intel/perfmon/blob/main/scripts/create_perf_json.py
Signed-off-by: Ian Rogers <irogers@google.com>
---
.../pmu-events/arch/x86/icelakex/cache.json | 8 +++++
.../arch/x86/icelakex/floating-point.json | 31 +++++++++++++++++++
.../arch/x86/icelakex/pipeline.json | 10 ++++++
tools/perf/pmu-events/arch/x86/mapfile.csv | 2 +-
4 files changed, 50 insertions(+), 1 deletion(-)
diff --git a/tools/perf/pmu-events/arch/x86/icelakex/cache.json b/tools/perf/pmu-events/arch/x86/icelakex/cache.json
index d6463c8d9462..3bdc56a75097 100644
--- a/tools/perf/pmu-events/arch/x86/icelakex/cache.json
+++ b/tools/perf/pmu-events/arch/x86/icelakex/cache.json
@@ -825,6 +825,14 @@
"SampleAfterValue": "1000003",
"UMask": "0x1"
},
+ {
+ "BriefDescription": "Counts bus locks, accounts for cache line split locks and UC locks.",
+ "EventCode": "0xF4",
+ "EventName": "SQ_MISC.BUS_LOCK",
+ "PublicDescription": "Counts the more expensive bus lock needed to enforce cache coherency for certain memory accesses that need to be done atomically. Can be created by issuing an atomic instruction (via the LOCK prefix) which causes a cache line split or accesses uncacheable memory.",
+ "SampleAfterValue": "100003",
+ "UMask": "0x10"
+ },
{
"BriefDescription": "Cycles the queue waiting for offcore responses is full.",
"EventCode": "0xf4",
diff --git a/tools/perf/pmu-events/arch/x86/icelakex/floating-point.json b/tools/perf/pmu-events/arch/x86/icelakex/floating-point.json
index 655342dadac6..85c26c889088 100644
--- a/tools/perf/pmu-events/arch/x86/icelakex/floating-point.json
+++ b/tools/perf/pmu-events/arch/x86/icelakex/floating-point.json
@@ -39,6 +39,14 @@
"SampleAfterValue": "100003",
"UMask": "0x20"
},
+ {
+ "BriefDescription": "Number of SSE/AVX computational 128-bit packed single and 256-bit packed double precision FP instructions retired; some instructions will count twice as noted below. Each count represents 2 or/and 4 computation operations, 1 for each element. Applies to SSE* and AVX* packed single precision and packed double precision FP instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX RCP14 RSQRT14 SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB count twice as they perform 2 calculations per element.",
+ "EventCode": "0xc7",
+ "EventName": "FP_ARITH_INST_RETIRED.4_FLOPS",
+ "PublicDescription": "Number of SSE/AVX computational 128-bit packed single precision and 256-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 2 or/and 4 computation operations, one for each element. Applies to SSE* and AVX* packed single precision floating-point and packed double precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX RCP14 RSQRT14 SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.",
+ "SampleAfterValue": "100003",
+ "UMask": "0x18"
+ },
{
"BriefDescription": "Counts number of SSE/AVX computational 512-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 8 computation operations, one for each element. Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT14 RCP14 FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.",
"EventCode": "0xc7",
@@ -55,6 +63,22 @@
"SampleAfterValue": "100003",
"UMask": "0x80"
},
+ {
+ "BriefDescription": "Number of SSE/AVX computational 256-bit packed single precision and 512-bit packed double precision FP instructions retired; some instructions will count twice as noted below. Each count represents 8 computation operations, 1 for each element. Applies to SSE* and AVX* packed single precision and double precision FP instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT RSQRT RSQRT14 RCP RCP14 DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB count twice as they perform 2 calculations per element.",
+ "EventCode": "0xc7",
+ "EventName": "FP_ARITH_INST_RETIRED.8_FLOPS",
+ "PublicDescription": "Number of SSE/AVX computational 256-bit packed single precision and 512-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 8 computation operations, one for each element. Applies to SSE* and AVX* packed single precision and double precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT RSQRT RSQRT14 RCP RCP14 DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.",
+ "SampleAfterValue": "100003",
+ "UMask": "0x60"
+ },
+ {
+ "BriefDescription": "Number of SSE/AVX computational scalar floating-point instructions retired; some instructions will count twice as noted below. Applies to SSE* and AVX* scalar, double and single precision floating-point: ADD SUB MUL DIV MIN MAX RCP14 RSQRT14 SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element.",
+ "EventCode": "0xc7",
+ "EventName": "FP_ARITH_INST_RETIRED.SCALAR",
+ "PublicDescription": "Number of SSE/AVX computational scalar single precision and double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 1 computational operation. Applies to SSE* and AVX* scalar single precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT RCP FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.",
+ "SampleAfterValue": "1000003",
+ "UMask": "0x3"
+ },
{
"BriefDescription": "Counts number of SSE/AVX computational scalar double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 1 computational operation. Applies to SSE* and AVX* scalar double precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.",
"EventCode": "0xc7",
@@ -70,5 +94,12 @@
"PublicDescription": "Number of SSE/AVX computational scalar single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 1 computational operation. Applies to SSE* and AVX* scalar single precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT RCP FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.",
"SampleAfterValue": "100003",
"UMask": "0x2"
+ },
+ {
+ "BriefDescription": "Number of any Vector retired FP arithmetic instructions",
+ "EventCode": "0xc7",
+ "EventName": "FP_ARITH_INST_RETIRED.VECTOR",
+ "SampleAfterValue": "1000003",
+ "UMask": "0xfc"
}
]
diff --git a/tools/perf/pmu-events/arch/x86/icelakex/pipeline.json b/tools/perf/pmu-events/arch/x86/icelakex/pipeline.json
index 4cf16a1fcad4..442a4c7539dd 100644
--- a/tools/perf/pmu-events/arch/x86/icelakex/pipeline.json
+++ b/tools/perf/pmu-events/arch/x86/icelakex/pipeline.json
@@ -374,6 +374,16 @@
"SampleAfterValue": "2000003",
"UMask": "0x3"
},
+ {
+ "BriefDescription": "Clears speculative count",
+ "CounterMask": "1",
+ "EdgeDetect": "1",
+ "EventCode": "0x0D",
+ "EventName": "INT_MISC.CLEARS_COUNT",
+ "PublicDescription": "Counts the number of speculative clears due to any type of branch misprediction or machine clears",
+ "SampleAfterValue": "500009",
+ "UMask": "0x1"
+ },
{
"BriefDescription": "Counts cycles after recovery from a branch misprediction or machine clear till the first uop is issued from the resteered path.",
"EventCode": "0x0d",
diff --git a/tools/perf/pmu-events/arch/x86/mapfile.csv b/tools/perf/pmu-events/arch/x86/mapfile.csv
index 1c5776e37120..bb4e545fa100 100644
--- a/tools/perf/pmu-events/arch/x86/mapfile.csv
+++ b/tools/perf/pmu-events/arch/x86/mapfile.csv
@@ -13,7 +13,7 @@ GenuineIntel-6-A[DE],v1.00,graniterapids,core
GenuineIntel-6-(3C|45|46),v32,haswell,core
GenuineIntel-6-3F,v26,haswellx,core
GenuineIntel-6-(7D|7E|A7),v1.17,icelake,core
-GenuineIntel-6-6[AC],v1.18,icelakex,core
+GenuineIntel-6-6[AC],v1.19,icelakex,core
GenuineIntel-6-3A,v23,ivybridge,core
GenuineIntel-6-3E,v22,ivytown,core
GenuineIntel-6-2D,v22,jaketown,core
--
2.39.2.637.g21b0678d19-goog
^ permalink raw reply related [flat|nested] 5+ messages in thread
* Re: [PATCH v1 0/3] Update Alderlake and IcelakeX events
2023-02-23 5:53 [PATCH v1 0/3] Update Alderlake and IcelakeX events Ian Rogers
` (2 preceding siblings ...)
2023-02-23 5:53 ` [PATCH v1 3/3] perf vendor events intel: Update icelakex " Ian Rogers
@ 2023-02-27 21:42 ` Arnaldo Carvalho de Melo
3 siblings, 0 replies; 5+ messages in thread
From: Arnaldo Carvalho de Melo @ 2023-02-27 21:42 UTC (permalink / raw)
To: Ian Rogers
Cc: Peter Zijlstra, Ingo Molnar, Mark Rutland, Alexander Shishkin,
Jiri Olsa, Namhyung Kim, Zhengjun Xing, Kan Liang,
linux-perf-users, linux-kernel, Edward Baker
Em Wed, Feb 22, 2023 at 09:53:03PM -0800, Ian Rogers escreveu:
> Update Alderlake and IcelakeX events to v1.19.
>
> Developed on the perf-tools-next branch of:
> git://git.kernel.org/pub/scm/linux/kernel/git/acme/linux.git
Thanks, applied.
- Arnaldo
> Ian Rogers (3):
> perf vendor events intel: Update alderlake to v1.19
> perf vendor events intel: Update alderlaken to v1.19
> perf vendor events intel: Update icelakex to v1.19
>
> .../pmu-events/arch/x86/alderlake/memory.json | 8 +++++
> .../arch/x86/alderlake/pipeline.json | 10 ++++++
> .../arch/x86/alderlaken/memory.json | 7 +++++
> .../pmu-events/arch/x86/icelakex/cache.json | 8 +++++
> .../arch/x86/icelakex/floating-point.json | 31 +++++++++++++++++++
> .../arch/x86/icelakex/pipeline.json | 10 ++++++
> tools/perf/pmu-events/arch/x86/mapfile.csv | 6 ++--
> 7 files changed, 77 insertions(+), 3 deletions(-)
>
> --
> 2.39.2.637.g21b0678d19-goog
>
--
- Arnaldo
^ permalink raw reply [flat|nested] 5+ messages in thread
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2023-02-23 5:53 [PATCH v1 0/3] Update Alderlake and IcelakeX events Ian Rogers
2023-02-23 5:53 ` [PATCH v1 1/3] perf vendor events intel: Update alderlake to v1.19 Ian Rogers
2023-02-23 5:53 ` [PATCH v1 2/3] perf vendor events intel: Update alderlaken " Ian Rogers
2023-02-23 5:53 ` [PATCH v1 3/3] perf vendor events intel: Update icelakex " Ian Rogers
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