Re: [PATCH] perf pmu: Fix event list for uncore PMUs

Xing Zhengjun
2021-12-21T06:59:09Z

On 12/21/2021 12:34 AM, Liang, Kan wrote:
>
>
> On 12/20/2021 3:38 AM, John Garry wrote:
>> On 18/12/2021 01:47, Arnaldo Carvalho de Melo wrote:
>>>> Commit 0e0ae8742207 ("perf list: Display hybrid PMU events with cpu
>>>> type")
>>>> changed the list for uncore PMUs, such that duplicate aliases are now
>>>> listed per PMU (which they should not be), like:
>>>>
>>>> ./perf list
>>>> ...
>>>> unc_cbo_cache_lookup.any_es
>>>> [Unit: uncore_cbox L3 Lookup any request that access cache and found
>>>> line in E or S-state]
>>>> unc_cbo_cache_lookup.any_es
>>>> [Unit: uncore_cbox L3 Lookup any request that access cache and found
>>>> line in E or S-state]
>>>> unc_cbo_cache_lookup.any_i
>>>> [Unit: uncore_cbox L3 Lookup any request that access cache and found
>>>> line in I-state]
>>>> unc_cbo_cache_lookup.any_i
>>>> [Unit: uncore_cbox L3 Lookup any request that access cache and found
>>>> line in I-state]
>>>> ...
>>>>
>>>> Notice how the events are listed twice.
>>> Hi Jin,
>>>
>>>     Can I have your acked-by/tested-by?
>>
>> Hi Arnaldo,
>>
>> I assume that address is bouncing for you also.
>>
>
> Yes, Jin Yao has left Intel.
>
>> So if anyone else has one of these hybrid PMU x86 systems then it
>> would be appreciated to check this change.
>>
>
> + Zhengjun
>
> Zhengjun,
>
> Could you please help to verify the change?
>
> Thanks,
> Kan

Tested this patch on one hybrid PMU x86 system, it works OK.

Tested-by: Zhengjun Xing <zhengjun.xing@linux.intel.com>

--
Zhengjun Xing