* [PATCH 02/14] perf vendor events intel: Fix icelakex cstate metrics
2022-04-13 21:04 [PATCH 01/14] perf vendor events intel: Fix icelake cstate metrics Ian Rogers
@ 2022-04-13 21:04 ` Ian Rogers
2022-04-13 21:04 ` [PATCH 04/14] perf vendor events intel: Update CLX uncore to v1.14 Ian Rogers
` (12 subsequent siblings)
13 siblings, 0 replies; 19+ messages in thread
From: Ian Rogers @ 2022-04-13 21:04 UTC (permalink / raw)
To: Peter Zijlstra, Ingo Molnar, Arnaldo Carvalho de Melo,
Mark Rutland, Alexander Shishkin, Jiri Olsa, Namhyung Kim,
Maxime Coquelin, Alexandre Torgue, Kan Liang, Xing Zhengjun,
Andi Kleen, John Garry, James Clark, linux-kernel,
linux-perf-users
Cc: Ian Rogers
Apply cstate fix from:
https://github.com/intel/event-converter-for-linux-perf/
so that metrics for cstates that exist on the particular architecture
are generated. This corrects issues with metric testing.
Also correct topic of ASSISTS.ANY event.
Signed-off-by: Ian Rogers <irogers@google.com>
---
.../pmu-events/arch/x86/icelakex/cache.json | 31 +-------
.../arch/x86/icelakex/icx-metrics.json | 24 +------
.../pmu-events/arch/x86/icelakex/memory.json | 21 +-----
.../pmu-events/arch/x86/icelakex/other.json | 70 ++++---------------
.../arch/x86/icelakex/pipeline.json | 14 +++-
5 files changed, 33 insertions(+), 127 deletions(-)
diff --git a/tools/perf/pmu-events/arch/x86/icelakex/cache.json b/tools/perf/pmu-events/arch/x86/icelakex/cache.json
index 3c4da0371df9..95fcbec188f8 100644
--- a/tools/perf/pmu-events/arch/x86/icelakex/cache.json
+++ b/tools/perf/pmu-events/arch/x86/icelakex/cache.json
@@ -665,7 +665,6 @@
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3F803C0004",
"Offcore": "1",
- "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
@@ -677,7 +676,6 @@
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x10003C0004",
"Offcore": "1",
- "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
@@ -689,7 +687,6 @@
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x1008000004",
"Offcore": "1",
- "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
@@ -701,7 +698,6 @@
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x808000004",
"Offcore": "1",
- "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
@@ -713,7 +709,6 @@
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3F803C0001",
"Offcore": "1",
- "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
@@ -725,7 +720,6 @@
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x10003C0001",
"Offcore": "1",
- "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
@@ -737,7 +731,6 @@
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x4003C0001",
"Offcore": "1",
- "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
@@ -749,7 +742,6 @@
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x8003C0001",
"Offcore": "1",
- "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
@@ -761,7 +753,6 @@
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x1030000001",
"Offcore": "1",
- "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
@@ -773,7 +764,6 @@
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x830000001",
"Offcore": "1",
- "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
@@ -785,7 +775,6 @@
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x1008000001",
"Offcore": "1",
- "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
@@ -797,7 +786,6 @@
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x808000001",
"Offcore": "1",
- "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
@@ -809,7 +797,6 @@
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3F803C0002",
"Offcore": "1",
- "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
@@ -821,7 +808,6 @@
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x10003C0002",
"Offcore": "1",
- "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
@@ -833,7 +819,6 @@
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x1008000002",
"Offcore": "1",
- "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
@@ -845,7 +830,6 @@
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x808000002",
"Offcore": "1",
- "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
@@ -857,7 +841,6 @@
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3F803C0400",
"Offcore": "1",
- "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
@@ -869,7 +852,6 @@
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x80082380",
"Offcore": "1",
- "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
@@ -881,7 +863,6 @@
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3F803C27F0",
"Offcore": "1",
- "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
@@ -893,7 +874,6 @@
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3F003C0477",
"Offcore": "1",
- "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
@@ -905,7 +885,6 @@
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x10003C0477",
"Offcore": "1",
- "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
@@ -917,7 +896,6 @@
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x4003C0477",
"Offcore": "1",
- "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
@@ -929,7 +907,6 @@
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x8003C0477",
"Offcore": "1",
- "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
@@ -941,7 +918,6 @@
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x1830000477",
"Offcore": "1",
- "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
@@ -953,7 +929,6 @@
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x1030000477",
"Offcore": "1",
- "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
@@ -965,7 +940,6 @@
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x830000477",
"Offcore": "1",
- "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
@@ -977,7 +951,6 @@
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x1008000477",
"Offcore": "1",
- "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
@@ -989,7 +962,6 @@
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x808000477",
"Offcore": "1",
- "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
@@ -1001,7 +973,6 @@
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x80080800",
"Offcore": "1",
- "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
@@ -1200,4 +1171,4 @@
"Speculative": "1",
"UMask": "0x4"
}
-]
\ No newline at end of file
+]
diff --git a/tools/perf/pmu-events/arch/x86/icelakex/icx-metrics.json b/tools/perf/pmu-events/arch/x86/icelakex/icx-metrics.json
index a737fa40feb0..be70672bfdb0 100644
--- a/tools/perf/pmu-events/arch/x86/icelakex/icx-metrics.json
+++ b/tools/perf/pmu-events/arch/x86/icelakex/icx-metrics.json
@@ -475,10 +475,10 @@
"MetricName": "IpFarBranch"
},
{
- "BriefDescription": "C3 residency percent per core",
- "MetricExpr": "(cstate_core@c3\\-residency@ / msr@tsc@) * 100",
+ "BriefDescription": "C1 residency percent per core",
+ "MetricExpr": "(cstate_core@c1\\-residency@ / msr@tsc@) * 100",
"MetricGroup": "Power",
- "MetricName": "C3_Core_Residency"
+ "MetricName": "C1_Core_Residency"
},
{
"BriefDescription": "C6 residency percent per core",
@@ -486,34 +486,16 @@
"MetricGroup": "Power",
"MetricName": "C6_Core_Residency"
},
- {
- "BriefDescription": "C7 residency percent per core",
- "MetricExpr": "(cstate_core@c7\\-residency@ / msr@tsc@) * 100",
- "MetricGroup": "Power",
- "MetricName": "C7_Core_Residency"
- },
{
"BriefDescription": "C2 residency percent per package",
"MetricExpr": "(cstate_pkg@c2\\-residency@ / msr@tsc@) * 100",
"MetricGroup": "Power",
"MetricName": "C2_Pkg_Residency"
},
- {
- "BriefDescription": "C3 residency percent per package",
- "MetricExpr": "(cstate_pkg@c3\\-residency@ / msr@tsc@) * 100",
- "MetricGroup": "Power",
- "MetricName": "C3_Pkg_Residency"
- },
{
"BriefDescription": "C6 residency percent per package",
"MetricExpr": "(cstate_pkg@c6\\-residency@ / msr@tsc@) * 100",
"MetricGroup": "Power",
"MetricName": "C6_Pkg_Residency"
- },
- {
- "BriefDescription": "C7 residency percent per package",
- "MetricExpr": "(cstate_pkg@c7\\-residency@ / msr@tsc@) * 100",
- "MetricGroup": "Power",
- "MetricName": "C7_Pkg_Residency"
}
]
diff --git a/tools/perf/pmu-events/arch/x86/icelakex/memory.json b/tools/perf/pmu-events/arch/x86/icelakex/memory.json
index c10a1bbc66b1..58b03a8a1b95 100644
--- a/tools/perf/pmu-events/arch/x86/icelakex/memory.json
+++ b/tools/perf/pmu-events/arch/x86/icelakex/memory.json
@@ -159,7 +159,6 @@
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3FBFC00004",
"Offcore": "1",
- "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
@@ -171,7 +170,6 @@
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3F84400004",
"Offcore": "1",
- "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
@@ -183,7 +181,6 @@
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3FBFC00001",
"Offcore": "1",
- "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
@@ -195,7 +192,6 @@
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3F84400001",
"Offcore": "1",
- "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
@@ -207,7 +203,6 @@
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3F3FC00002",
"Offcore": "1",
- "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
@@ -219,7 +214,6 @@
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3F04400002",
"Offcore": "1",
- "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
@@ -231,7 +225,6 @@
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3FBFC00400",
"Offcore": "1",
- "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
@@ -243,7 +236,6 @@
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3F84400400",
"Offcore": "1",
- "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
@@ -255,7 +247,6 @@
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x94002380",
"Offcore": "1",
- "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
@@ -267,7 +258,6 @@
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x84002380",
"Offcore": "1",
- "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
@@ -279,7 +269,6 @@
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x84000002",
"Offcore": "1",
- "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
@@ -291,7 +280,6 @@
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3FBFC08000",
"Offcore": "1",
- "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
@@ -303,7 +291,6 @@
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3F84408000",
"Offcore": "1",
- "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
@@ -315,7 +302,6 @@
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3F844027F0",
"Offcore": "1",
- "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
@@ -327,7 +313,6 @@
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3F3FC00477",
"Offcore": "1",
- "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
@@ -339,7 +324,6 @@
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3F04400477",
"Offcore": "1",
- "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
@@ -351,7 +335,6 @@
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x70CC00477",
"Offcore": "1",
- "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
@@ -363,7 +346,6 @@
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x94000800",
"Offcore": "1",
- "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
@@ -375,7 +357,6 @@
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x84000800",
"Offcore": "1",
- "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
@@ -565,4 +546,4 @@
"Speculative": "1",
"UMask": "0x1"
}
-]
\ No newline at end of file
+]
diff --git a/tools/perf/pmu-events/arch/x86/icelakex/other.json b/tools/perf/pmu-events/arch/x86/icelakex/other.json
index 1246b22769da..c9bf6808ead7 100644
--- a/tools/perf/pmu-events/arch/x86/icelakex/other.json
+++ b/tools/perf/pmu-events/arch/x86/icelakex/other.json
@@ -1,16 +1,4 @@
[
- {
- "BriefDescription": "Number of occurrences where a microcode assist is invoked by hardware.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3,4,5,6,7",
- "EventCode": "0xc1",
- "EventName": "ASSISTS.ANY",
- "PEBScounters": "0,1,2,3,4,5,6,7",
- "PublicDescription": "Counts the number of occurrences where a microcode assist is invoked by hardware Examples include AD (page Access Dirty), FP and AVX related assists.",
- "SampleAfterValue": "100003",
- "Speculative": "1",
- "UMask": "0x7"
- },
{
"BriefDescription": "Core cycles where the core was running in a manner where Turbo may be clipped to the Non-AVX turbo schedule.",
"CollectPEBSRecord": "2",
@@ -139,7 +127,6 @@
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x10004",
"Offcore": "1",
- "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
@@ -151,7 +138,6 @@
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x73C000004",
"Offcore": "1",
- "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
@@ -163,7 +149,6 @@
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x104000004",
"Offcore": "1",
- "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
@@ -175,7 +160,6 @@
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x708000004",
"Offcore": "1",
- "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
@@ -187,7 +171,6 @@
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x10001",
"Offcore": "1",
- "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
@@ -199,7 +182,6 @@
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x73C000001",
"Offcore": "1",
- "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
@@ -211,7 +193,6 @@
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x104000001",
"Offcore": "1",
- "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
@@ -223,7 +204,6 @@
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x100400001",
"Offcore": "1",
- "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
@@ -235,7 +215,6 @@
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x703C00001",
"Offcore": "1",
- "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
@@ -247,7 +226,6 @@
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x730000001",
"Offcore": "1",
- "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
@@ -259,7 +237,6 @@
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x703000001",
"Offcore": "1",
- "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
@@ -271,19 +248,17 @@
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x708000001",
"Offcore": "1",
- "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
- "BriefDescription": "Counts demand data reads that (IC) were supplied by PMM on a distant memory controller of this socket when the system is in SNC (sub-NUMA cluster) mode.",
+ "BriefDescription": "Counts demand data reads that were supplied by PMM on a distant memory controller of this socket when the system is in SNC (sub-NUMA cluster) mode.",
"Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.DEMAND_DATA_RD.SNC_PMM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x700800001",
"Offcore": "1",
- "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
@@ -295,7 +270,6 @@
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3F3FFC0002",
"Offcore": "1",
- "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
@@ -307,7 +281,6 @@
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x73C000002",
"Offcore": "1",
- "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
@@ -319,7 +292,6 @@
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x104000002",
"Offcore": "1",
- "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
@@ -331,7 +303,6 @@
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x100400002",
"Offcore": "1",
- "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
@@ -343,7 +314,6 @@
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x703C00002",
"Offcore": "1",
- "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
@@ -355,7 +325,6 @@
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x703000002",
"Offcore": "1",
- "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
@@ -367,19 +336,17 @@
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x708000002",
"Offcore": "1",
- "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
- "BriefDescription": "Counts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that (IC) were supplied by PMM on a distant memory controller of this socket when the system is in SNC (sub-NUMA cluster) mode.",
+ "BriefDescription": "Counts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that were supplied by PMM on a distant memory controller of this socket when the system is in SNC (sub-NUMA cluster) mode.",
"Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.DEMAND_RFO.SNC_PMM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x700800002",
"Offcore": "1",
- "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
@@ -391,7 +358,6 @@
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x73C000400",
"Offcore": "1",
- "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
@@ -403,7 +369,17 @@
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x104000400",
"Offcore": "1",
- "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
+ "SampleAfterValue": "100003",
+ "UMask": "0x1"
+ },
+ {
+ "BriefDescription": "Counts hardware prefetch (which bring data to L2) that have any type of response.",
+ "Counter": "0,1,2,3",
+ "EventCode": "0xB7, 0xBB",
+ "EventName": "OCR.HWPF_L2.ANY_RESPONSE",
+ "MSRIndex": "0x1a6,0x1a7",
+ "MSRValue": "0x10070",
+ "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
@@ -415,7 +391,6 @@
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x12380",
"Offcore": "1",
- "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
@@ -427,7 +402,6 @@
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x90002380",
"Offcore": "1",
- "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
@@ -439,7 +413,6 @@
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x90000002",
"Offcore": "1",
- "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
@@ -451,7 +424,6 @@
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x18000",
"Offcore": "1",
- "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
@@ -463,7 +435,6 @@
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3F3FFC0477",
"Offcore": "1",
- "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
@@ -475,7 +446,6 @@
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x73C000477",
"Offcore": "1",
- "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
@@ -487,7 +457,6 @@
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x104000477",
"Offcore": "1",
- "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
@@ -499,7 +468,6 @@
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x100400477",
"Offcore": "1",
- "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
@@ -511,7 +479,6 @@
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x70C000477",
"Offcore": "1",
- "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
@@ -523,7 +490,6 @@
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x700C00477",
"Offcore": "1",
- "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
@@ -535,7 +501,6 @@
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3F33000477",
"Offcore": "1",
- "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
@@ -547,7 +512,6 @@
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x730000477",
"Offcore": "1",
- "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
@@ -559,7 +523,6 @@
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x703000477",
"Offcore": "1",
- "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
@@ -571,19 +534,17 @@
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x708000477",
"Offcore": "1",
- "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
- "BriefDescription": "Counts all data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that (IC) were supplied by PMM on a distant memory controller of this socket when the system is in SNC (sub-NUMA cluster) mode.",
+ "BriefDescription": "Counts all data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were supplied by PMM on a distant memory controller of this socket when the system is in SNC (sub-NUMA cluster) mode.",
"Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.READS_TO_CORE.SNC_PMM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x700800477",
"Offcore": "1",
- "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
@@ -595,8 +556,7 @@
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x10800",
"Offcore": "1",
- "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
"SampleAfterValue": "100003",
"UMask": "0x1"
}
-]
\ No newline at end of file
+]
diff --git a/tools/perf/pmu-events/arch/x86/icelakex/pipeline.json b/tools/perf/pmu-events/arch/x86/icelakex/pipeline.json
index 068a3d46b443..95c1008ef057 100644
--- a/tools/perf/pmu-events/arch/x86/icelakex/pipeline.json
+++ b/tools/perf/pmu-events/arch/x86/icelakex/pipeline.json
@@ -12,6 +12,18 @@
"Speculative": "1",
"UMask": "0x9"
},
+ {
+ "BriefDescription": "Number of occurrences where a microcode assist is invoked by hardware.",
+ "CollectPEBSRecord": "2",
+ "Counter": "0,1,2,3,4,5,6,7",
+ "EventCode": "0xc1",
+ "EventName": "ASSISTS.ANY",
+ "PEBScounters": "0,1,2,3,4,5,6,7",
+ "PublicDescription": "Counts the number of occurrences where a microcode assist is invoked by hardware Examples include AD (page Access Dirty), FP and AVX related assists.",
+ "SampleAfterValue": "100003",
+ "Speculative": "1",
+ "UMask": "0x7"
+ },
{
"BriefDescription": "All branch instructions retired.",
"CollectPEBSRecord": "2",
@@ -1076,4 +1088,4 @@
"SampleAfterValue": "1000003",
"UMask": "0x2"
}
-]
\ No newline at end of file
+]
--
2.36.0.rc0.470.gd361397f0d-goog
^ permalink raw reply related [flat|nested] 19+ messages in thread
* [PATCH 04/14] perf vendor events intel: Update CLX uncore to v1.14
2022-04-13 21:04 [PATCH 01/14] perf vendor events intel: Fix icelake cstate metrics Ian Rogers
2022-04-13 21:04 ` [PATCH 02/14] perf vendor events intel: Fix icelakex " Ian Rogers
@ 2022-04-13 21:04 ` Ian Rogers
2022-04-13 21:04 ` [PATCH 05/14] perf vendor events intel: Update SKX uncore Ian Rogers
` (11 subsequent siblings)
13 siblings, 0 replies; 19+ messages in thread
From: Ian Rogers @ 2022-04-13 21:04 UTC (permalink / raw)
To: Peter Zijlstra, Ingo Molnar, Arnaldo Carvalho de Melo,
Mark Rutland, Alexander Shishkin, Jiri Olsa, Namhyung Kim,
Maxime Coquelin, Alexandre Torgue, Kan Liang, Xing Zhengjun,
Andi Kleen, John Garry, James Clark, linux-kernel,
linux-perf-users
Cc: Ian Rogers
JSON uncore events are generated for CascadeLake Server for v1.14
with events from:
https://download.01.org/perfmon/CLX/
New event names are added, that match the original json names,
due to an update to:
https://github.com/intel/event-converter-for-linux-perf/
Signed-off-by: Ian Rogers <irogers@google.com>
---
.../arch/x86/cascadelakex/uncore-memory.json | 61 ++++++++++++
.../arch/x86/cascadelakex/uncore-other.json | 92 +++++++++++++++++++
2 files changed, 153 insertions(+)
diff --git a/tools/perf/pmu-events/arch/x86/cascadelakex/uncore-memory.json b/tools/perf/pmu-events/arch/x86/cascadelakex/uncore-memory.json
index 2600fd8d7a54..a416515d41da 100644
--- a/tools/perf/pmu-events/arch/x86/cascadelakex/uncore-memory.json
+++ b/tools/perf/pmu-events/arch/x86/cascadelakex/uncore-memory.json
@@ -9,6 +9,16 @@
"UMask": "0x3",
"Unit": "iMC"
},
+ {
+ "BriefDescription": "read requests to memory controller",
+ "Counter": "0,1,2,3",
+ "EventCode": "0x4",
+ "EventName": "UNC_M_CAS_COUNT.RD",
+ "PerPkg": "1",
+ "ScaleUnit": "64Bytes",
+ "UMask": "0x3",
+ "Unit": "iMC"
+ },
{
"BriefDescription": "write requests to memory controller. Derived from unc_m_cas_count.wr",
"Counter": "0,1,2,3",
@@ -19,6 +29,16 @@
"UMask": "0xC",
"Unit": "iMC"
},
+ {
+ "BriefDescription": "write requests to memory controller",
+ "Counter": "0,1,2,3",
+ "EventCode": "0x4",
+ "EventName": "UNC_M_CAS_COUNT.WR",
+ "PerPkg": "1",
+ "ScaleUnit": "64Bytes",
+ "UMask": "0xC",
+ "Unit": "iMC"
+ },
{
"BriefDescription": "Memory controller clock ticks",
"Counter": "0,1,2,3",
@@ -89,6 +109,15 @@
"ScaleUnit": "6.103515625E-5MB/sec",
"Unit": "iMC"
},
+ {
+ "BriefDescription": "Intel Optane DC persistent memory bandwidth read (MB/sec)",
+ "Counter": "0,1,2,3",
+ "EventCode": "0xE3",
+ "EventName": "UNC_M_PMM_RPQ_INSERTS",
+ "PerPkg": "1",
+ "ScaleUnit": "6.103515625E-5MB/sec",
+ "Unit": "iMC"
+ },
{
"BriefDescription": "Intel Optane DC persistent memory bandwidth write (MB/sec). Derived from unc_m_pmm_wpq_inserts",
"Counter": "0,1,2,3",
@@ -98,6 +127,15 @@
"ScaleUnit": "6.103515625E-5MB/sec",
"Unit": "iMC"
},
+ {
+ "BriefDescription": "Intel Optane DC persistent memory bandwidth write (MB/sec)",
+ "Counter": "0,1,2,3",
+ "EventCode": "0xE7",
+ "EventName": "UNC_M_PMM_WPQ_INSERTS",
+ "PerPkg": "1",
+ "ScaleUnit": "6.103515625E-5MB/sec",
+ "Unit": "iMC"
+ },
{
"BriefDescription": "Intel Optane DC persistent memory bandwidth total (MB/sec). Derived from unc_m_pmm_rpq_inserts",
"Counter": "0,1,2,3",
@@ -109,6 +147,17 @@
"ScaleUnit": "6.103515625E-5MB/sec",
"Unit": "iMC"
},
+ {
+ "BriefDescription": "Intel Optane DC persistent memory bandwidth total (MB/sec)",
+ "Counter": "0,1,2,3",
+ "EventCode": "0xE3",
+ "EventName": "UNC_M_PMM_RPQ_INSERTS",
+ "MetricExpr": "UNC_M_PMM_RPQ_INSERTS + UNC_M_PMM_WPQ_INSERTS",
+ "MetricName": "UNC_M_PMM_BANDWIDTH.TOTAL",
+ "PerPkg": "1",
+ "ScaleUnit": "6.103515625E-5MB/sec",
+ "Unit": "iMC"
+ },
{
"BriefDescription": "Read Pending Queue Occupancy of all read requests for Intel Optane DC persistent memory",
"Counter": "0,1,2,3",
@@ -130,6 +179,18 @@
"UMask": "0x1",
"Unit": "iMC"
},
+ {
+ "BriefDescription": "Intel Optane DC persistent memory read latency (ns)",
+ "Counter": "0,1,2,3",
+ "EventCode": "0xE0",
+ "EventName": "UNC_M_PMM_RPQ_OCCUPANCY.ALL",
+ "MetricExpr": "UNC_M_PMM_RPQ_OCCUPANCY.ALL / UNC_M_PMM_RPQ_INSERTS / UNC_M_CLOCKTICKS",
+ "MetricName": "UNC_M_PMM_READ_LATENCY",
+ "PerPkg": "1",
+ "ScaleUnit": "6000000000ns",
+ "UMask": "0x1",
+ "Unit": "iMC"
+ },
{
"BriefDescription": "DRAM Page Activate commands sent due to a write request",
"Counter": "0,1,2,3",
diff --git a/tools/perf/pmu-events/arch/x86/cascadelakex/uncore-other.json b/tools/perf/pmu-events/arch/x86/cascadelakex/uncore-other.json
index 7f1cf4d8f0fa..03575ef9f4c3 100644
--- a/tools/perf/pmu-events/arch/x86/cascadelakex/uncore-other.json
+++ b/tools/perf/pmu-events/arch/x86/cascadelakex/uncore-other.json
@@ -16,6 +16,16 @@
"UMask": "0x21",
"Unit": "CHA"
},
+ {
+ "BriefDescription": "LLC misses - Uncacheable reads (from cpu) ",
+ "Counter": "0,1,2,3",
+ "EventCode": "0x35",
+ "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS",
+ "Filter": "config1=0x40e33",
+ "PerPkg": "1",
+ "UMask": "0x21",
+ "Unit": "CHA"
+ },
{
"BriefDescription": "MMIO reads. Derived from unc_cha_tor_inserts.ia_miss",
"Counter": "0,1,2,3",
@@ -26,6 +36,16 @@
"UMask": "0x21",
"Unit": "CHA"
},
+ {
+ "BriefDescription": "MMIO reads",
+ "Counter": "0,1,2,3",
+ "EventCode": "0x35",
+ "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS",
+ "Filter": "config1=0x40040e33",
+ "PerPkg": "1",
+ "UMask": "0x21",
+ "Unit": "CHA"
+ },
{
"BriefDescription": "MMIO writes. Derived from unc_cha_tor_inserts.ia_miss",
"Counter": "0,1,2,3",
@@ -36,6 +56,16 @@
"UMask": "0x21",
"Unit": "CHA"
},
+ {
+ "BriefDescription": "MMIO writes",
+ "Counter": "0,1,2,3",
+ "EventCode": "0x35",
+ "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS",
+ "Filter": "config1=0x40041e33",
+ "PerPkg": "1",
+ "UMask": "0x21",
+ "Unit": "CHA"
+ },
{
"BriefDescription": "Streaming stores (full cache line). Derived from unc_cha_tor_inserts.ia_miss",
"Counter": "0,1,2,3",
@@ -47,6 +77,17 @@
"UMask": "0x21",
"Unit": "CHA"
},
+ {
+ "BriefDescription": "Streaming stores (full cache line)",
+ "Counter": "0,1,2,3",
+ "EventCode": "0x35",
+ "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS",
+ "Filter": "config1=0x41833",
+ "PerPkg": "1",
+ "ScaleUnit": "64Bytes",
+ "UMask": "0x21",
+ "Unit": "CHA"
+ },
{
"BriefDescription": "Streaming stores (partial cache line). Derived from unc_cha_tor_inserts.ia_miss",
"Counter": "0,1,2,3",
@@ -58,6 +99,17 @@
"UMask": "0x21",
"Unit": "CHA"
},
+ {
+ "BriefDescription": "Streaming stores (partial cache line)",
+ "Counter": "0,1,2,3",
+ "EventCode": "0x35",
+ "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS",
+ "Filter": "config1=0x41a33",
+ "PerPkg": "1",
+ "ScaleUnit": "64Bytes",
+ "UMask": "0x21",
+ "Unit": "CHA"
+ },
{
"BriefDescription": "read requests from home agent",
"Counter": "0,1,2,3",
@@ -113,6 +165,16 @@
"UMask": "0xf",
"Unit": "UPI LL"
},
+ {
+ "BriefDescription": "UPI interconnect send bandwidth for payload",
+ "Counter": "0,1,2,3",
+ "EventCode": "0x2",
+ "EventName": "UNC_UPI_TxL_FLITS.ALL_DATA",
+ "PerPkg": "1",
+ "ScaleUnit": "7.11E-06Bytes",
+ "UMask": "0xf",
+ "Unit": "UPI LL"
+ },
{
"BriefDescription": "PCI Express bandwidth writing at IIO, part 0",
"Counter": "0,1",
@@ -176,6 +238,21 @@
"UMask": "0x01",
"Unit": "IIO"
},
+ {
+ "BriefDescription": "PCI Express bandwidth writing at IIO",
+ "Counter": "0,1",
+ "EventCode": "0x83",
+ "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART0",
+ "FCMask": "0x07",
+ "Filter": "ch_mask=0x1f",
+ "MetricExpr": "UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART0 + UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART1 + UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART2 + UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART3",
+ "MetricName": "LLC_MISSES.PCIE_WRITE",
+ "PerPkg": "1",
+ "PortMask": "0x01",
+ "ScaleUnit": "4Bytes",
+ "UMask": "0x01",
+ "Unit": "IIO"
+ },
{
"BriefDescription": "PCI Express bandwidth reading at IIO, part 0",
"Counter": "0,1",
@@ -239,6 +316,21 @@
"UMask": "0x04",
"Unit": "IIO"
},
+ {
+ "BriefDescription": "PCI Express bandwidth reading at IIO",
+ "Counter": "0,1",
+ "EventCode": "0x83",
+ "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART0",
+ "FCMask": "0x07",
+ "Filter": "ch_mask=0x1f",
+ "MetricExpr": "UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART0 + UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART1 + UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART2 + UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART3",
+ "MetricName": "LLC_MISSES.PCIE_READ",
+ "PerPkg": "1",
+ "PortMask": "0x01",
+ "ScaleUnit": "4Bytes",
+ "UMask": "0x04",
+ "Unit": "IIO"
+ },
{
"BriefDescription": "Core Cross Snoops Issued; Multiple Core Requests",
"Counter": "0,1,2,3",
--
2.36.0.rc0.470.gd361397f0d-goog
^ permalink raw reply related [flat|nested] 19+ messages in thread
* [PATCH 05/14] perf vendor events intel: Update SKX uncore
2022-04-13 21:04 [PATCH 01/14] perf vendor events intel: Fix icelake cstate metrics Ian Rogers
2022-04-13 21:04 ` [PATCH 02/14] perf vendor events intel: Fix icelakex " Ian Rogers
2022-04-13 21:04 ` [PATCH 04/14] perf vendor events intel: Update CLX uncore to v1.14 Ian Rogers
@ 2022-04-13 21:04 ` Ian Rogers
2022-04-13 21:04 ` [PATCH 06/14] perf vendor events intel: Update nehalemep event topics Ian Rogers
` (10 subsequent siblings)
13 siblings, 0 replies; 19+ messages in thread
From: Ian Rogers @ 2022-04-13 21:04 UTC (permalink / raw)
To: Peter Zijlstra, Ingo Molnar, Arnaldo Carvalho de Melo,
Mark Rutland, Alexander Shishkin, Jiri Olsa, Namhyung Kim,
Maxime Coquelin, Alexandre Torgue, Kan Liang, Xing Zhengjun,
Andi Kleen, John Garry, James Clark, linux-kernel,
linux-perf-users
Cc: Ian Rogers
JSON uncore events are generated for Skylake Server for v1.26
with events from:
https://download.01.org/perfmon/SKX/
New event names are added, that match the original json names,
due to an update to:
https://github.com/intel/event-converter-for-linux-perf/
Signed-off-by: Ian Rogers <irogers@google.com>
---
.../arch/x86/skylakex/uncore-memory.json | 20 ++++
.../arch/x86/skylakex/uncore-other.json | 92 +++++++++++++++++++
2 files changed, 112 insertions(+)
diff --git a/tools/perf/pmu-events/arch/x86/skylakex/uncore-memory.json b/tools/perf/pmu-events/arch/x86/skylakex/uncore-memory.json
index 0b66e6af8177..4dcbac887380 100644
--- a/tools/perf/pmu-events/arch/x86/skylakex/uncore-memory.json
+++ b/tools/perf/pmu-events/arch/x86/skylakex/uncore-memory.json
@@ -9,6 +9,16 @@
"UMask": "0x3",
"Unit": "iMC"
},
+ {
+ "BriefDescription": "read requests to memory controller",
+ "Counter": "0,1,2,3",
+ "EventCode": "0x4",
+ "EventName": "UNC_M_CAS_COUNT.RD",
+ "PerPkg": "1",
+ "ScaleUnit": "64Bytes",
+ "UMask": "0x3",
+ "Unit": "iMC"
+ },
{
"BriefDescription": "write requests to memory controller. Derived from unc_m_cas_count.wr",
"Counter": "0,1,2,3",
@@ -19,6 +29,16 @@
"UMask": "0xC",
"Unit": "iMC"
},
+ {
+ "BriefDescription": "write requests to memory controller",
+ "Counter": "0,1,2,3",
+ "EventCode": "0x4",
+ "EventName": "UNC_M_CAS_COUNT.WR",
+ "PerPkg": "1",
+ "ScaleUnit": "64Bytes",
+ "UMask": "0xC",
+ "Unit": "iMC"
+ },
{
"BriefDescription": "Memory controller clock ticks",
"Counter": "0,1,2,3",
diff --git a/tools/perf/pmu-events/arch/x86/skylakex/uncore-other.json b/tools/perf/pmu-events/arch/x86/skylakex/uncore-other.json
index 06c5ca26ca3f..567d86434839 100644
--- a/tools/perf/pmu-events/arch/x86/skylakex/uncore-other.json
+++ b/tools/perf/pmu-events/arch/x86/skylakex/uncore-other.json
@@ -16,6 +16,16 @@
"UMask": "0x21",
"Unit": "CHA"
},
+ {
+ "BriefDescription": "LLC misses - Uncacheable reads (from cpu) ",
+ "Counter": "0,1,2,3",
+ "EventCode": "0x35",
+ "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS",
+ "Filter": "config1=0x40e33",
+ "PerPkg": "1",
+ "UMask": "0x21",
+ "Unit": "CHA"
+ },
{
"BriefDescription": "MMIO reads. Derived from unc_cha_tor_inserts.ia_miss",
"Counter": "0,1,2,3",
@@ -26,6 +36,16 @@
"UMask": "0x21",
"Unit": "CHA"
},
+ {
+ "BriefDescription": "MMIO reads",
+ "Counter": "0,1,2,3",
+ "EventCode": "0x35",
+ "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS",
+ "Filter": "config1=0x40040e33",
+ "PerPkg": "1",
+ "UMask": "0x21",
+ "Unit": "CHA"
+ },
{
"BriefDescription": "MMIO writes. Derived from unc_cha_tor_inserts.ia_miss",
"Counter": "0,1,2,3",
@@ -36,6 +56,16 @@
"UMask": "0x21",
"Unit": "CHA"
},
+ {
+ "BriefDescription": "MMIO writes",
+ "Counter": "0,1,2,3",
+ "EventCode": "0x35",
+ "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS",
+ "Filter": "config1=0x40041e33",
+ "PerPkg": "1",
+ "UMask": "0x21",
+ "Unit": "CHA"
+ },
{
"BriefDescription": "Streaming stores (full cache line). Derived from unc_cha_tor_inserts.ia_miss",
"Counter": "0,1,2,3",
@@ -47,6 +77,17 @@
"UMask": "0x21",
"Unit": "CHA"
},
+ {
+ "BriefDescription": "Streaming stores (full cache line)",
+ "Counter": "0,1,2,3",
+ "EventCode": "0x35",
+ "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS",
+ "Filter": "config1=0x41833",
+ "PerPkg": "1",
+ "ScaleUnit": "64Bytes",
+ "UMask": "0x21",
+ "Unit": "CHA"
+ },
{
"BriefDescription": "Streaming stores (partial cache line). Derived from unc_cha_tor_inserts.ia_miss",
"Counter": "0,1,2,3",
@@ -58,6 +99,17 @@
"UMask": "0x21",
"Unit": "CHA"
},
+ {
+ "BriefDescription": "Streaming stores (partial cache line)",
+ "Counter": "0,1,2,3",
+ "EventCode": "0x35",
+ "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS",
+ "Filter": "config1=0x41a33",
+ "PerPkg": "1",
+ "ScaleUnit": "64Bytes",
+ "UMask": "0x21",
+ "Unit": "CHA"
+ },
{
"BriefDescription": "read requests from home agent",
"Counter": "0,1,2,3",
@@ -113,6 +165,16 @@
"UMask": "0xf",
"Unit": "UPI LL"
},
+ {
+ "BriefDescription": "UPI interconnect send bandwidth for payload",
+ "Counter": "0,1,2,3",
+ "EventCode": "0x2",
+ "EventName": "UNC_UPI_TxL_FLITS.ALL_DATA",
+ "PerPkg": "1",
+ "ScaleUnit": "7.11E-06Bytes",
+ "UMask": "0xf",
+ "Unit": "UPI LL"
+ },
{
"BriefDescription": "PCI Express bandwidth reading at IIO, part 0",
"Counter": "0,1",
@@ -176,6 +238,21 @@
"UMask": "0x04",
"Unit": "IIO"
},
+ {
+ "BriefDescription": "PCI Express bandwidth reading at IIO",
+ "Counter": "0,1",
+ "EventCode": "0x83",
+ "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART0",
+ "FCMask": "0x07",
+ "Filter": "ch_mask=0x1f",
+ "MetricExpr": "UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART0 +UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART1 +UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART2 +UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART3",
+ "MetricName": "LLC_MISSES.PCIE_READ",
+ "PerPkg": "1",
+ "PortMask": "0x01",
+ "ScaleUnit": "4Bytes",
+ "UMask": "0x04",
+ "Unit": "IIO"
+ },
{
"BriefDescription": "PCI Express bandwidth writing at IIO, part 0",
"Counter": "0,1",
@@ -239,6 +316,21 @@
"UMask": "0x01",
"Unit": "IIO"
},
+ {
+ "BriefDescription": "PCI Express bandwidth writing at IIO",
+ "Counter": "0,1",
+ "EventCode": "0x83",
+ "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART0",
+ "FCMask": "0x07",
+ "Filter": "ch_mask=0x1f",
+ "MetricExpr": "UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART0 +UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART1 +UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART2 +UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART3",
+ "MetricName": "LLC_MISSES.PCIE_WRITE",
+ "PerPkg": "1",
+ "PortMask": "0x01",
+ "ScaleUnit": "4Bytes",
+ "UMask": "0x01",
+ "Unit": "IIO"
+ },
{
"BriefDescription": "Core Cross Snoops Issued; Multiple Core Requests",
"Counter": "0,1,2,3",
--
2.36.0.rc0.470.gd361397f0d-goog
^ permalink raw reply related [flat|nested] 19+ messages in thread
* [PATCH 06/14] perf vendor events intel: Update nehalemep event topics
2022-04-13 21:04 [PATCH 01/14] perf vendor events intel: Fix icelake cstate metrics Ian Rogers
` (2 preceding siblings ...)
2022-04-13 21:04 ` [PATCH 05/14] perf vendor events intel: Update SKX uncore Ian Rogers
@ 2022-04-13 21:04 ` Ian Rogers
2022-04-13 21:04 ` [PATCH 07/14] perf vendor events intel: Update tigerlake topic Ian Rogers
` (9 subsequent siblings)
13 siblings, 0 replies; 19+ messages in thread
From: Ian Rogers @ 2022-04-13 21:04 UTC (permalink / raw)
To: Peter Zijlstra, Ingo Molnar, Arnaldo Carvalho de Melo,
Mark Rutland, Alexander Shishkin, Jiri Olsa, Namhyung Kim,
Maxime Coquelin, Alexandre Torgue, Kan Liang, Xing Zhengjun,
Andi Kleen, John Garry, James Clark, linux-kernel,
linux-perf-users
Cc: Ian Rogers
Apply topic updates from:
https://github.com/intel/event-converter-for-linux-perf/
Signed-off-by: Ian Rogers <irogers@google.com>
---
.../pmu-events/arch/x86/nehalemep/other.json | 66 +------------------
.../arch/x86/nehalemep/pipeline.json | 66 ++++++++++++++++++-
2 files changed, 66 insertions(+), 66 deletions(-)
diff --git a/tools/perf/pmu-events/arch/x86/nehalemep/other.json b/tools/perf/pmu-events/arch/x86/nehalemep/other.json
index 710b106ce12a..f6887b234b0e 100644
--- a/tools/perf/pmu-events/arch/x86/nehalemep/other.json
+++ b/tools/perf/pmu-events/arch/x86/nehalemep/other.json
@@ -1,28 +1,4 @@
[
- {
- "BriefDescription": "Early Branch Prediciton Unit clears",
- "Counter": "0,1,2,3",
- "EventCode": "0xE8",
- "EventName": "BPU_CLEARS.EARLY",
- "SampleAfterValue": "2000000",
- "UMask": "0x1"
- },
- {
- "BriefDescription": "Late Branch Prediction Unit clears",
- "Counter": "0,1,2,3",
- "EventCode": "0xE8",
- "EventName": "BPU_CLEARS.LATE",
- "SampleAfterValue": "2000000",
- "UMask": "0x2"
- },
- {
- "BriefDescription": "Branch prediction unit missed call or return",
- "Counter": "0,1,2,3",
- "EventCode": "0xE5",
- "EventName": "BPU_MISSED_CALL_RET",
- "SampleAfterValue": "2000000",
- "UMask": "0x1"
- },
{
"BriefDescription": "ES segment renames",
"Counter": "0,1,2,3",
@@ -119,46 +95,6 @@
"SampleAfterValue": "200000",
"UMask": "0x1"
},
- {
- "BriefDescription": "All RAT stall cycles",
- "Counter": "0,1,2,3",
- "EventCode": "0xD2",
- "EventName": "RAT_STALLS.ANY",
- "SampleAfterValue": "2000000",
- "UMask": "0xf"
- },
- {
- "BriefDescription": "Flag stall cycles",
- "Counter": "0,1,2,3",
- "EventCode": "0xD2",
- "EventName": "RAT_STALLS.FLAGS",
- "SampleAfterValue": "2000000",
- "UMask": "0x1"
- },
- {
- "BriefDescription": "Partial register stall cycles",
- "Counter": "0,1,2,3",
- "EventCode": "0xD2",
- "EventName": "RAT_STALLS.REGISTERS",
- "SampleAfterValue": "2000000",
- "UMask": "0x2"
- },
- {
- "BriefDescription": "ROB read port stalls cycles",
- "Counter": "0,1,2,3",
- "EventCode": "0xD2",
- "EventName": "RAT_STALLS.ROB_READ_PORT",
- "SampleAfterValue": "2000000",
- "UMask": "0x4"
- },
- {
- "BriefDescription": "Scoreboard stall cycles",
- "Counter": "0,1,2,3",
- "EventCode": "0xD2",
- "EventName": "RAT_STALLS.SCOREBOARD",
- "SampleAfterValue": "2000000",
- "UMask": "0x8"
- },
{
"BriefDescription": "All Store buffer stall cycles",
"Counter": "0,1,2,3",
@@ -207,4 +143,4 @@
"SampleAfterValue": "2000000",
"UMask": "0x1"
}
-]
\ No newline at end of file
+]
diff --git a/tools/perf/pmu-events/arch/x86/nehalemep/pipeline.json b/tools/perf/pmu-events/arch/x86/nehalemep/pipeline.json
index e64d685c128a..6fc1a6efd8e8 100644
--- a/tools/perf/pmu-events/arch/x86/nehalemep/pipeline.json
+++ b/tools/perf/pmu-events/arch/x86/nehalemep/pipeline.json
@@ -50,6 +50,30 @@
"SampleAfterValue": "2000000",
"UMask": "0x1"
},
+ {
+ "BriefDescription": "Early Branch Prediciton Unit clears",
+ "Counter": "0,1,2,3",
+ "EventCode": "0xE8",
+ "EventName": "BPU_CLEARS.EARLY",
+ "SampleAfterValue": "2000000",
+ "UMask": "0x1"
+ },
+ {
+ "BriefDescription": "Late Branch Prediction Unit clears",
+ "Counter": "0,1,2,3",
+ "EventCode": "0xE8",
+ "EventName": "BPU_CLEARS.LATE",
+ "SampleAfterValue": "2000000",
+ "UMask": "0x2"
+ },
+ {
+ "BriefDescription": "Branch prediction unit missed call or return",
+ "Counter": "0,1,2,3",
+ "EventCode": "0xE5",
+ "EventName": "BPU_MISSED_CALL_RET",
+ "SampleAfterValue": "2000000",
+ "UMask": "0x1"
+ },
{
"BriefDescription": "Branch instructions decoded",
"Counter": "0,1,2,3",
@@ -476,6 +500,46 @@
"SampleAfterValue": "20000",
"UMask": "0x4"
},
+ {
+ "BriefDescription": "All RAT stall cycles",
+ "Counter": "0,1,2,3",
+ "EventCode": "0xD2",
+ "EventName": "RAT_STALLS.ANY",
+ "SampleAfterValue": "2000000",
+ "UMask": "0xf"
+ },
+ {
+ "BriefDescription": "Flag stall cycles",
+ "Counter": "0,1,2,3",
+ "EventCode": "0xD2",
+ "EventName": "RAT_STALLS.FLAGS",
+ "SampleAfterValue": "2000000",
+ "UMask": "0x1"
+ },
+ {
+ "BriefDescription": "Partial register stall cycles",
+ "Counter": "0,1,2,3",
+ "EventCode": "0xD2",
+ "EventName": "RAT_STALLS.REGISTERS",
+ "SampleAfterValue": "2000000",
+ "UMask": "0x2"
+ },
+ {
+ "BriefDescription": "ROB read port stalls cycles",
+ "Counter": "0,1,2,3",
+ "EventCode": "0xD2",
+ "EventName": "RAT_STALLS.ROB_READ_PORT",
+ "SampleAfterValue": "2000000",
+ "UMask": "0x4"
+ },
+ {
+ "BriefDescription": "Scoreboard stall cycles",
+ "Counter": "0,1,2,3",
+ "EventCode": "0xD2",
+ "EventName": "RAT_STALLS.SCOREBOARD",
+ "SampleAfterValue": "2000000",
+ "UMask": "0x8"
+ },
{
"BriefDescription": "Resource related stall cycles",
"Counter": "0,1,2,3",
@@ -878,4 +942,4 @@
"SampleAfterValue": "2000000",
"UMask": "0x1"
}
-]
\ No newline at end of file
+]
--
2.36.0.rc0.470.gd361397f0d-goog
^ permalink raw reply related [flat|nested] 19+ messages in thread
* [PATCH 07/14] perf vendor events intel: Update tigerlake topic
2022-04-13 21:04 [PATCH 01/14] perf vendor events intel: Fix icelake cstate metrics Ian Rogers
` (3 preceding siblings ...)
2022-04-13 21:04 ` [PATCH 06/14] perf vendor events intel: Update nehalemep event topics Ian Rogers
@ 2022-04-13 21:04 ` Ian Rogers
2022-04-13 21:04 ` [PATCH 08/14] perf vendor events intel: Update tremontx uncore and topics Ian Rogers
` (8 subsequent siblings)
13 siblings, 0 replies; 19+ messages in thread
From: Ian Rogers @ 2022-04-13 21:04 UTC (permalink / raw)
To: Peter Zijlstra, Ingo Molnar, Arnaldo Carvalho de Melo,
Mark Rutland, Alexander Shishkin, Jiri Olsa, Namhyung Kim,
Maxime Coquelin, Alexandre Torgue, Kan Liang, Xing Zhengjun,
Andi Kleen, John Garry, James Clark, linux-kernel,
linux-perf-users
Cc: Ian Rogers
Update the topic of ASSISTS.ANY as per:
https://github.com/intel/event-converter-for-linux-perf/
Signed-off-by: Ian Rogers <irogers@google.com>
---
tools/perf/pmu-events/arch/x86/tigerlake/other.json | 13 +------------
.../pmu-events/arch/x86/tigerlake/pipeline.json | 13 ++++++++++++-
2 files changed, 13 insertions(+), 13 deletions(-)
diff --git a/tools/perf/pmu-events/arch/x86/tigerlake/other.json b/tools/perf/pmu-events/arch/x86/tigerlake/other.json
index 304cd09fe159..65539490e18f 100644
--- a/tools/perf/pmu-events/arch/x86/tigerlake/other.json
+++ b/tools/perf/pmu-events/arch/x86/tigerlake/other.json
@@ -1,15 +1,4 @@
[
- {
- "BriefDescription": "Number of occurrences where a microcode assist is invoked by hardware.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3,4,5,6,7",
- "EventCode": "0xc1",
- "EventName": "ASSISTS.ANY",
- "PEBScounters": "0,1,2,3,4,5,6,7",
- "PublicDescription": "Counts the number of occurrences where a microcode assist is invoked by hardware Examples include AD (page Access Dirty), FP and AVX related assists.",
- "SampleAfterValue": "100003",
- "UMask": "0x7"
- },
{
"BriefDescription": "Core cycles where the core was running in a manner where Turbo may be clipped to the Non-AVX turbo schedule.",
"CollectPEBSRecord": "2",
@@ -57,4 +46,4 @@
"SampleAfterValue": "100003",
"UMask": "0x1"
}
-]
\ No newline at end of file
+]
diff --git a/tools/perf/pmu-events/arch/x86/tigerlake/pipeline.json b/tools/perf/pmu-events/arch/x86/tigerlake/pipeline.json
index d436775c80db..a8aa1b455c77 100644
--- a/tools/perf/pmu-events/arch/x86/tigerlake/pipeline.json
+++ b/tools/perf/pmu-events/arch/x86/tigerlake/pipeline.json
@@ -11,6 +11,17 @@
"SampleAfterValue": "1000003",
"UMask": "0x9"
},
+ {
+ "BriefDescription": "Number of occurrences where a microcode assist is invoked by hardware.",
+ "CollectPEBSRecord": "2",
+ "Counter": "0,1,2,3,4,5,6,7",
+ "EventCode": "0xc1",
+ "EventName": "ASSISTS.ANY",
+ "PEBScounters": "0,1,2,3,4,5,6,7",
+ "PublicDescription": "Counts the number of occurrences where a microcode assist is invoked by hardware Examples include AD (page Access Dirty), FP and AVX related assists.",
+ "SampleAfterValue": "100003",
+ "UMask": "0x7"
+ },
{
"BriefDescription": "All branch instructions retired.",
"CollectPEBSRecord": "2",
@@ -1055,4 +1066,4 @@
"SampleAfterValue": "1000003",
"UMask": "0x2"
}
-]
\ No newline at end of file
+]
--
2.36.0.rc0.470.gd361397f0d-goog
^ permalink raw reply related [flat|nested] 19+ messages in thread
* [PATCH 08/14] perf vendor events intel: Update tremontx uncore and topics
2022-04-13 21:04 [PATCH 01/14] perf vendor events intel: Fix icelake cstate metrics Ian Rogers
` (4 preceding siblings ...)
2022-04-13 21:04 ` [PATCH 07/14] perf vendor events intel: Update tigerlake topic Ian Rogers
@ 2022-04-13 21:04 ` Ian Rogers
2022-04-13 21:04 ` [PATCH 09/14] perf vendor events intel: Update westmereep-dp event topics Ian Rogers
` (7 subsequent siblings)
13 siblings, 0 replies; 19+ messages in thread
From: Ian Rogers @ 2022-04-13 21:04 UTC (permalink / raw)
To: Peter Zijlstra, Ingo Molnar, Arnaldo Carvalho de Melo,
Mark Rutland, Alexander Shishkin, Jiri Olsa, Namhyung Kim,
Maxime Coquelin, Alexandre Torgue, Kan Liang, Xing Zhengjun,
Andi Kleen, John Garry, James Clark, linux-kernel,
linux-perf-users
Cc: Ian Rogers
Update the topic of BTCLEAR.ANY and add additional uncore event names
as per:
https://github.com/intel/event-converter-for-linux-perf/
Signed-off-by: Ian Rogers <irogers@google.com>
---
.../pmu-events/arch/x86/tremontx/other.json | 13 +--
.../arch/x86/tremontx/pipeline.json | 13 ++-
.../arch/x86/tremontx/uncore-memory.json | 22 +++++
.../arch/x86/tremontx/uncore-other.json | 94 +++++++++++++++++++
4 files changed, 129 insertions(+), 13 deletions(-)
diff --git a/tools/perf/pmu-events/arch/x86/tremontx/other.json b/tools/perf/pmu-events/arch/x86/tremontx/other.json
index 4f20f45a4898..2766e9dfc325 100644
--- a/tools/perf/pmu-events/arch/x86/tremontx/other.json
+++ b/tools/perf/pmu-events/arch/x86/tremontx/other.json
@@ -1,15 +1,4 @@
[
- {
- "BriefDescription": "Counts the total number of BTCLEARS.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
- "EventCode": "0xe8",
- "EventName": "BTCLEAR.ANY",
- "PDIR_COUNTER": "na",
- "PEBScounters": "0,1,2,3",
- "PublicDescription": "Counts the total number of BTCLEARS which occurs when the Branch Target Buffer (BTB) predicts a taken branch.",
- "SampleAfterValue": "200003"
- },
{
"BriefDescription": "This event is deprecated. Refer to new event BUS_LOCK.SELF_LOCKS",
"CollectPEBSRecord": "2",
@@ -683,4 +672,4 @@
"SampleAfterValue": "100003",
"UMask": "0x1"
}
-]
\ No newline at end of file
+]
diff --git a/tools/perf/pmu-events/arch/x86/tremontx/pipeline.json b/tools/perf/pmu-events/arch/x86/tremontx/pipeline.json
index 0a77e9f9a16a..38dc8044767b 100644
--- a/tools/perf/pmu-events/arch/x86/tremontx/pipeline.json
+++ b/tools/perf/pmu-events/arch/x86/tremontx/pipeline.json
@@ -164,6 +164,17 @@
"SampleAfterValue": "200003",
"UMask": "0xfe"
},
+ {
+ "BriefDescription": "Counts the total number of BTCLEARS.",
+ "CollectPEBSRecord": "2",
+ "Counter": "0,1,2,3",
+ "EventCode": "0xe8",
+ "EventName": "BTCLEAR.ANY",
+ "PDIR_COUNTER": "na",
+ "PEBScounters": "0,1,2,3",
+ "PublicDescription": "Counts the total number of BTCLEARS which occurs when the Branch Target Buffer (BTB) predicts a taken branch.",
+ "SampleAfterValue": "200003"
+ },
{
"BriefDescription": "Counts the number of unhalted core clock cycles. (Fixed event)",
"CollectPEBSRecord": "2",
@@ -671,4 +682,4 @@
"SampleAfterValue": "2000003",
"UMask": "0x2"
}
-]
\ No newline at end of file
+]
diff --git a/tools/perf/pmu-events/arch/x86/tremontx/uncore-memory.json b/tools/perf/pmu-events/arch/x86/tremontx/uncore-memory.json
index 0d342efae154..b7ff25a5d717 100644
--- a/tools/perf/pmu-events/arch/x86/tremontx/uncore-memory.json
+++ b/tools/perf/pmu-events/arch/x86/tremontx/uncore-memory.json
@@ -10,6 +10,17 @@
"UMask": "0x0f",
"Unit": "iMC"
},
+ {
+ "BriefDescription": "read requests to memory controller",
+ "Counter": "0,1,2,3",
+ "CounterType": "PGMABLE",
+ "EventCode": "0x04",
+ "EventName": "UNC_M_CAS_COUNT.RD",
+ "PerPkg": "1",
+ "ScaleUnit": "64Bytes",
+ "UMask": "0x0f",
+ "Unit": "iMC"
+ },
{
"BriefDescription": "write requests to memory controller. Derived from unc_m_cas_count.wr",
"Counter": "0,1,2,3",
@@ -21,6 +32,17 @@
"UMask": "0x30",
"Unit": "iMC"
},
+ {
+ "BriefDescription": "write requests to memory controller",
+ "Counter": "0,1,2,3",
+ "CounterType": "PGMABLE",
+ "EventCode": "0x04",
+ "EventName": "UNC_M_CAS_COUNT.WR",
+ "PerPkg": "1",
+ "ScaleUnit": "64Bytes",
+ "UMask": "0x30",
+ "Unit": "iMC"
+ },
{
"BriefDescription": "Memory controller clock ticks",
"Counter": "0,1,2,3",
diff --git a/tools/perf/pmu-events/arch/x86/tremontx/uncore-other.json b/tools/perf/pmu-events/arch/x86/tremontx/uncore-other.json
index 0f73582248f9..5194ce1b4390 100644
--- a/tools/perf/pmu-events/arch/x86/tremontx/uncore-other.json
+++ b/tools/perf/pmu-events/arch/x86/tremontx/uncore-other.json
@@ -19,6 +19,18 @@
"UMaskExt": "0xC001FE",
"Unit": "CHA"
},
+ {
+ "BriefDescription": "LLC misses - Uncacheable reads (from cpu) ",
+ "Counter": "0,1,2,3",
+ "CounterType": "PGMABLE",
+ "EventCode": "0x35",
+ "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS",
+ "Filter": "config1=0x40e33",
+ "PerPkg": "1",
+ "UMask": "0xC001FE01",
+ "UMaskExt": "0xC001FE",
+ "Unit": "CHA"
+ },
{
"BriefDescription": "MMIO reads. Derived from unc_cha_tor_inserts.ia_miss",
"Counter": "0,1,2,3",
@@ -31,6 +43,18 @@
"UMaskExt": "0xC001FE",
"Unit": "CHA"
},
+ {
+ "BriefDescription": "MMIO reads",
+ "Counter": "0,1,2,3",
+ "CounterType": "PGMABLE",
+ "EventCode": "0x35",
+ "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS",
+ "Filter": "config1=0x40040e33",
+ "PerPkg": "1",
+ "UMask": "0xC001FE01",
+ "UMaskExt": "0xC001FE",
+ "Unit": "CHA"
+ },
{
"BriefDescription": "MMIO writes. Derived from unc_cha_tor_inserts.ia_miss",
"Counter": "0,1,2,3",
@@ -43,6 +67,18 @@
"UMaskExt": "0xC001FE",
"Unit": "CHA"
},
+ {
+ "BriefDescription": "MMIO writes",
+ "Counter": "0,1,2,3",
+ "CounterType": "PGMABLE",
+ "EventCode": "0x35",
+ "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS",
+ "Filter": "config1=0x40041e33",
+ "PerPkg": "1",
+ "UMask": "0xC001FE01",
+ "UMaskExt": "0xC001FE",
+ "Unit": "CHA"
+ },
{
"BriefDescription": "Streaming stores (full cache line). Derived from unc_cha_tor_inserts.ia_miss",
"Counter": "0,1,2,3",
@@ -56,6 +92,19 @@
"UMaskExt": "0xC001FE",
"Unit": "CHA"
},
+ {
+ "BriefDescription": "Streaming stores (full cache line)",
+ "Counter": "0,1,2,3",
+ "CounterType": "PGMABLE",
+ "EventCode": "0x35",
+ "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS",
+ "Filter": "config1=0x41833",
+ "PerPkg": "1",
+ "ScaleUnit": "64Bytes",
+ "UMask": "0xC001FE01",
+ "UMaskExt": "0xC001FE",
+ "Unit": "CHA"
+ },
{
"BriefDescription": "Streaming stores (partial cache line). Derived from unc_cha_tor_inserts.ia_miss",
"Counter": "0,1,2,3",
@@ -69,6 +118,19 @@
"UMaskExt": "0xC001FE",
"Unit": "CHA"
},
+ {
+ "BriefDescription": "Streaming stores (partial cache line)",
+ "Counter": "0,1,2,3",
+ "CounterType": "PGMABLE",
+ "EventCode": "0x35",
+ "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS",
+ "Filter": "config1=0x41a33",
+ "PerPkg": "1",
+ "ScaleUnit": "64Bytes",
+ "UMask": "0xC001FE01",
+ "UMaskExt": "0xC001FE",
+ "Unit": "CHA"
+ },
{
"BriefDescription": "read requests from home agent",
"Counter": "0,1,2,3",
@@ -105,6 +167,22 @@
"UMask": "0x04",
"Unit": "IIO"
},
+ {
+ "BriefDescription": "PCI Express bandwidth reading at IIO",
+ "Counter": "0,1",
+ "CounterType": "PGMABLE",
+ "EventCode": "0x83",
+ "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART0",
+ "FCMask": "0x07",
+ "Filter": "ch_mask=0x1f",
+ "MetricExpr": "UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART0 +UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART1 +UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART2 +UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART3",
+ "MetricName": "LLC_MISSES.PCIE_READ",
+ "PerPkg": "1",
+ "PortMask": "0x01",
+ "ScaleUnit": "4Bytes",
+ "UMask": "0x04",
+ "Unit": "IIO"
+ },
{
"BriefDescription": "PCI Express bandwidth writing at IIO. Derived from unc_iio_data_req_of_cpu.mem_write.part0",
"Counter": "0,1",
@@ -121,6 +199,22 @@
"UMask": "0x01",
"Unit": "IIO"
},
+ {
+ "BriefDescription": "PCI Express bandwidth writing at IIO",
+ "Counter": "0,1",
+ "CounterType": "PGMABLE",
+ "EventCode": "0x83",
+ "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART0",
+ "FCMask": "0x07",
+ "Filter": "ch_mask=0x1f",
+ "MetricExpr": "UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART0 +UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART1 +UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART2 +UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART3",
+ "MetricName": "LLC_MISSES.PCIE_WRITE",
+ "PerPkg": "1",
+ "PortMask": "0x01",
+ "ScaleUnit": "4Bytes",
+ "UMask": "0x01",
+ "Unit": "IIO"
+ },
{
"BriefDescription": "PCI Express bandwidth writing at IIO, part 1",
"Counter": "0,1",
--
2.36.0.rc0.470.gd361397f0d-goog
^ permalink raw reply related [flat|nested] 19+ messages in thread
* [PATCH 09/14] perf vendor events intel: Update westmereep-dp event topics
2022-04-13 21:04 [PATCH 01/14] perf vendor events intel: Fix icelake cstate metrics Ian Rogers
` (5 preceding siblings ...)
2022-04-13 21:04 ` [PATCH 08/14] perf vendor events intel: Update tremontx uncore and topics Ian Rogers
@ 2022-04-13 21:04 ` Ian Rogers
2022-04-13 21:04 ` [PATCH 10/14] perf vendor events intel: Update westmereep-sp " Ian Rogers
` (6 subsequent siblings)
13 siblings, 0 replies; 19+ messages in thread
From: Ian Rogers @ 2022-04-13 21:04 UTC (permalink / raw)
To: Peter Zijlstra, Ingo Molnar, Arnaldo Carvalho de Melo,
Mark Rutland, Alexander Shishkin, Jiri Olsa, Namhyung Kim,
Maxime Coquelin, Alexandre Torgue, Kan Liang, Xing Zhengjun,
Andi Kleen, John Garry, James Clark, linux-kernel,
linux-perf-users
Cc: Ian Rogers
Apply topic updates from:
https://github.com/intel/event-converter-for-linux-perf/
Signed-off-by: Ian Rogers <irogers@google.com>
---
.../arch/x86/westmereep-dp/other.json | 66 +------------------
.../arch/x86/westmereep-dp/pipeline.json | 66 ++++++++++++++++++-
2 files changed, 66 insertions(+), 66 deletions(-)
diff --git a/tools/perf/pmu-events/arch/x86/westmereep-dp/other.json b/tools/perf/pmu-events/arch/x86/westmereep-dp/other.json
index 23dcd554728c..67bc34984fa8 100644
--- a/tools/perf/pmu-events/arch/x86/westmereep-dp/other.json
+++ b/tools/perf/pmu-events/arch/x86/westmereep-dp/other.json
@@ -1,28 +1,4 @@
[
- {
- "BriefDescription": "Early Branch Prediciton Unit clears",
- "Counter": "0,1,2,3",
- "EventCode": "0xE8",
- "EventName": "BPU_CLEARS.EARLY",
- "SampleAfterValue": "2000000",
- "UMask": "0x1"
- },
- {
- "BriefDescription": "Late Branch Prediction Unit clears",
- "Counter": "0,1,2,3",
- "EventCode": "0xE8",
- "EventName": "BPU_CLEARS.LATE",
- "SampleAfterValue": "2000000",
- "UMask": "0x2"
- },
- {
- "BriefDescription": "Branch prediction unit missed call or return",
- "Counter": "0,1,2,3",
- "EventCode": "0xE5",
- "EventName": "BPU_MISSED_CALL_RET",
- "SampleAfterValue": "2000000",
- "UMask": "0x1"
- },
{
"BriefDescription": "ES segment renames",
"Counter": "0,1,2,3",
@@ -127,46 +103,6 @@
"SampleAfterValue": "200000",
"UMask": "0x1"
},
- {
- "BriefDescription": "All RAT stall cycles",
- "Counter": "0,1,2,3",
- "EventCode": "0xD2",
- "EventName": "RAT_STALLS.ANY",
- "SampleAfterValue": "2000000",
- "UMask": "0xf"
- },
- {
- "BriefDescription": "Flag stall cycles",
- "Counter": "0,1,2,3",
- "EventCode": "0xD2",
- "EventName": "RAT_STALLS.FLAGS",
- "SampleAfterValue": "2000000",
- "UMask": "0x1"
- },
- {
- "BriefDescription": "Partial register stall cycles",
- "Counter": "0,1,2,3",
- "EventCode": "0xD2",
- "EventName": "RAT_STALLS.REGISTERS",
- "SampleAfterValue": "2000000",
- "UMask": "0x2"
- },
- {
- "BriefDescription": "ROB read port stalls cycles",
- "Counter": "0,1,2,3",
- "EventCode": "0xD2",
- "EventName": "RAT_STALLS.ROB_READ_PORT",
- "SampleAfterValue": "2000000",
- "UMask": "0x4"
- },
- {
- "BriefDescription": "Scoreboard stall cycles",
- "Counter": "0,1,2,3",
- "EventCode": "0xD2",
- "EventName": "RAT_STALLS.SCOREBOARD",
- "SampleAfterValue": "2000000",
- "UMask": "0x8"
- },
{
"BriefDescription": "All Store buffer stall cycles",
"Counter": "0,1,2,3",
@@ -284,4 +220,4 @@
"SampleAfterValue": "2000000",
"UMask": "0x1"
}
-]
\ No newline at end of file
+]
diff --git a/tools/perf/pmu-events/arch/x86/westmereep-dp/pipeline.json b/tools/perf/pmu-events/arch/x86/westmereep-dp/pipeline.json
index 10140f460fbb..403fb2b87fc4 100644
--- a/tools/perf/pmu-events/arch/x86/westmereep-dp/pipeline.json
+++ b/tools/perf/pmu-events/arch/x86/westmereep-dp/pipeline.json
@@ -50,6 +50,30 @@
"SampleAfterValue": "2000000",
"UMask": "0x1"
},
+ {
+ "BriefDescription": "Early Branch Prediciton Unit clears",
+ "Counter": "0,1,2,3",
+ "EventCode": "0xE8",
+ "EventName": "BPU_CLEARS.EARLY",
+ "SampleAfterValue": "2000000",
+ "UMask": "0x1"
+ },
+ {
+ "BriefDescription": "Late Branch Prediction Unit clears",
+ "Counter": "0,1,2,3",
+ "EventCode": "0xE8",
+ "EventName": "BPU_CLEARS.LATE",
+ "SampleAfterValue": "2000000",
+ "UMask": "0x2"
+ },
+ {
+ "BriefDescription": "Branch prediction unit missed call or return",
+ "Counter": "0,1,2,3",
+ "EventCode": "0xE5",
+ "EventName": "BPU_MISSED_CALL_RET",
+ "SampleAfterValue": "2000000",
+ "UMask": "0x1"
+ },
{
"BriefDescription": "Branch instructions decoded",
"Counter": "0,1,2,3",
@@ -494,6 +518,46 @@
"SampleAfterValue": "20000",
"UMask": "0x4"
},
+ {
+ "BriefDescription": "All RAT stall cycles",
+ "Counter": "0,1,2,3",
+ "EventCode": "0xD2",
+ "EventName": "RAT_STALLS.ANY",
+ "SampleAfterValue": "2000000",
+ "UMask": "0xf"
+ },
+ {
+ "BriefDescription": "Flag stall cycles",
+ "Counter": "0,1,2,3",
+ "EventCode": "0xD2",
+ "EventName": "RAT_STALLS.FLAGS",
+ "SampleAfterValue": "2000000",
+ "UMask": "0x1"
+ },
+ {
+ "BriefDescription": "Partial register stall cycles",
+ "Counter": "0,1,2,3",
+ "EventCode": "0xD2",
+ "EventName": "RAT_STALLS.REGISTERS",
+ "SampleAfterValue": "2000000",
+ "UMask": "0x2"
+ },
+ {
+ "BriefDescription": "ROB read port stalls cycles",
+ "Counter": "0,1,2,3",
+ "EventCode": "0xD2",
+ "EventName": "RAT_STALLS.ROB_READ_PORT",
+ "SampleAfterValue": "2000000",
+ "UMask": "0x4"
+ },
+ {
+ "BriefDescription": "Scoreboard stall cycles",
+ "Counter": "0,1,2,3",
+ "EventCode": "0xD2",
+ "EventName": "RAT_STALLS.SCOREBOARD",
+ "SampleAfterValue": "2000000",
+ "UMask": "0x8"
+ },
{
"BriefDescription": "Resource related stall cycles",
"Counter": "0,1,2,3",
@@ -896,4 +960,4 @@
"SampleAfterValue": "2000000",
"UMask": "0x1"
}
-]
\ No newline at end of file
+]
--
2.36.0.rc0.470.gd361397f0d-goog
^ permalink raw reply related [flat|nested] 19+ messages in thread
* [PATCH 10/14] perf vendor events intel: Update westmereep-sp event topics
2022-04-13 21:04 [PATCH 01/14] perf vendor events intel: Fix icelake cstate metrics Ian Rogers
` (6 preceding siblings ...)
2022-04-13 21:04 ` [PATCH 09/14] perf vendor events intel: Update westmereep-dp event topics Ian Rogers
@ 2022-04-13 21:04 ` Ian Rogers
2022-04-13 21:05 ` [PATCH 11/14] perf vendor events intel: Update westmereex " Ian Rogers
` (5 subsequent siblings)
13 siblings, 0 replies; 19+ messages in thread
From: Ian Rogers @ 2022-04-13 21:04 UTC (permalink / raw)
To: Peter Zijlstra, Ingo Molnar, Arnaldo Carvalho de Melo,
Mark Rutland, Alexander Shishkin, Jiri Olsa, Namhyung Kim,
Maxime Coquelin, Alexandre Torgue, Kan Liang, Xing Zhengjun,
Andi Kleen, John Garry, James Clark, linux-kernel,
linux-perf-users
Cc: Ian Rogers
Apply topic updates from:
https://github.com/intel/event-converter-for-linux-perf/
Signed-off-by: Ian Rogers <irogers@google.com>
---
.../arch/x86/westmereep-sp/other.json | 66 +------------------
.../arch/x86/westmereep-sp/pipeline.json | 66 ++++++++++++++++++-
2 files changed, 66 insertions(+), 66 deletions(-)
diff --git a/tools/perf/pmu-events/arch/x86/westmereep-sp/other.json b/tools/perf/pmu-events/arch/x86/westmereep-sp/other.json
index 23dcd554728c..67bc34984fa8 100644
--- a/tools/perf/pmu-events/arch/x86/westmereep-sp/other.json
+++ b/tools/perf/pmu-events/arch/x86/westmereep-sp/other.json
@@ -1,28 +1,4 @@
[
- {
- "BriefDescription": "Early Branch Prediciton Unit clears",
- "Counter": "0,1,2,3",
- "EventCode": "0xE8",
- "EventName": "BPU_CLEARS.EARLY",
- "SampleAfterValue": "2000000",
- "UMask": "0x1"
- },
- {
- "BriefDescription": "Late Branch Prediction Unit clears",
- "Counter": "0,1,2,3",
- "EventCode": "0xE8",
- "EventName": "BPU_CLEARS.LATE",
- "SampleAfterValue": "2000000",
- "UMask": "0x2"
- },
- {
- "BriefDescription": "Branch prediction unit missed call or return",
- "Counter": "0,1,2,3",
- "EventCode": "0xE5",
- "EventName": "BPU_MISSED_CALL_RET",
- "SampleAfterValue": "2000000",
- "UMask": "0x1"
- },
{
"BriefDescription": "ES segment renames",
"Counter": "0,1,2,3",
@@ -127,46 +103,6 @@
"SampleAfterValue": "200000",
"UMask": "0x1"
},
- {
- "BriefDescription": "All RAT stall cycles",
- "Counter": "0,1,2,3",
- "EventCode": "0xD2",
- "EventName": "RAT_STALLS.ANY",
- "SampleAfterValue": "2000000",
- "UMask": "0xf"
- },
- {
- "BriefDescription": "Flag stall cycles",
- "Counter": "0,1,2,3",
- "EventCode": "0xD2",
- "EventName": "RAT_STALLS.FLAGS",
- "SampleAfterValue": "2000000",
- "UMask": "0x1"
- },
- {
- "BriefDescription": "Partial register stall cycles",
- "Counter": "0,1,2,3",
- "EventCode": "0xD2",
- "EventName": "RAT_STALLS.REGISTERS",
- "SampleAfterValue": "2000000",
- "UMask": "0x2"
- },
- {
- "BriefDescription": "ROB read port stalls cycles",
- "Counter": "0,1,2,3",
- "EventCode": "0xD2",
- "EventName": "RAT_STALLS.ROB_READ_PORT",
- "SampleAfterValue": "2000000",
- "UMask": "0x4"
- },
- {
- "BriefDescription": "Scoreboard stall cycles",
- "Counter": "0,1,2,3",
- "EventCode": "0xD2",
- "EventName": "RAT_STALLS.SCOREBOARD",
- "SampleAfterValue": "2000000",
- "UMask": "0x8"
- },
{
"BriefDescription": "All Store buffer stall cycles",
"Counter": "0,1,2,3",
@@ -284,4 +220,4 @@
"SampleAfterValue": "2000000",
"UMask": "0x1"
}
-]
\ No newline at end of file
+]
diff --git a/tools/perf/pmu-events/arch/x86/westmereep-sp/pipeline.json b/tools/perf/pmu-events/arch/x86/westmereep-sp/pipeline.json
index 10140f460fbb..403fb2b87fc4 100644
--- a/tools/perf/pmu-events/arch/x86/westmereep-sp/pipeline.json
+++ b/tools/perf/pmu-events/arch/x86/westmereep-sp/pipeline.json
@@ -50,6 +50,30 @@
"SampleAfterValue": "2000000",
"UMask": "0x1"
},
+ {
+ "BriefDescription": "Early Branch Prediciton Unit clears",
+ "Counter": "0,1,2,3",
+ "EventCode": "0xE8",
+ "EventName": "BPU_CLEARS.EARLY",
+ "SampleAfterValue": "2000000",
+ "UMask": "0x1"
+ },
+ {
+ "BriefDescription": "Late Branch Prediction Unit clears",
+ "Counter": "0,1,2,3",
+ "EventCode": "0xE8",
+ "EventName": "BPU_CLEARS.LATE",
+ "SampleAfterValue": "2000000",
+ "UMask": "0x2"
+ },
+ {
+ "BriefDescription": "Branch prediction unit missed call or return",
+ "Counter": "0,1,2,3",
+ "EventCode": "0xE5",
+ "EventName": "BPU_MISSED_CALL_RET",
+ "SampleAfterValue": "2000000",
+ "UMask": "0x1"
+ },
{
"BriefDescription": "Branch instructions decoded",
"Counter": "0,1,2,3",
@@ -494,6 +518,46 @@
"SampleAfterValue": "20000",
"UMask": "0x4"
},
+ {
+ "BriefDescription": "All RAT stall cycles",
+ "Counter": "0,1,2,3",
+ "EventCode": "0xD2",
+ "EventName": "RAT_STALLS.ANY",
+ "SampleAfterValue": "2000000",
+ "UMask": "0xf"
+ },
+ {
+ "BriefDescription": "Flag stall cycles",
+ "Counter": "0,1,2,3",
+ "EventCode": "0xD2",
+ "EventName": "RAT_STALLS.FLAGS",
+ "SampleAfterValue": "2000000",
+ "UMask": "0x1"
+ },
+ {
+ "BriefDescription": "Partial register stall cycles",
+ "Counter": "0,1,2,3",
+ "EventCode": "0xD2",
+ "EventName": "RAT_STALLS.REGISTERS",
+ "SampleAfterValue": "2000000",
+ "UMask": "0x2"
+ },
+ {
+ "BriefDescription": "ROB read port stalls cycles",
+ "Counter": "0,1,2,3",
+ "EventCode": "0xD2",
+ "EventName": "RAT_STALLS.ROB_READ_PORT",
+ "SampleAfterValue": "2000000",
+ "UMask": "0x4"
+ },
+ {
+ "BriefDescription": "Scoreboard stall cycles",
+ "Counter": "0,1,2,3",
+ "EventCode": "0xD2",
+ "EventName": "RAT_STALLS.SCOREBOARD",
+ "SampleAfterValue": "2000000",
+ "UMask": "0x8"
+ },
{
"BriefDescription": "Resource related stall cycles",
"Counter": "0,1,2,3",
@@ -896,4 +960,4 @@
"SampleAfterValue": "2000000",
"UMask": "0x1"
}
-]
\ No newline at end of file
+]
--
2.36.0.rc0.470.gd361397f0d-goog
^ permalink raw reply related [flat|nested] 19+ messages in thread
* [PATCH 11/14] perf vendor events intel: Update westmereex event topics
2022-04-13 21:04 [PATCH 01/14] perf vendor events intel: Fix icelake cstate metrics Ian Rogers
` (7 preceding siblings ...)
2022-04-13 21:04 ` [PATCH 10/14] perf vendor events intel: Update westmereep-sp " Ian Rogers
@ 2022-04-13 21:05 ` Ian Rogers
2022-04-13 21:05 ` [PATCH 12/14] perf vendor events intel: Update elkhartlake " Ian Rogers
` (4 subsequent siblings)
13 siblings, 0 replies; 19+ messages in thread
From: Ian Rogers @ 2022-04-13 21:05 UTC (permalink / raw)
To: Peter Zijlstra, Ingo Molnar, Arnaldo Carvalho de Melo,
Mark Rutland, Alexander Shishkin, Jiri Olsa, Namhyung Kim,
Maxime Coquelin, Alexandre Torgue, Kan Liang, Xing Zhengjun,
Andi Kleen, John Garry, James Clark, linux-kernel,
linux-perf-users
Cc: Ian Rogers
Apply topic updates from:
https://github.com/intel/event-converter-for-linux-perf/
Signed-off-by: Ian Rogers <irogers@google.com>
---
.../pmu-events/arch/x86/westmereex/other.json | 66 +------------------
.../arch/x86/westmereex/pipeline.json | 66 ++++++++++++++++++-
2 files changed, 66 insertions(+), 66 deletions(-)
diff --git a/tools/perf/pmu-events/arch/x86/westmereex/other.json b/tools/perf/pmu-events/arch/x86/westmereex/other.json
index 23dcd554728c..67bc34984fa8 100644
--- a/tools/perf/pmu-events/arch/x86/westmereex/other.json
+++ b/tools/perf/pmu-events/arch/x86/westmereex/other.json
@@ -1,28 +1,4 @@
[
- {
- "BriefDescription": "Early Branch Prediciton Unit clears",
- "Counter": "0,1,2,3",
- "EventCode": "0xE8",
- "EventName": "BPU_CLEARS.EARLY",
- "SampleAfterValue": "2000000",
- "UMask": "0x1"
- },
- {
- "BriefDescription": "Late Branch Prediction Unit clears",
- "Counter": "0,1,2,3",
- "EventCode": "0xE8",
- "EventName": "BPU_CLEARS.LATE",
- "SampleAfterValue": "2000000",
- "UMask": "0x2"
- },
- {
- "BriefDescription": "Branch prediction unit missed call or return",
- "Counter": "0,1,2,3",
- "EventCode": "0xE5",
- "EventName": "BPU_MISSED_CALL_RET",
- "SampleAfterValue": "2000000",
- "UMask": "0x1"
- },
{
"BriefDescription": "ES segment renames",
"Counter": "0,1,2,3",
@@ -127,46 +103,6 @@
"SampleAfterValue": "200000",
"UMask": "0x1"
},
- {
- "BriefDescription": "All RAT stall cycles",
- "Counter": "0,1,2,3",
- "EventCode": "0xD2",
- "EventName": "RAT_STALLS.ANY",
- "SampleAfterValue": "2000000",
- "UMask": "0xf"
- },
- {
- "BriefDescription": "Flag stall cycles",
- "Counter": "0,1,2,3",
- "EventCode": "0xD2",
- "EventName": "RAT_STALLS.FLAGS",
- "SampleAfterValue": "2000000",
- "UMask": "0x1"
- },
- {
- "BriefDescription": "Partial register stall cycles",
- "Counter": "0,1,2,3",
- "EventCode": "0xD2",
- "EventName": "RAT_STALLS.REGISTERS",
- "SampleAfterValue": "2000000",
- "UMask": "0x2"
- },
- {
- "BriefDescription": "ROB read port stalls cycles",
- "Counter": "0,1,2,3",
- "EventCode": "0xD2",
- "EventName": "RAT_STALLS.ROB_READ_PORT",
- "SampleAfterValue": "2000000",
- "UMask": "0x4"
- },
- {
- "BriefDescription": "Scoreboard stall cycles",
- "Counter": "0,1,2,3",
- "EventCode": "0xD2",
- "EventName": "RAT_STALLS.SCOREBOARD",
- "SampleAfterValue": "2000000",
- "UMask": "0x8"
- },
{
"BriefDescription": "All Store buffer stall cycles",
"Counter": "0,1,2,3",
@@ -284,4 +220,4 @@
"SampleAfterValue": "2000000",
"UMask": "0x1"
}
-]
\ No newline at end of file
+]
diff --git a/tools/perf/pmu-events/arch/x86/westmereex/pipeline.json b/tools/perf/pmu-events/arch/x86/westmereex/pipeline.json
index 620d9084d860..7d6c2c1e0db0 100644
--- a/tools/perf/pmu-events/arch/x86/westmereex/pipeline.json
+++ b/tools/perf/pmu-events/arch/x86/westmereex/pipeline.json
@@ -50,6 +50,30 @@
"SampleAfterValue": "2000000",
"UMask": "0x1"
},
+ {
+ "BriefDescription": "Early Branch Prediciton Unit clears",
+ "Counter": "0,1,2,3",
+ "EventCode": "0xE8",
+ "EventName": "BPU_CLEARS.EARLY",
+ "SampleAfterValue": "2000000",
+ "UMask": "0x1"
+ },
+ {
+ "BriefDescription": "Late Branch Prediction Unit clears",
+ "Counter": "0,1,2,3",
+ "EventCode": "0xE8",
+ "EventName": "BPU_CLEARS.LATE",
+ "SampleAfterValue": "2000000",
+ "UMask": "0x2"
+ },
+ {
+ "BriefDescription": "Branch prediction unit missed call or return",
+ "Counter": "0,1,2,3",
+ "EventCode": "0xE5",
+ "EventName": "BPU_MISSED_CALL_RET",
+ "SampleAfterValue": "2000000",
+ "UMask": "0x1"
+ },
{
"BriefDescription": "Branch instructions decoded",
"Counter": "0,1,2,3",
@@ -494,6 +518,46 @@
"SampleAfterValue": "20000",
"UMask": "0x4"
},
+ {
+ "BriefDescription": "All RAT stall cycles",
+ "Counter": "0,1,2,3",
+ "EventCode": "0xD2",
+ "EventName": "RAT_STALLS.ANY",
+ "SampleAfterValue": "2000000",
+ "UMask": "0xf"
+ },
+ {
+ "BriefDescription": "Flag stall cycles",
+ "Counter": "0,1,2,3",
+ "EventCode": "0xD2",
+ "EventName": "RAT_STALLS.FLAGS",
+ "SampleAfterValue": "2000000",
+ "UMask": "0x1"
+ },
+ {
+ "BriefDescription": "Partial register stall cycles",
+ "Counter": "0,1,2,3",
+ "EventCode": "0xD2",
+ "EventName": "RAT_STALLS.REGISTERS",
+ "SampleAfterValue": "2000000",
+ "UMask": "0x2"
+ },
+ {
+ "BriefDescription": "ROB read port stalls cycles",
+ "Counter": "0,1,2,3",
+ "EventCode": "0xD2",
+ "EventName": "RAT_STALLS.ROB_READ_PORT",
+ "SampleAfterValue": "2000000",
+ "UMask": "0x4"
+ },
+ {
+ "BriefDescription": "Scoreboard stall cycles",
+ "Counter": "0,1,2,3",
+ "EventCode": "0xD2",
+ "EventName": "RAT_STALLS.SCOREBOARD",
+ "SampleAfterValue": "2000000",
+ "UMask": "0x8"
+ },
{
"BriefDescription": "Resource related stall cycles",
"Counter": "0,1,2,3",
@@ -894,4 +958,4 @@
"SampleAfterValue": "2000000",
"UMask": "0x1"
}
-]
\ No newline at end of file
+]
--
2.36.0.rc0.470.gd361397f0d-goog
^ permalink raw reply related [flat|nested] 19+ messages in thread
* [PATCH 12/14] perf vendor events intel: Update elkhartlake event topics
2022-04-13 21:04 [PATCH 01/14] perf vendor events intel: Fix icelake cstate metrics Ian Rogers
` (8 preceding siblings ...)
2022-04-13 21:05 ` [PATCH 11/14] perf vendor events intel: Update westmereex " Ian Rogers
@ 2022-04-13 21:05 ` Ian Rogers
2022-04-13 21:05 ` [PATCH 13/14] perf vendor events intel: Update goldmontplus " Ian Rogers
` (3 subsequent siblings)
13 siblings, 0 replies; 19+ messages in thread
From: Ian Rogers @ 2022-04-13 21:05 UTC (permalink / raw)
To: Peter Zijlstra, Ingo Molnar, Arnaldo Carvalho de Melo,
Mark Rutland, Alexander Shishkin, Jiri Olsa, Namhyung Kim,
Maxime Coquelin, Alexandre Torgue, Kan Liang, Xing Zhengjun,
Andi Kleen, John Garry, James Clark, linux-kernel,
linux-perf-users
Cc: Ian Rogers
Apply topic updates from:
https://github.com/intel/event-converter-for-linux-perf/
Signed-off-by: Ian Rogers <irogers@google.com>
---
.../perf/pmu-events/arch/x86/elkhartlake/other.json | 13 +------------
.../pmu-events/arch/x86/elkhartlake/pipeline.json | 13 ++++++++++++-
2 files changed, 13 insertions(+), 13 deletions(-)
diff --git a/tools/perf/pmu-events/arch/x86/elkhartlake/other.json b/tools/perf/pmu-events/arch/x86/elkhartlake/other.json
index de55b199ba79..8692d4847476 100644
--- a/tools/perf/pmu-events/arch/x86/elkhartlake/other.json
+++ b/tools/perf/pmu-events/arch/x86/elkhartlake/other.json
@@ -1,15 +1,4 @@
[
- {
- "BriefDescription": "Counts the total number of BTCLEARS.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
- "EventCode": "0xe8",
- "EventName": "BTCLEAR.ANY",
- "PDIR_COUNTER": "na",
- "PEBScounters": "0,1,2,3",
- "PublicDescription": "Counts the total number of BTCLEARS which occurs when the Branch Target Buffer (BTB) predicts a taken branch.",
- "SampleAfterValue": "200003"
- },
{
"BriefDescription": "This event is deprecated. Refer to new event BUS_LOCK.SELF_LOCKS",
"CollectPEBSRecord": "2",
@@ -180,4 +169,4 @@
"SampleAfterValue": "100003",
"UMask": "0x1"
}
-]
\ No newline at end of file
+]
diff --git a/tools/perf/pmu-events/arch/x86/elkhartlake/pipeline.json b/tools/perf/pmu-events/arch/x86/elkhartlake/pipeline.json
index 31816c6543a8..c18acb422145 100644
--- a/tools/perf/pmu-events/arch/x86/elkhartlake/pipeline.json
+++ b/tools/perf/pmu-events/arch/x86/elkhartlake/pipeline.json
@@ -153,6 +153,17 @@
"SampleAfterValue": "200003",
"UMask": "0xfe"
},
+ {
+ "BriefDescription": "Counts the total number of BTCLEARS.",
+ "CollectPEBSRecord": "2",
+ "Counter": "0,1,2,3",
+ "EventCode": "0xe8",
+ "EventName": "BTCLEAR.ANY",
+ "PDIR_COUNTER": "na",
+ "PEBScounters": "0,1,2,3",
+ "PublicDescription": "Counts the total number of BTCLEARS which occurs when the Branch Target Buffer (BTB) predicts a taken branch.",
+ "SampleAfterValue": "200003"
+ },
{
"BriefDescription": "Counts the number of unhalted core clock cycles. (Fixed event)",
"CollectPEBSRecord": "2",
@@ -516,4 +527,4 @@
"SampleAfterValue": "2000003",
"UMask": "0x1"
}
-]
\ No newline at end of file
+]
--
2.36.0.rc0.470.gd361397f0d-goog
^ permalink raw reply related [flat|nested] 19+ messages in thread
* [PATCH 13/14] perf vendor events intel: Update goldmontplus event topics
2022-04-13 21:04 [PATCH 01/14] perf vendor events intel: Fix icelake cstate metrics Ian Rogers
` (9 preceding siblings ...)
2022-04-13 21:05 ` [PATCH 12/14] perf vendor events intel: Update elkhartlake " Ian Rogers
@ 2022-04-13 21:05 ` Ian Rogers
2022-04-13 21:05 ` [PATCH 14/14] perf vendor events intel: Update goldmont " Ian Rogers
` (2 subsequent siblings)
13 siblings, 0 replies; 19+ messages in thread
From: Ian Rogers @ 2022-04-13 21:05 UTC (permalink / raw)
To: Peter Zijlstra, Ingo Molnar, Arnaldo Carvalho de Melo,
Mark Rutland, Alexander Shishkin, Jiri Olsa, Namhyung Kim,
Maxime Coquelin, Alexandre Torgue, Kan Liang, Xing Zhengjun,
Andi Kleen, John Garry, James Clark, linux-kernel,
linux-perf-users
Cc: Ian Rogers
Apply topic updates from:
https://github.com/intel/event-converter-for-linux-perf/
Signed-off-by: Ian Rogers <irogers@google.com>
---
.../arch/x86/goldmontplus/other.json | 37 +------------------
.../arch/x86/goldmontplus/pipeline.json | 37 ++++++++++++++++++-
2 files changed, 37 insertions(+), 37 deletions(-)
diff --git a/tools/perf/pmu-events/arch/x86/goldmontplus/other.json b/tools/perf/pmu-events/arch/x86/goldmontplus/other.json
index 3378f48cb818..92586fe4538a 100644
--- a/tools/perf/pmu-events/arch/x86/goldmontplus/other.json
+++ b/tools/perf/pmu-events/arch/x86/goldmontplus/other.json
@@ -57,40 +57,5 @@
"PublicDescription": "Counts hardware interrupts received by the processor.",
"SampleAfterValue": "203",
"UMask": "0x1"
- },
- {
- "BriefDescription": "Unfilled issue slots per cycle",
- "CollectPEBSRecord": "1",
- "Counter": "0,1,2,3",
- "EventCode": "0xCA",
- "EventName": "ISSUE_SLOTS_NOT_CONSUMED.ANY",
- "PDIR_COUNTER": "na",
- "PEBScounters": "0,1,2,3",
- "PublicDescription": "Counts the number of issue slots per core cycle that were not consumed by the backend due to either a full resource in the backend (RESOURCE_FULL) or due to the processor recovering from some event (RECOVERY).",
- "SampleAfterValue": "200003"
- },
- {
- "BriefDescription": "Unfilled issue slots per cycle to recover",
- "CollectPEBSRecord": "1",
- "Counter": "0,1,2,3",
- "EventCode": "0xCA",
- "EventName": "ISSUE_SLOTS_NOT_CONSUMED.RECOVERY",
- "PDIR_COUNTER": "na",
- "PEBScounters": "0,1,2,3",
- "PublicDescription": "Counts the number of issue slots per core cycle that were not consumed by the backend because allocation is stalled waiting for a mispredicted jump to retire or other branch-like conditions (e.g. the event is relevant during certain microcode flows). Counts all issue slots blocked while within this window including slots where uops were not available in the Instruction Queue.",
- "SampleAfterValue": "200003",
- "UMask": "0x2"
- },
- {
- "BriefDescription": "Unfilled issue slots per cycle because of a full resource in the backend",
- "CollectPEBSRecord": "1",
- "Counter": "0,1,2,3",
- "EventCode": "0xCA",
- "EventName": "ISSUE_SLOTS_NOT_CONSUMED.RESOURCE_FULL",
- "PDIR_COUNTER": "na",
- "PEBScounters": "0,1,2,3",
- "PublicDescription": "Counts the number of issue slots per core cycle that were not consumed because of a full resource in the backend. Including but not limited to resources such as the Re-order Buffer (ROB), reservation stations (RS), load/store buffers, physical registers, or any other needed machine resource that is currently unavailable. Note that uops must be available for consumption in order for this event to fire. If a uop is not available (Instruction Queue is empty), this event will not count.",
- "SampleAfterValue": "200003",
- "UMask": "0x1"
}
-]
\ No newline at end of file
+]
diff --git a/tools/perf/pmu-events/arch/x86/goldmontplus/pipeline.json b/tools/perf/pmu-events/arch/x86/goldmontplus/pipeline.json
index 8305e2ecf617..4d7e3129e5ac 100644
--- a/tools/perf/pmu-events/arch/x86/goldmontplus/pipeline.json
+++ b/tools/perf/pmu-events/arch/x86/goldmontplus/pipeline.json
@@ -290,6 +290,41 @@
"PublicDescription": "Counts INST_RETIRED.ANY using the Reduced Skid PEBS feature that reduces the shadow in which events aren't counted allowing for a more unbiased distribution of samples across instructions retired.",
"SampleAfterValue": "2000003"
},
+ {
+ "BriefDescription": "Unfilled issue slots per cycle",
+ "CollectPEBSRecord": "1",
+ "Counter": "0,1,2,3",
+ "EventCode": "0xCA",
+ "EventName": "ISSUE_SLOTS_NOT_CONSUMED.ANY",
+ "PDIR_COUNTER": "na",
+ "PEBScounters": "0,1,2,3",
+ "PublicDescription": "Counts the number of issue slots per core cycle that were not consumed by the backend due to either a full resource in the backend (RESOURCE_FULL) or due to the processor recovering from some event (RECOVERY).",
+ "SampleAfterValue": "200003"
+ },
+ {
+ "BriefDescription": "Unfilled issue slots per cycle to recover",
+ "CollectPEBSRecord": "1",
+ "Counter": "0,1,2,3",
+ "EventCode": "0xCA",
+ "EventName": "ISSUE_SLOTS_NOT_CONSUMED.RECOVERY",
+ "PDIR_COUNTER": "na",
+ "PEBScounters": "0,1,2,3",
+ "PublicDescription": "Counts the number of issue slots per core cycle that were not consumed by the backend because allocation is stalled waiting for a mispredicted jump to retire or other branch-like conditions (e.g. the event is relevant during certain microcode flows). Counts all issue slots blocked while within this window including slots where uops were not available in the Instruction Queue.",
+ "SampleAfterValue": "200003",
+ "UMask": "0x2"
+ },
+ {
+ "BriefDescription": "Unfilled issue slots per cycle because of a full resource in the backend",
+ "CollectPEBSRecord": "1",
+ "Counter": "0,1,2,3",
+ "EventCode": "0xCA",
+ "EventName": "ISSUE_SLOTS_NOT_CONSUMED.RESOURCE_FULL",
+ "PDIR_COUNTER": "na",
+ "PEBScounters": "0,1,2,3",
+ "PublicDescription": "Counts the number of issue slots per core cycle that were not consumed because of a full resource in the backend. Including but not limited to resources such as the Re-order Buffer (ROB), reservation stations (RS), load/store buffers, physical registers, or any other needed machine resource that is currently unavailable. Note that uops must be available for consumption in order for this event to fire. If a uop is not available (Instruction Queue is empty), this event will not count.",
+ "SampleAfterValue": "200003",
+ "UMask": "0x1"
+ },
{
"BriefDescription": "Loads blocked because address has 4k partial address false dependence (Precise event capable)",
"CollectPEBSRecord": "2",
@@ -456,4 +491,4 @@
"SampleAfterValue": "2000003",
"UMask": "0x1"
}
-]
\ No newline at end of file
+]
--
2.36.0.rc0.470.gd361397f0d-goog
^ permalink raw reply related [flat|nested] 19+ messages in thread
* [PATCH 14/14] perf vendor events intel: Update goldmont event topics
2022-04-13 21:04 [PATCH 01/14] perf vendor events intel: Fix icelake cstate metrics Ian Rogers
` (10 preceding siblings ...)
2022-04-13 21:05 ` [PATCH 13/14] perf vendor events intel: Update goldmontplus " Ian Rogers
@ 2022-04-13 21:05 ` Ian Rogers
2022-04-14 12:11 ` [PATCH 01/14] perf vendor events intel: Fix icelake cstate metrics Arnaldo Carvalho de Melo
[not found] ` <20220413210503.3256922-3-irogers@google.com>
13 siblings, 0 replies; 19+ messages in thread
From: Ian Rogers @ 2022-04-13 21:05 UTC (permalink / raw)
To: Peter Zijlstra, Ingo Molnar, Arnaldo Carvalho de Melo,
Mark Rutland, Alexander Shishkin, Jiri Olsa, Namhyung Kim,
Maxime Coquelin, Alexandre Torgue, Kan Liang, Xing Zhengjun,
Andi Kleen, John Garry, James Clark, linux-kernel,
linux-perf-users
Cc: Ian Rogers
Apply topic updates from:
https://github.com/intel/event-converter-for-linux-perf/
Signed-off-by: Ian Rogers <irogers@google.com>
---
.../pmu-events/arch/x86/goldmont/other.json | 31 +------------------
.../arch/x86/goldmont/pipeline.json | 31 ++++++++++++++++++-
2 files changed, 31 insertions(+), 31 deletions(-)
diff --git a/tools/perf/pmu-events/arch/x86/goldmont/other.json b/tools/perf/pmu-events/arch/x86/goldmont/other.json
index e4605e636447..d888f67aa2ea 100644
--- a/tools/perf/pmu-events/arch/x86/goldmont/other.json
+++ b/tools/perf/pmu-events/arch/x86/goldmont/other.json
@@ -47,34 +47,5 @@
"PublicDescription": "Counts hardware interrupts received by the processor.",
"SampleAfterValue": "203",
"UMask": "0x1"
- },
- {
- "BriefDescription": "Unfilled issue slots per cycle",
- "CollectPEBSRecord": "1",
- "Counter": "0,1,2,3",
- "EventCode": "0xCA",
- "EventName": "ISSUE_SLOTS_NOT_CONSUMED.ANY",
- "PublicDescription": "Counts the number of issue slots per core cycle that were not consumed by the backend due to either a full resource in the backend (RESOURCE_FULL) or due to the processor recovering from some event (RECOVERY).",
- "SampleAfterValue": "200003"
- },
- {
- "BriefDescription": "Unfilled issue slots per cycle to recover",
- "CollectPEBSRecord": "1",
- "Counter": "0,1,2,3",
- "EventCode": "0xCA",
- "EventName": "ISSUE_SLOTS_NOT_CONSUMED.RECOVERY",
- "PublicDescription": "Counts the number of issue slots per core cycle that were not consumed by the backend because allocation is stalled waiting for a mispredicted jump to retire or other branch-like conditions (e.g. the event is relevant during certain microcode flows). Counts all issue slots blocked while within this window including slots where uops were not available in the Instruction Queue.",
- "SampleAfterValue": "200003",
- "UMask": "0x2"
- },
- {
- "BriefDescription": "Unfilled issue slots per cycle because of a full resource in the backend",
- "CollectPEBSRecord": "1",
- "Counter": "0,1,2,3",
- "EventCode": "0xCA",
- "EventName": "ISSUE_SLOTS_NOT_CONSUMED.RESOURCE_FULL",
- "PublicDescription": "Counts the number of issue slots per core cycle that were not consumed because of a full resource in the backend. Including but not limited to resources such as the Re-order Buffer (ROB), reservation stations (RS), load/store buffers, physical registers, or any other needed machine resource that is currently unavailable. Note that uops must be available for consumption in order for this event to fire. If a uop is not available (Instruction Queue is empty), this event will not count.",
- "SampleAfterValue": "200003",
- "UMask": "0x1"
}
-]
\ No newline at end of file
+]
diff --git a/tools/perf/pmu-events/arch/x86/goldmont/pipeline.json b/tools/perf/pmu-events/arch/x86/goldmont/pipeline.json
index cb9155c3836d..5dba4313013f 100644
--- a/tools/perf/pmu-events/arch/x86/goldmont/pipeline.json
+++ b/tools/perf/pmu-events/arch/x86/goldmont/pipeline.json
@@ -245,6 +245,35 @@
"PublicDescription": "Counts the number of instructions that retire execution. For instructions that consist of multiple uops, this event counts the retirement of the last uop of the instruction. The event continues counting during hardware interrupts, traps, and inside interrupt handlers. This is an architectural performance event. This event uses a (_P)rogrammable general purpose performance counter. *This event is Precise Event capable: The EventingRIP field in the PEBS record is precise to the address of the instruction which caused the event. Note: Because PEBS records can be collected only on IA32_PMC0, only one event can use the PEBS facility at a time.",
"SampleAfterValue": "2000003"
},
+ {
+ "BriefDescription": "Unfilled issue slots per cycle",
+ "CollectPEBSRecord": "1",
+ "Counter": "0,1,2,3",
+ "EventCode": "0xCA",
+ "EventName": "ISSUE_SLOTS_NOT_CONSUMED.ANY",
+ "PublicDescription": "Counts the number of issue slots per core cycle that were not consumed by the backend due to either a full resource in the backend (RESOURCE_FULL) or due to the processor recovering from some event (RECOVERY).",
+ "SampleAfterValue": "200003"
+ },
+ {
+ "BriefDescription": "Unfilled issue slots per cycle to recover",
+ "CollectPEBSRecord": "1",
+ "Counter": "0,1,2,3",
+ "EventCode": "0xCA",
+ "EventName": "ISSUE_SLOTS_NOT_CONSUMED.RECOVERY",
+ "PublicDescription": "Counts the number of issue slots per core cycle that were not consumed by the backend because allocation is stalled waiting for a mispredicted jump to retire or other branch-like conditions (e.g. the event is relevant during certain microcode flows). Counts all issue slots blocked while within this window including slots where uops were not available in the Instruction Queue.",
+ "SampleAfterValue": "200003",
+ "UMask": "0x2"
+ },
+ {
+ "BriefDescription": "Unfilled issue slots per cycle because of a full resource in the backend",
+ "CollectPEBSRecord": "1",
+ "Counter": "0,1,2,3",
+ "EventCode": "0xCA",
+ "EventName": "ISSUE_SLOTS_NOT_CONSUMED.RESOURCE_FULL",
+ "PublicDescription": "Counts the number of issue slots per core cycle that were not consumed because of a full resource in the backend. Including but not limited to resources such as the Re-order Buffer (ROB), reservation stations (RS), load/store buffers, physical registers, or any other needed machine resource that is currently unavailable. Note that uops must be available for consumption in order for this event to fire. If a uop is not available (Instruction Queue is empty), this event will not count.",
+ "SampleAfterValue": "200003",
+ "UMask": "0x1"
+ },
{
"BriefDescription": "Loads blocked because address has 4k partial address false dependence (Precise event capable)",
"CollectPEBSRecord": "2",
@@ -379,4 +408,4 @@
"SampleAfterValue": "2000003",
"UMask": "0x1"
}
-]
\ No newline at end of file
+]
--
2.36.0.rc0.470.gd361397f0d-goog
^ permalink raw reply related [flat|nested] 19+ messages in thread
* Re: [PATCH 01/14] perf vendor events intel: Fix icelake cstate metrics
2022-04-13 21:04 [PATCH 01/14] perf vendor events intel: Fix icelake cstate metrics Ian Rogers
` (11 preceding siblings ...)
2022-04-13 21:05 ` [PATCH 14/14] perf vendor events intel: Update goldmont " Ian Rogers
@ 2022-04-14 12:11 ` Arnaldo Carvalho de Melo
[not found] ` <20220413210503.3256922-3-irogers@google.com>
13 siblings, 0 replies; 19+ messages in thread
From: Arnaldo Carvalho de Melo @ 2022-04-14 12:11 UTC (permalink / raw)
To: Ian Rogers
Cc: Peter Zijlstra, Ingo Molnar, Mark Rutland, Alexander Shishkin,
Jiri Olsa, Namhyung Kim, Maxime Coquelin, Alexandre Torgue,
Kan Liang, Xing Zhengjun, Andi Kleen, John Garry, James Clark,
linux-kernel, linux-perf-users
Em Wed, Apr 13, 2022 at 02:04:50PM -0700, Ian Rogers escreveu:
> Apply cstate fix from:
> https://github.com/intel/event-converter-for-linux-perf/
> so that metrics for cstates that exist on the particular architecture
> are generated. This corrects issues with metric testing.
>
> Also correct topic of ASSISTS.ANY event.
I would really appreciate acks/reviewed-by tags for these,
Thanks!
- Arnaldo
> Signed-off-by: Ian Rogers <irogers@google.com>
> ---
> .../arch/x86/icelake/icl-metrics.json | 24 ++++++++++++++-----
> .../pmu-events/arch/x86/icelake/other.json | 14 +----------
> .../pmu-events/arch/x86/icelake/pipeline.json | 14 ++++++++++-
> 3 files changed, 32 insertions(+), 20 deletions(-)
>
> diff --git a/tools/perf/pmu-events/arch/x86/icelake/icl-metrics.json b/tools/perf/pmu-events/arch/x86/icelake/icl-metrics.json
> index 4af23c04dc18..ea73bc1889ba 100644
> --- a/tools/perf/pmu-events/arch/x86/icelake/icl-metrics.json
> +++ b/tools/perf/pmu-events/arch/x86/icelake/icl-metrics.json
> @@ -408,12 +408,6 @@
> "MetricGroup": "Branches;OS",
> "MetricName": "IpFarBranch"
> },
> - {
> - "BriefDescription": "C3 residency percent per core",
> - "MetricExpr": "(cstate_core@c3\\-residency@ / msr@tsc@) * 100",
> - "MetricGroup": "Power",
> - "MetricName": "C3_Core_Residency"
> - },
> {
> "BriefDescription": "C6 residency percent per core",
> "MetricExpr": "(cstate_core@c6\\-residency@ / msr@tsc@) * 100",
> @@ -449,5 +443,23 @@
> "MetricExpr": "(cstate_pkg@c7\\-residency@ / msr@tsc@) * 100",
> "MetricGroup": "Power",
> "MetricName": "C7_Pkg_Residency"
> + },
> + {
> + "BriefDescription": "C8 residency percent per package",
> + "MetricExpr": "(cstate_pkg@c8\\-residency@ / msr@tsc@) * 100",
> + "MetricGroup": "Power",
> + "MetricName": "C8_Pkg_Residency"
> + },
> + {
> + "BriefDescription": "C9 residency percent per package",
> + "MetricExpr": "(cstate_pkg@c9\\-residency@ / msr@tsc@) * 100",
> + "MetricGroup": "Power",
> + "MetricName": "C9_Pkg_Residency"
> + },
> + {
> + "BriefDescription": "C10 residency percent per package",
> + "MetricExpr": "(cstate_pkg@c10\\-residency@ / msr@tsc@) * 100",
> + "MetricGroup": "Power",
> + "MetricName": "C10_Pkg_Residency"
> }
> ]
> diff --git a/tools/perf/pmu-events/arch/x86/icelake/other.json b/tools/perf/pmu-events/arch/x86/icelake/other.json
> index 08f6321025e8..2e177f95a9cb 100644
> --- a/tools/perf/pmu-events/arch/x86/icelake/other.json
> +++ b/tools/perf/pmu-events/arch/x86/icelake/other.json
> @@ -1,16 +1,4 @@
> [
> - {
> - "BriefDescription": "Number of occurrences where a microcode assist is invoked by hardware.",
> - "CollectPEBSRecord": "2",
> - "Counter": "0,1,2,3,4,5,6,7",
> - "EventCode": "0xc1",
> - "EventName": "ASSISTS.ANY",
> - "PEBScounters": "0,1,2,3,4,5,6,7",
> - "PublicDescription": "Counts the number of occurrences where a microcode assist is invoked by hardware Examples include AD (page Access Dirty), FP and AVX related assists.",
> - "SampleAfterValue": "100003",
> - "Speculative": "1",
> - "UMask": "0x7"
> - },
> {
> "BriefDescription": "Core cycles where the core was running in a manner where Turbo may be clipped to the Non-AVX turbo schedule.",
> "CollectPEBSRecord": "2",
> @@ -407,4 +395,4 @@
> "Speculative": "1",
> "UMask": "0x1"
> }
> -]
> \ No newline at end of file
> +]
> diff --git a/tools/perf/pmu-events/arch/x86/icelake/pipeline.json b/tools/perf/pmu-events/arch/x86/icelake/pipeline.json
> index 573ac7ac8879..2b58cfaaaf39 100644
> --- a/tools/perf/pmu-events/arch/x86/icelake/pipeline.json
> +++ b/tools/perf/pmu-events/arch/x86/icelake/pipeline.json
> @@ -12,6 +12,18 @@
> "Speculative": "1",
> "UMask": "0x9"
> },
> + {
> + "BriefDescription": "Number of occurrences where a microcode assist is invoked by hardware.",
> + "CollectPEBSRecord": "2",
> + "Counter": "0,1,2,3,4,5,6,7",
> + "EventCode": "0xc1",
> + "EventName": "ASSISTS.ANY",
> + "PEBScounters": "0,1,2,3,4,5,6,7",
> + "PublicDescription": "Counts the number of occurrences where a microcode assist is invoked by hardware Examples include AD (page Access Dirty), FP and AVX related assists.",
> + "SampleAfterValue": "100003",
> + "Speculative": "1",
> + "UMask": "0x7"
> + },
> {
> "BriefDescription": "All branch instructions retired.",
> "CollectPEBSRecord": "2",
> @@ -1102,4 +1114,4 @@
> "SampleAfterValue": "1000003",
> "UMask": "0x2"
> }
> -]
> \ No newline at end of file
> +]
> --
> 2.36.0.rc0.470.gd361397f0d-goog
--
- Arnaldo
^ permalink raw reply [flat|nested] 19+ messages in thread
[parent not found: <20220413210503.3256922-3-irogers@google.com>]
* Re: [PATCH 03/14] perf vendor events intel: Add sapphirerapids events
[not found] ` <20220413210503.3256922-3-irogers@google.com>
@ 2022-04-14 15:03 ` Liang, Kan
2022-04-14 16:36 ` Ian Rogers
2022-04-18 15:39 ` Arnaldo Carvalho de Melo
0 siblings, 2 replies; 19+ messages in thread
From: Liang, Kan @ 2022-04-14 15:03 UTC (permalink / raw)
To: Ian Rogers, Peter Zijlstra, Ingo Molnar, Arnaldo Carvalho de Melo,
Mark Rutland, Alexander Shishkin, Jiri Olsa, Namhyung Kim,
Maxime Coquelin, Alexandre Torgue, Xing Zhengjun, Andi Kleen,
John Garry, James Clark, linux-kernel, linux-perf-users
On 4/13/2022 5:04 PM, Ian Rogers wrote:
> Events were generated from 01.org using:
> https://github.com/intel/event-converter-for-linux-perf
>
> Signed-off-by: Ian Rogers<irogers@google.com>
> ---
> tools/perf/pmu-events/arch/x86/mapfile.csv | 1 +
> .../arch/x86/sapphirerapids/cache.json | 1083 ++++++++++++++
> .../x86/sapphirerapids/floating-point.json | 218 +++
> .../arch/x86/sapphirerapids/frontend.json | 471 ++++++
> .../arch/x86/sapphirerapids/memory.json | 415 ++++++
> .../arch/x86/sapphirerapids/other.json | 329 +++++
> .../arch/x86/sapphirerapids/pipeline.json | 1271 +++++++++++++++++
> .../x86/sapphirerapids/virtual-memory.json | 225 +++
Thank you very much Ian for the patches. They all looks good to me.
Reviewed-by: Kan Liang <kan.liang@linux.intel.com>
BTW: I think the uncore events for SPR are also published in 01.org.
Do you have plan to add them later?
Thanks,
Kan
^ permalink raw reply [flat|nested] 19+ messages in thread
* Re: [PATCH 03/14] perf vendor events intel: Add sapphirerapids events
2022-04-14 15:03 ` [PATCH 03/14] perf vendor events intel: Add sapphirerapids events Liang, Kan
@ 2022-04-14 16:36 ` Ian Rogers
2022-04-14 18:25 ` Liang, Kan
2022-04-18 15:39 ` Arnaldo Carvalho de Melo
1 sibling, 1 reply; 19+ messages in thread
From: Ian Rogers @ 2022-04-14 16:36 UTC (permalink / raw)
To: Liang, Kan
Cc: Peter Zijlstra, Ingo Molnar, Arnaldo Carvalho de Melo,
Mark Rutland, Alexander Shishkin, Jiri Olsa, Namhyung Kim,
Maxime Coquelin, Alexandre Torgue, Xing Zhengjun, Andi Kleen,
John Garry, James Clark, linux-kernel, linux-perf-users
On Thu, Apr 14, 2022 at 8:03 AM Liang, Kan <kan.liang@linux.intel.com> wrote:
>
>
>
> On 4/13/2022 5:04 PM, Ian Rogers wrote:
> > Events were generated from 01.org using:
> > https://github.com/intel/event-converter-for-linux-perf
> >
> > Signed-off-by: Ian Rogers<irogers@google.com>
> > ---
> > tools/perf/pmu-events/arch/x86/mapfile.csv | 1 +
> > .../arch/x86/sapphirerapids/cache.json | 1083 ++++++++++++++
> > .../x86/sapphirerapids/floating-point.json | 218 +++
> > .../arch/x86/sapphirerapids/frontend.json | 471 ++++++
> > .../arch/x86/sapphirerapids/memory.json | 415 ++++++
> > .../arch/x86/sapphirerapids/other.json | 329 +++++
> > .../arch/x86/sapphirerapids/pipeline.json | 1271 +++++++++++++++++
> > .../x86/sapphirerapids/virtual-memory.json | 225 +++
>
> Thank you very much Ian for the patches. They all looks good to me.
>
> Reviewed-by: Kan Liang <kan.liang@linux.intel.com>
>
> BTW: I think the uncore events for SPR are also published in 01.org.
> Do you have plan to add them later?
Thanks Kan, we need to add the csv file to the github project to make
this work. I can make a basic one if that works?
Thanks,
Ian
> Thanks,
> Kan
^ permalink raw reply [flat|nested] 19+ messages in thread
* Re: [PATCH 03/14] perf vendor events intel: Add sapphirerapids events
2022-04-14 16:36 ` Ian Rogers
@ 2022-04-14 18:25 ` Liang, Kan
2022-04-15 2:59 ` Xing Zhengjun
0 siblings, 1 reply; 19+ messages in thread
From: Liang, Kan @ 2022-04-14 18:25 UTC (permalink / raw)
To: Ian Rogers, Xing Zhengjun
Cc: Peter Zijlstra, Ingo Molnar, Arnaldo Carvalho de Melo,
Mark Rutland, Alexander Shishkin, Jiri Olsa, Namhyung Kim,
Maxime Coquelin, Alexandre Torgue, Andi Kleen, John Garry,
James Clark, linux-kernel, linux-perf-users
On 4/14/2022 12:36 PM, Ian Rogers wrote:
> On Thu, Apr 14, 2022 at 8:03 AM Liang, Kan <kan.liang@linux.intel.com> wrote:
>>
>>
>>
>> On 4/13/2022 5:04 PM, Ian Rogers wrote:
>>> Events were generated from 01.org using:
>>> https://github.com/intel/event-converter-for-linux-perf
>>>
>>> Signed-off-by: Ian Rogers<irogers@google.com>
>>> ---
>>> tools/perf/pmu-events/arch/x86/mapfile.csv | 1 +
>>> .../arch/x86/sapphirerapids/cache.json | 1083 ++++++++++++++
>>> .../x86/sapphirerapids/floating-point.json | 218 +++
>>> .../arch/x86/sapphirerapids/frontend.json | 471 ++++++
>>> .../arch/x86/sapphirerapids/memory.json | 415 ++++++
>>> .../arch/x86/sapphirerapids/other.json | 329 +++++
>>> .../arch/x86/sapphirerapids/pipeline.json | 1271 +++++++++++++++++
>>> .../x86/sapphirerapids/virtual-memory.json | 225 +++
>>
>> Thank you very much Ian for the patches. They all looks good to me.
>>
>> Reviewed-by: Kan Liang <kan.liang@linux.intel.com>
>>
>> BTW: I think the uncore events for SPR are also published in 01.org.
>> Do you have plan to add them later?
>
> Thanks Kan, we need to add the csv file to the github project to make
> this work. I can make a basic one if that works?
>
I think Zhengjun may already have one. Zhengjun?
Thanks,
Kan
^ permalink raw reply [flat|nested] 19+ messages in thread
* Re: [PATCH 03/14] perf vendor events intel: Add sapphirerapids events
2022-04-14 18:25 ` Liang, Kan
@ 2022-04-15 2:59 ` Xing Zhengjun
0 siblings, 0 replies; 19+ messages in thread
From: Xing Zhengjun @ 2022-04-15 2:59 UTC (permalink / raw)
To: Liang, Kan, Ian Rogers
Cc: Peter Zijlstra, Ingo Molnar, Arnaldo Carvalho de Melo,
Mark Rutland, Alexander Shishkin, Jiri Olsa, Namhyung Kim,
Maxime Coquelin, Alexandre Torgue, Andi Kleen, John Garry,
James Clark, linux-kernel, linux-perf-users
On 4/15/2022 2:25 AM, Liang, Kan wrote:
>
>
> On 4/14/2022 12:36 PM, Ian Rogers wrote:
>> On Thu, Apr 14, 2022 at 8:03 AM Liang, Kan <kan.liang@linux.intel.com>
>> wrote:
>>>
>>>
>>>
>>> On 4/13/2022 5:04 PM, Ian Rogers wrote:
>>>> Events were generated from 01.org using:
>>>> https://github.com/intel/event-converter-for-linux-perf
>>>>
>>>> Signed-off-by: Ian Rogers<irogers@google.com>
>>>> ---
>>>> tools/perf/pmu-events/arch/x86/mapfile.csv | 1 +
>>>> .../arch/x86/sapphirerapids/cache.json | 1083 ++++++++++++++
>>>> .../x86/sapphirerapids/floating-point.json | 218 +++
>>>> .../arch/x86/sapphirerapids/frontend.json | 471 ++++++
>>>> .../arch/x86/sapphirerapids/memory.json | 415 ++++++
>>>> .../arch/x86/sapphirerapids/other.json | 329 +++++
>>>> .../arch/x86/sapphirerapids/pipeline.json | 1271
>>>> +++++++++++++++++
>>>> .../x86/sapphirerapids/virtual-memory.json | 225 +++
>>>
>>> Thank you very much Ian for the patches. They all looks good to me.
>>>
>>> Reviewed-by: Kan Liang <kan.liang@linux.intel.com>
>>>
>>> BTW: I think the uncore events for SPR are also published in 01.org.
>>> Do you have plan to add them later?
>>
>> Thanks Kan, we need to add the csv file to the github project to make
>> this work. I can make a basic one if that works?
>>
>
> I think Zhengjun may already have one. Zhengjun?
The CSV file for SPR has been added to the event convert tool, please
have a try.
>
> Thanks,
> Kan
--
Zhengjun Xing
^ permalink raw reply [flat|nested] 19+ messages in thread
* Re: [PATCH 03/14] perf vendor events intel: Add sapphirerapids events
2022-04-14 15:03 ` [PATCH 03/14] perf vendor events intel: Add sapphirerapids events Liang, Kan
2022-04-14 16:36 ` Ian Rogers
@ 2022-04-18 15:39 ` Arnaldo Carvalho de Melo
1 sibling, 0 replies; 19+ messages in thread
From: Arnaldo Carvalho de Melo @ 2022-04-18 15:39 UTC (permalink / raw)
To: Liang, Kan
Cc: Ian Rogers, Peter Zijlstra, Ingo Molnar, Mark Rutland,
Alexander Shishkin, Jiri Olsa, Namhyung Kim, Maxime Coquelin,
Alexandre Torgue, Xing Zhengjun, Andi Kleen, John Garry,
James Clark, linux-kernel, linux-perf-users
Em Thu, Apr 14, 2022 at 11:03:03AM -0400, Liang, Kan escreveu:
>
>
> On 4/13/2022 5:04 PM, Ian Rogers wrote:
> > Events were generated from 01.org using:
> > https://github.com/intel/event-converter-for-linux-perf
> >
> > Signed-off-by: Ian Rogers<irogers@google.com>
> > ---
> > tools/perf/pmu-events/arch/x86/mapfile.csv | 1 +
> > .../arch/x86/sapphirerapids/cache.json | 1083 ++++++++++++++
> > .../x86/sapphirerapids/floating-point.json | 218 +++
> > .../arch/x86/sapphirerapids/frontend.json | 471 ++++++
> > .../arch/x86/sapphirerapids/memory.json | 415 ++++++
> > .../arch/x86/sapphirerapids/other.json | 329 +++++
> > .../arch/x86/sapphirerapids/pipeline.json | 1271 +++++++++++++++++
> > .../x86/sapphirerapids/virtual-memory.json | 225 +++
>
> Thank you very much Ian for the patches. They all looks good to me.
>
> Reviewed-by: Kan Liang <kan.liang@linux.intel.com>
Next time please reply with the Reviewed-by to the cover letter (PATCH
00/14) so that the b4 tool can collect the Reviewed-by to all the
patches.
- Arnaldo
> BTW: I think the uncore events for SPR are also published in 01.org.
> Do you have plan to add them later?
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