[PATCH v14 5/7] drm/xe/pmu: Add attribute skeleton

Lucas De Marchi
2025-01-22T06:24:16Z

Add the generic support for defining new attributes. This uses
gt-c6-residency as first attribute to bootstrap it, but its
implementation will be added by a follow up commit: until proper support
is added, it will always be invisible in sysfs since the corresponding
bit is not set in the supported_events bitmap.

Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
drivers/gpu/drm/xe/xe_pmu.c | 46 +++++++++++++++++++++++++++++--
drivers/gpu/drm/xe/xe_pmu_types.h | 4 +++
2 files changed, 48 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/xe/xe_pmu.c b/drivers/gpu/drm/xe/xe_pmu.c
index 5a93634f17a2b..68ebec1746a53 100644
--- a/drivers/gpu/drm/xe/xe_pmu.c
+++ b/drivers/gpu/drm/xe/xe_pmu.c
@@ -54,6 +54,8 @@ static unsigned int config_to_gt_id(u64 config)
return FIELD_GET(XE_PMU_EVENT_GT_MASK, config);
}

+#define XE_PMU_EVENT_GT_C6_RESIDENCY 0x01
+
static struct xe_gt *event_to_gt(struct perf_event *event)
{
struct xe_device *xe = container_of(event->pmu, typeof(*xe), pmu.base);
@@ -68,7 +70,8 @@ static bool event_supported(struct xe_pmu *pmu, unsigned int gt,
if (gt >= XE_MAX_GT_PER_TILE)
return false;

- return false;
+ return id < sizeof(pmu->supported_events) * BITS_PER_BYTE &&
+ pmu->supported_events & BIT_ULL(id);
}

static void xe_pmu_event_destroy(struct perf_event *event)
@@ -218,16 +221,53 @@ static const struct attribute_group pmu_format_attr_group = {
.attrs = pmu_format_attrs,
};

+static ssize_t event_attr_show(struct device *dev,
+ struct device_attribute *attr, char *buf)
+{
+ struct perf_pmu_events_attr *pmu_attr =
+ container_of(attr, struct perf_pmu_events_attr, attr);
+
+ return sprintf(buf, "event=%#04llx\n", pmu_attr->id);
+}
+
+static umode_t event_attr_is_visible(struct kobject *kobj,
+ struct attribute *attr, int idx)
+{
+ struct device *dev = kobj_to_dev(kobj);
+ struct perf_pmu_events_attr *pmu_attr =
+ container_of(attr, typeof(*pmu_attr), attr.attr);
+ struct xe_pmu *pmu =
+ container_of(dev_get_drvdata(dev), typeof(*pmu), base);
+
+ if (event_supported(pmu, 0, pmu_attr->id))
+ return attr->mode;
+
+ return 0;
+}
+
+#define XE_EVENT_ATTR(name_, v_, id_, unit_) \
+ PMU_EVENT_ATTR(name_, pmu_event_ ## v_, id_, event_attr_show) \
+ PMU_EVENT_ATTR_ID_STRING(name_.unit, pmu_event_unit_ ## v_, id_, unit_)
+
+XE_EVENT_ATTR(gt-c6-residency, gt_c6_residency, XE_PMU_EVENT_GT_C6_RESIDENCY, "ms")
+
static struct attribute *pmu_event_attrs[] = {
- /* No events yet */
+ &pmu_event_gt_c6_residency.attr.attr,
+ &pmu_event_unit_gt_c6_residency.attr.attr,
+
NULL,
};

static const struct attribute_group pmu_events_attr_group = {
.name = "events",
.attrs = pmu_event_attrs,
+ .is_visible = event_attr_is_visible,
};

+static void set_supported_events(struct xe_pmu *pmu)
+{
+}
+
/**
* xe_pmu_unregister() - Remove/cleanup PMU registration
* @arg: Ptr to pmu
@@ -290,6 +330,8 @@ int xe_pmu_register(struct xe_pmu *pmu)
pmu->base.stop = xe_pmu_event_stop;
pmu->base.read = xe_pmu_event_read;

+ set_supported_events(pmu);
+
ret = perf_pmu_register(&pmu->base, pmu->name, -1);
if (ret)
goto err_name;
diff --git a/drivers/gpu/drm/xe/xe_pmu_types.h b/drivers/gpu/drm/xe/xe_pmu_types.h
index e0cf7169f4fda..64a1ca881c233 100644
--- a/drivers/gpu/drm/xe/xe_pmu_types.h
+++ b/drivers/gpu/drm/xe/xe_pmu_types.h
@@ -38,6 +38,10 @@ struct xe_pmu {
* @lock: Lock protecting enable mask and ref count handling.
*/
raw_spinlock_t lock;
+ /**
+ * @supported_events: Bitmap of supported events, indexed by event id
+ */
+ u64 supported_events;
};

#endif
--
2.48.0