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From: Fan Ni <nifan.cxl@gmail.com>
To: Shradha Todi <shradha.t@samsung.com>
Cc: linux-kernel@vger.kernel.org, linux-pci@vger.kernel.org,
	linux-arm-kernel@lists.infradead.org,
	linux-perf-users@vger.kernel.org,
	manivannan.sadhasivam@linaro.org, lpieralisi@kernel.org,
	kw@linux.com, robh@kernel.org, bhelgaas@google.com,
	jingoohan1@gmail.com, Jonathan.Cameron@huawei.com,
	nifan.cxl@gmail.com, a.manzanares@samsung.com,
	pankaj.dubey@samsung.com, cassel@kernel.org, 18255117159@163.com,
	xueshuai@linux.alibaba.com, renyu.zj@linux.alibaba.com,
	will@kernel.org, mark.rutland@arm.com
Subject: Re: [PATCH v7 5/5] Add debugfs based statistical counter support in DWC
Date: Mon, 3 Mar 2025 10:02:32 -0800	[thread overview]
Message-ID: <Z8XuuNb6TRevUlHH@debian> (raw)
In-Reply-To: <20250221131548.59616-6-shradha.t@samsung.com>

On Fri, Feb 21, 2025 at 06:45:48PM +0530, Shradha Todi wrote:
> Add support to provide statistical counter interface to userspace. This set
> of debug registers are part of the RASDES feature present in DesignWare
> PCIe controllers.
> 
One comment inline.
> Signed-off-by: Shradha Todi <shradha.t@samsung.com>
> ---
>  Documentation/ABI/testing/debugfs-dwc-pcie    |  61 +++++
>  .../controller/dwc/pcie-designware-debugfs.c  | 229 +++++++++++++++++-
>  2 files changed, 289 insertions(+), 1 deletion(-)
> 
> diff --git a/Documentation/ABI/testing/debugfs-dwc-pcie b/Documentation/ABI/testing/debugfs-dwc-pcie
> index 6ee0897fe753..650a89b0511e 100644
> --- a/Documentation/ABI/testing/debugfs-dwc-pcie
> +++ b/Documentation/ABI/testing/debugfs-dwc-pcie
> @@ -81,3 +81,64 @@ Description:	rasdes_err_inj is the directory which can be used to inject errors
>  
>  			<count>
>  				Number of errors to be injected

...

> +
> +static ssize_t counter_value_read(struct file *file, char __user *buf, size_t count, loff_t *ppos)
> +{
> +	struct dwc_pcie_rasdes_priv *pdata = file->private_data;
> +	struct dw_pcie *pci = pdata->pci;
> +	struct dwc_pcie_rasdes_info *rinfo = pci->debugfs->rasdes_info;
> +	char debugfs_buf[DWC_DEBUGFS_BUF_MAX];
> +	ssize_t pos;
> +	u32 val;
> +
> +	mutex_lock(&rinfo->reg_event_lock);
> +	set_event_number(pdata, pci, rinfo);
> +	val = dw_pcie_readl_dbi(pci, rinfo->ras_cap_offset + RAS_DES_EVENT_COUNTER_DATA_REG);
> +	mutex_unlock(&rinfo->reg_event_lock);
> +	pos = scnprintf(debugfs_buf, DWC_DEBUGFS_BUF_MAX, "Counter value: %d\n", val);
> +
> +	return simple_read_from_buffer(buf, count, ppos, debugfs_buf, pos);
> +}

Do we need to check whether the counter is enabled or not for the event
before retrieving the counter value?

Fan
> +
>  #define dwc_debugfs_create(name)			\
>  debugfs_create_file(#name, 0644, rasdes_debug, pci,	\
>  			&dbg_ ## name ## _fops)
> @@ -249,6 +436,23 @@ static const struct file_operations dwc_pcie_err_inj_ops = {
>  	.write = err_inj_write,
>  };
>  
> +static const struct file_operations dwc_pcie_counter_enable_ops = {
> +	.open = simple_open,
> +	.read = counter_enable_read,
> +	.write = counter_enable_write,
> +};
> +
> +static const struct file_operations dwc_pcie_counter_lane_ops = {
> +	.open = simple_open,
> +	.read = counter_lane_read,
> +	.write = counter_lane_write,
> +};
> +
> +static const struct file_operations dwc_pcie_counter_value_ops = {
> +	.open = simple_open,
> +	.read = counter_value_read,
> +};
> +
>  static void dwc_pcie_rasdes_debugfs_deinit(struct dw_pcie *pci)
>  {
>  	struct dwc_pcie_rasdes_info *rinfo = pci->debugfs->rasdes_info;
> @@ -258,7 +462,7 @@ static void dwc_pcie_rasdes_debugfs_deinit(struct dw_pcie *pci)
>  
>  static int dwc_pcie_rasdes_debugfs_init(struct dw_pcie *pci, struct dentry *dir)
>  {
> -	struct dentry *rasdes_debug, *rasdes_err_inj;
> +	struct dentry *rasdes_debug, *rasdes_err_inj, *rasdes_event_counter, *rasdes_events;
>  	struct dwc_pcie_rasdes_info *rasdes_info;
>  	struct dwc_pcie_rasdes_priv *priv_tmp;
>  	struct device *dev = pci->dev;
> @@ -277,6 +481,7 @@ static int dwc_pcie_rasdes_debugfs_init(struct dw_pcie *pci, struct dentry *dir)
>  	/* Create subdirectories for Debug, Error injection, Statistics */
>  	rasdes_debug = debugfs_create_dir("rasdes_debug", dir);
>  	rasdes_err_inj = debugfs_create_dir("rasdes_err_inj", dir);
> +	rasdes_event_counter = debugfs_create_dir("rasdes_event_counter", dir);
>  
>  	mutex_init(&rasdes_info->reg_event_lock);
>  	rasdes_info->ras_cap_offset = ras_cap;
> @@ -299,6 +504,28 @@ static int dwc_pcie_rasdes_debugfs_init(struct dw_pcie *pci, struct dentry *dir)
>  		debugfs_create_file(err_inj_list[i].name, 0200, rasdes_err_inj, priv_tmp,
>  				    &dwc_pcie_err_inj_ops);
>  	}
> +
> +	/* Create debugfs files for Statistical counter subdirectory */
> +	for (i = 0; i < ARRAY_SIZE(event_list); i++) {
> +		priv_tmp = devm_kzalloc(dev, sizeof(*priv_tmp), GFP_KERNEL);
> +		if (!priv_tmp) {
> +			ret = -ENOMEM;
> +			goto err_deinit;
> +		}
> +
> +		priv_tmp->idx = i;
> +		priv_tmp->pci = pci;
> +		rasdes_events = debugfs_create_dir(event_list[i].name, rasdes_event_counter);
> +		if (event_list[i].group_no == 0 || event_list[i].group_no == 4) {
> +			debugfs_create_file("lane_select", 0644, rasdes_events,
> +					    priv_tmp, &dwc_pcie_counter_lane_ops);
> +		}
> +		debugfs_create_file("counter_value", 0444, rasdes_events, priv_tmp,
> +				    &dwc_pcie_counter_value_ops);
> +		debugfs_create_file("counter_enable", 0644, rasdes_events, priv_tmp,
> +				    &dwc_pcie_counter_enable_ops);
> +	}
> +
>  	return 0;
>  
>  err_deinit:
> -- 
> 2.17.1
> 

  parent reply	other threads:[~2025-03-03 18:02 UTC|newest]

Thread overview: 57+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
     [not found] <CGME20250221132011epcas5p4dea1e9ae5c09afaabcd1822f3a7d15c5@epcas5p4.samsung.com>
2025-02-21 13:15 ` [PATCH v7 0/5] Add support for debugfs based RAS DES feature in PCIe DW Shradha Todi
     [not found]   ` <CGME20250221132024epcas5p13d6e617805e4ef0c081227b08119871b@epcas5p1.samsung.com>
2025-02-21 13:15     ` [PATCH v7 1/5] perf/dwc_pcie: Move common DWC struct definitions to 'pcie-dwc.h' Shradha Todi
2025-02-25 14:47       ` Krzysztof Wilczyński
2025-02-26  1:55       ` Shuai Xue
2025-02-26  6:48         ` Krzysztof Wilczyński
2025-03-03 17:19       ` Fan Ni
     [not found]   ` <CGME20250221132029epcas5p1e56dd355e7ac912ceb25325595de0d24@epcas5p1.samsung.com>
2025-02-21 13:15     ` [PATCH v7 2/5] PCI: dwc: Add helper to find the Vendor Specific Extended Capability (VSEC) Shradha Todi
2025-03-03 17:22       ` Fan Ni
     [not found]   ` <CGME20250221132035epcas5p47221a5198df9bf86020abcefdfded789@epcas5p4.samsung.com>
2025-02-21 13:15     ` [PATCH v7 3/5] Add debugfs based silicon debug support in DWC Shradha Todi
2025-02-23  8:51       ` Manivannan Sadhasivam
2025-03-03 17:48       ` Fan Ni
2025-03-03 19:46         ` Krzysztof Wilczyński
2025-03-03 20:50           ` Fan Ni
2025-03-04  6:44             ` Krzysztof Wilczyński
2025-03-04 14:54           ` Geert Uytterhoeven
2025-03-04 14:57           ` Geert Uytterhoeven
2025-03-04 15:46             ` Krzysztof Wilczyński
2025-03-04 16:52               ` Shradha Todi
2025-03-05  7:44                 ` 'Krzysztof Wilczyński'
2025-03-05  9:04                   ` Shradha Todi
2025-03-04 17:11               ` Manivannan Sadhasivam
2025-03-04 17:58                 ` Krzysztof Wilczyński
2025-03-05 17:38                 ` Bjorn Helgaas
2025-03-05 18:28                   ` Manivannan Sadhasivam
2025-03-05 19:09                     ` Krzysztof Wilczyński
2025-03-05 21:57                       ` Krzysztof Wilczyński
2025-03-06  8:22                       ` Geert Uytterhoeven
2025-03-06  9:02                         ` Krzysztof Wilczyński
2025-03-07  9:37                           ` Shradha Todi
2025-03-04 15:18           ` Manivannan Sadhasivam
     [not found]   ` <CGME20250221132039epcas5p31913eab0acec1eb5e7874897a084c725@epcas5p3.samsung.com>
2025-02-21 13:15     ` [PATCH v7 4/5] Add debugfs based error injection " Shradha Todi
2025-02-23  8:53       ` Manivannan Sadhasivam
2025-03-03  9:52       ` Krzysztof Wilczyński
2025-03-04  6:50         ` Krzysztof Wilczyński
2025-03-04 15:29         ` Manivannan Sadhasivam
2025-03-04 15:35           ` Krzysztof Wilczyński
2025-03-04 17:00             ` Shradha Todi
2025-03-05  7:26               ` 'Krzysztof Wilczyński'
2025-03-03 17:53       ` Fan Ni
     [not found]   ` <CGME20250221132043epcas5p27fde98558b13b3311cdc467e8f246380@epcas5p2.samsung.com>
2025-02-21 13:15     ` [PATCH v7 5/5] Add debugfs based statistical counter " Shradha Todi
2025-02-23  8:54       ` Manivannan Sadhasivam
2025-03-03 18:02       ` Fan Ni [this message]
2025-03-03 19:42         ` Krzysztof Wilczyński
2025-03-03 21:03           ` Fan Ni
2025-03-04 15:32             ` Manivannan Sadhasivam
2025-03-04 17:10             ` Shradha Todi
2025-03-05  4:26               ` Fan Ni
2025-03-07  9:47                 ` Shradha Todi
2025-02-24 17:08   ` [PATCH v7 0/5] Add support for debugfs based RAS DES feature in PCIe DW Niklas Cassel
2025-02-25  8:28     ` Manivannan Sadhasivam
2025-02-25 14:33       ` Krzysztof Wilczyński
2025-02-25 14:35       ` Niklas Cassel
2025-02-25 17:15         ` Manivannan Sadhasivam
2025-02-25 14:30   ` Krzysztof Wilczyński
2025-03-03 19:51     ` Krzysztof Wilczyński
     [not found]   ` <CGME20250228114813epcas5p32127b99d3a0adf6900a104468b48768d@epcas5p3.samsung.com>
2025-02-28 11:43     ` Hrishikesh Deleep
2025-03-03 20:00       ` Krzysztof Wilczyński

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