From: Arnaldo Carvalho de Melo <acme@kernel.org>
To: Thomas Richter <tmricht@linux.ibm.com>
Cc: linux-kernel@vger.kernel.org, linux-perf-users@vger.kernel.org,
svens@linux.ibm.com, gor@linux.ibm.com, sumanthk@linux.ibm.com,
hca@linux.ibm.com, Arnaldo Carvalho de Melo <acme@redhat.com>
Subject: Re: [PATCH] perf list: Remove UTF-8 characters from json file
Date: Thu, 23 Mar 2023 10:07:25 -0300 [thread overview]
Message-ID: <ZBxPDagGB11SS8/D@kernel.org> (raw)
In-Reply-To: <20230323122532.2305847-1-tmricht@linux.ibm.com>
Em Thu, Mar 23, 2023 at 01:25:32PM +0100, Thomas Richter escreveu:
> commit 7f76b3113068 ("perf list: Add IBM z16 event description for s390")
> contains the verbal description for z16 extended counter set.
> However some entries of the public description contain
> UTF-8 characters which brakes the build on some distros.
>
> Fix this and remove the UTF-8 characters.
Thanks, tested and applied. Now its some power9 file failing...
- Arnaldo
> Fixes: 7f76b3113068 ("perf list: Add IBM z16 event description for s390")
> Reported-by: Arnaldo Carvalho de Melo <acme@redhat.com>
> Signed-off-by: Thomas Richter <tmricht@linux.ibm.com>
> ---
> tools/perf/pmu-events/arch/s390/cf_z16/extended.json | 10 +++++-----
> 1 file changed, 5 insertions(+), 5 deletions(-)
>
> diff --git a/tools/perf/pmu-events/arch/s390/cf_z16/extended.json b/tools/perf/pmu-events/arch/s390/cf_z16/extended.json
> index c306190fc06f..c2b10ec1c6e0 100644
> --- a/tools/perf/pmu-events/arch/s390/cf_z16/extended.json
> +++ b/tools/perf/pmu-events/arch/s390/cf_z16/extended.json
> @@ -95,28 +95,28 @@
> "EventCode": "145",
> "EventName": "DCW_REQ",
> "BriefDescription": "Directory Write Level 1 Data Cache from Cache",
> - "PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from the requestor’s Level-2 cache."
> + "PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from the requestors Level-2 cache."
> },
> {
> "Unit": "CPU-M-CF",
> "EventCode": "146",
> "EventName": "DCW_REQ_IV",
> "BriefDescription": "Directory Write Level 1 Data Cache from Cache with Intervention",
> - "PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from the requestor’s Level-2 cache with intervention."
> + "PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from the requestors Level-2 cache with intervention."
> },
> {
> "Unit": "CPU-M-CF",
> "EventCode": "147",
> "EventName": "DCW_REQ_CHIP_HIT",
> "BriefDescription": "Directory Write Level 1 Data Cache from Cache with Chip HP Hit",
> - "PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from the requestor’s Level-2 cache after using chip level horizontal persistence, Chip-HP hit."
> + "PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from the requestors Level-2 cache after using chip level horizontal persistence, Chip-HP hit."
> },
> {
> "Unit": "CPU-M-CF",
> "EventCode": "148",
> "EventName": "DCW_REQ_DRAWER_HIT",
> "BriefDescription": "Directory Write Level 1 Data Cache from Cache with Drawer HP Hit",
> - "PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from the requestor’s Level-2 cache after using drawer level horizontal persistence, Drawer-HP hit."
> + "PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from the requestors Level-2 cache after using drawer level horizontal persistence, Drawer-HP hit."
> },
> {
> "Unit": "CPU-M-CF",
> @@ -284,7 +284,7 @@
> "EventCode": "172",
> "EventName": "ICW_REQ_DRAWER_HIT",
> "BriefDescription": "Directory Write Level 1 Instruction Cache from Cache with Drawer HP Hit",
> - "PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from the requestor’s Level-2 cache using drawer level horizontal persistence, Drawer-HP hit."
> + "PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from the requestors Level-2 cache using drawer level horizontal persistence, Drawer-HP hit."
> },
> {
> "Unit": "CPU-M-CF",
> --
> 2.17.1
>
--
- Arnaldo
prev parent reply other threads:[~2023-03-23 13:08 UTC|newest]
Thread overview: 2+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-03-23 12:25 [PATCH] perf list: Remove UTF-8 characters from json file Thomas Richter
2023-03-23 13:07 ` Arnaldo Carvalho de Melo [this message]
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=ZBxPDagGB11SS8/D@kernel.org \
--to=acme@kernel.org \
--cc=acme@redhat.com \
--cc=gor@linux.ibm.com \
--cc=hca@linux.ibm.com \
--cc=linux-kernel@vger.kernel.org \
--cc=linux-perf-users@vger.kernel.org \
--cc=sumanthk@linux.ibm.com \
--cc=svens@linux.ibm.com \
--cc=tmricht@linux.ibm.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).