From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id E28AEC761A6 for ; Fri, 7 Apr 2023 00:56:57 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S238742AbjDGA44 (ORCPT ); Thu, 6 Apr 2023 20:56:56 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:51074 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S238744AbjDGA4y (ORCPT ); Thu, 6 Apr 2023 20:56:54 -0400 Received: from dfw.source.kernel.org (dfw.source.kernel.org [IPv6:2604:1380:4641:c500::1]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 2D32A977B; Thu, 6 Apr 2023 17:56:52 -0700 (PDT) Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by dfw.source.kernel.org (Postfix) with ESMTPS id AE63464DD7; Fri, 7 Apr 2023 00:56:51 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id BAD87C433EF; Fri, 7 Apr 2023 00:56:50 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1680829011; bh=dEpPj7Lxr+bYb5SRJPJTU3Tjh9vBIlTeY+zKfTX5zPI=; h=Date:From:To:Cc:Subject:References:In-Reply-To:From; b=CPnwwNg+cN2sk7oRPUU6NNN2BfD6VXipHOFLBaj0vG/yoxFkf624JnEkgo6Gd4TQX qZcfJswj9ImLuyotpNYnnbO3kc0/K6DWHIW2DDnxQo9yey13T83zXr+Ixj7MH7xlc/ 1RXorh6KhGsbL5XhxSsJA8V65aWgAy8kaSZLP1X1+NJh+UDzUyVvRlWBLdfjvWoUEE JJ/LVEXFMrEyEFXBN1OCqyEuKaGVLz0rT976dmj+YbjyNkdhD00s3/FiHuBszutshx 3dW5vvSOxieP/UR2+BvNPDNIoap7yIFq3AwyDCKNEzX4n5UG2FAw6DQALehhLmJiur LypQLrjYP3rnw== Received: by quaco.ghostprotocols.net (Postfix, from userid 1000) id D81F24052D; Thu, 6 Apr 2023 21:56:47 -0300 (-03) Date: Thu, 6 Apr 2023 21:56:47 -0300 From: Arnaldo Carvalho de Melo To: Ian Rogers Cc: Peter Zijlstra , Ingo Molnar , Mark Rutland , Alexander Shishkin , Jiri Olsa , Namhyung Kim , Adrian Hunter , Kan Liang , Zhengjun Xing , linux-kernel@vger.kernel.org, linux-perf-users@vger.kernel.org Subject: Re: [PATCH v2 1/5] perf vendor events intel: Update free running alderlake events Message-ID: References: <20230407001322.2776268-1-irogers@google.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20230407001322.2776268-1-irogers@google.com> X-Url: http://acmel.wordpress.com Precedence: bulk List-ID: X-Mailing-List: linux-perf-users@vger.kernel.org Em Thu, Apr 06, 2023 at 05:13:18PM -0700, Ian Rogers escreveu: > Fix the PMU name, event code and umask. > > These updates were generated by: > https://github.com/intel/perfmon/blob/main/scripts/create_perf_json.py > with this PR: > https://github.com/intel/perfmon/pull/66 Thanks, applied. - Arnaldo > Signed-off-by: Ian Rogers > --- > .../arch/x86/alderlake/uncore-memory.json | 16 ++++++++++++---- > .../arch/x86/alderlaken/uncore-memory.json | 16 ++++++++++++---- > 2 files changed, 24 insertions(+), 8 deletions(-) > > diff --git a/tools/perf/pmu-events/arch/x86/alderlake/uncore-memory.json b/tools/perf/pmu-events/arch/x86/alderlake/uncore-memory.json > index 2ccd9cf96957..163d7e7755c4 100644 > --- a/tools/perf/pmu-events/arch/x86/alderlake/uncore-memory.json > +++ b/tools/perf/pmu-events/arch/x86/alderlake/uncore-memory.json > @@ -1,29 +1,37 @@ > [ > { > "BriefDescription": "Counts every 64B read request entering the Memory Controller 0 to DRAM (sum of all channels).", > + "EventCode": "0xff", > "EventName": "UNC_MC0_RDCAS_COUNT_FREERUN", > "PerPkg": "1", > "PublicDescription": "Counts every 64B read request entering the Memory Controller 0 to DRAM (sum of all channels).", > - "Unit": "iMC" > + "UMask": "0x20", > + "Unit": "imc_free_running_0" > }, > { > "BriefDescription": "Counts every 64B write request entering the Memory Controller 0 to DRAM (sum of all channels). Each write request counts as a new request incrementing this counter. However, same cache line write requests (both full and partial) are combined to a single 64 byte data transfer to DRAM.", > + "EventCode": "0xff", > "EventName": "UNC_MC0_WRCAS_COUNT_FREERUN", > "PerPkg": "1", > - "Unit": "iMC" > + "UMask": "0x30", > + "Unit": "imc_free_running_0" > }, > { > "BriefDescription": "Counts every 64B read request entering the Memory Controller 1 to DRAM (sum of all channels).", > + "EventCode": "0xff", > "EventName": "UNC_MC1_RDCAS_COUNT_FREERUN", > "PerPkg": "1", > "PublicDescription": "Counts every 64B read entering the Memory Controller 1 to DRAM (sum of all channels).", > - "Unit": "iMC" > + "UMask": "0x20", > + "Unit": "imc_free_running_1" > }, > { > "BriefDescription": "Counts every 64B write request entering the Memory Controller 1 to DRAM (sum of all channels). Each write request counts as a new request incrementing this counter. However, same cache line write requests (both full and partial) are combined to a single 64 byte data transfer to DRAM.", > + "EventCode": "0xff", > "EventName": "UNC_MC1_WRCAS_COUNT_FREERUN", > "PerPkg": "1", > - "Unit": "iMC" > + "UMask": "0x30", > + "Unit": "imc_free_running_1" > }, > { > "BriefDescription": "ACT command for a read request sent to DRAM", > diff --git a/tools/perf/pmu-events/arch/x86/alderlaken/uncore-memory.json b/tools/perf/pmu-events/arch/x86/alderlaken/uncore-memory.json > index 2ccd9cf96957..163d7e7755c4 100644 > --- a/tools/perf/pmu-events/arch/x86/alderlaken/uncore-memory.json > +++ b/tools/perf/pmu-events/arch/x86/alderlaken/uncore-memory.json > @@ -1,29 +1,37 @@ > [ > { > "BriefDescription": "Counts every 64B read request entering the Memory Controller 0 to DRAM (sum of all channels).", > + "EventCode": "0xff", > "EventName": "UNC_MC0_RDCAS_COUNT_FREERUN", > "PerPkg": "1", > "PublicDescription": "Counts every 64B read request entering the Memory Controller 0 to DRAM (sum of all channels).", > - "Unit": "iMC" > + "UMask": "0x20", > + "Unit": "imc_free_running_0" > }, > { > "BriefDescription": "Counts every 64B write request entering the Memory Controller 0 to DRAM (sum of all channels). Each write request counts as a new request incrementing this counter. However, same cache line write requests (both full and partial) are combined to a single 64 byte data transfer to DRAM.", > + "EventCode": "0xff", > "EventName": "UNC_MC0_WRCAS_COUNT_FREERUN", > "PerPkg": "1", > - "Unit": "iMC" > + "UMask": "0x30", > + "Unit": "imc_free_running_0" > }, > { > "BriefDescription": "Counts every 64B read request entering the Memory Controller 1 to DRAM (sum of all channels).", > + "EventCode": "0xff", > "EventName": "UNC_MC1_RDCAS_COUNT_FREERUN", > "PerPkg": "1", > "PublicDescription": "Counts every 64B read entering the Memory Controller 1 to DRAM (sum of all channels).", > - "Unit": "iMC" > + "UMask": "0x20", > + "Unit": "imc_free_running_1" > }, > { > "BriefDescription": "Counts every 64B write request entering the Memory Controller 1 to DRAM (sum of all channels). Each write request counts as a new request incrementing this counter. However, same cache line write requests (both full and partial) are combined to a single 64 byte data transfer to DRAM.", > + "EventCode": "0xff", > "EventName": "UNC_MC1_WRCAS_COUNT_FREERUN", > "PerPkg": "1", > - "Unit": "iMC" > + "UMask": "0x30", > + "Unit": "imc_free_running_1" > }, > { > "BriefDescription": "ACT command for a read request sent to DRAM", > -- > 2.40.0.577.gac1e443424-goog > -- - Arnaldo