[PATCH v1 0/3] Updates to sapphirerapids, alderlake and icelakex events

[PATCH v1 0/3] Updates to sapphirerapids, alderlake and icelakex events

[Ian Rogers]

Changes largely stemming from:
https://github.com/intel/perfmon/pull/68

Changes generated by:
https://github.com/intel/perfmon/blob/main/scripts/create_perf_json.py

Ian Rogers (3):
  perf vendor events: Update alderlake to v1.20
  perf vendor events: Update icelakex to v1.20
  perf vendor events: Update sapphirerapids to v1.12

 .../pmu-events/arch/x86/alderlake/other.json  |     3 +-
 .../arch/x86/alderlake/pipeline.json          |     4 +-
 .../arch/x86/icelakex/uncore-other.json       |     2 +-
 tools/perf/pmu-events/arch/x86/mapfile.csv    |     8 +-
 .../arch/x86/sapphirerapids/other.json        |     3 +-
 .../arch/x86/sapphirerapids/pipeline.json     |     4 +-
 .../x86/sapphirerapids/uncore-memory.json     |   794 +-
 .../arch/x86/sapphirerapids/uncore-other.json | 18656 +++++++++++++---
 .../arch/x86/sapphirerapids/uncore-power.json |   107 +
 9 files changed, 16977 insertions(+), 2604 deletions(-)

-- 
2.40.0.577.gac1e443424-goog

[PATCH v1 1/3] perf vendor events: Update alderlake to v1.20

[Ian Rogers]

Update from v1.19 to v1.20 affecting the performance/goldencove
events. Adds cmask=1 for ARITH.IDIV_ACTIVE, and updates event
descriptions.

Signed-off-by: Ian Rogers <irogers@google.com>
---
 tools/perf/pmu-events/arch/x86/alderlake/other.json    | 3 ++-
 tools/perf/pmu-events/arch/x86/alderlake/pipeline.json | 4 +++-
 tools/perf/pmu-events/arch/x86/mapfile.csv             | 4 ++--
 3 files changed, 7 insertions(+), 4 deletions(-)

diff --git a/tools/perf/pmu-events/arch/x86/alderlake/other.json b/tools/perf/pmu-events/arch/x86/alderlake/other.json
index 329c611d7cf7..1db73e020215 100644
--- a/tools/perf/pmu-events/arch/x86/alderlake/other.json
+++ b/tools/perf/pmu-events/arch/x86/alderlake/other.json
@@ -162,10 +162,11 @@
         "Unit": "cpu_core"
     },
     {
-        "BriefDescription": "XQ.FULL_CYCLES",
+        "BriefDescription": "Cycles the uncore cannot take further requests",
         "CounterMask": "1",
         "EventCode": "0x2d",
         "EventName": "XQ.FULL_CYCLES",
+        "PublicDescription": "number of cycles when the thread is active and the uncore cannot take any further requests (for example prefetches, loads or stores initiated by the Core that miss the L2 cache).",
         "SampleAfterValue": "1000003",
         "UMask": "0x1",
         "Unit": "cpu_core"
diff --git a/tools/perf/pmu-events/arch/x86/alderlake/pipeline.json b/tools/perf/pmu-events/arch/x86/alderlake/pipeline.json
index f848530fbf07..cb5b8611064b 100644
--- a/tools/perf/pmu-events/arch/x86/alderlake/pipeline.json
+++ b/tools/perf/pmu-events/arch/x86/alderlake/pipeline.json
@@ -31,6 +31,7 @@
     },
     {
         "BriefDescription": "This event counts the cycles the integer divider is busy.",
+        "CounterMask": "1",
         "EventCode": "0xb0",
         "EventName": "ARITH.IDIV_ACTIVE",
         "SampleAfterValue": "1000003",
@@ -1079,9 +1080,10 @@
         "Unit": "cpu_core"
     },
     {
-        "BriefDescription": "MISC2_RETIRED.LFENCE",
+        "BriefDescription": "LFENCE instructions retired",
         "EventCode": "0xe0",
         "EventName": "MISC2_RETIRED.LFENCE",
+        "PublicDescription": "number of LFENCE retired instructions",
         "SampleAfterValue": "400009",
         "UMask": "0x20",
         "Unit": "cpu_core"
diff --git a/tools/perf/pmu-events/arch/x86/mapfile.csv b/tools/perf/pmu-events/arch/x86/mapfile.csv
index 97b3ffc284a6..9e7545d09b23 100644
--- a/tools/perf/pmu-events/arch/x86/mapfile.csv
+++ b/tools/perf/pmu-events/arch/x86/mapfile.csv
@@ -1,6 +1,6 @@
 Family-model,Version,Filename,EventType
-GenuineIntel-6-(97|9A|B7|BA|BF),v1.19,alderlake,core
-GenuineIntel-6-BE,v1.19,alderlaken,core
+GenuineIntel-6-(97|9A|B7|BA|BF),v1.20,alderlake,core
+GenuineIntel-6-BE,v1.20,alderlaken,core
 GenuineIntel-6-(1C|26|27|35|36),v4,bonnell,core
 GenuineIntel-6-(3D|47),v27,broadwell,core
 GenuineIntel-6-56,v9,broadwellde,core
-- 
2.40.0.577.gac1e443424-goog

[PATCH v1 2/3] perf vendor events: Update icelakex to v1.20

[Ian Rogers]

Update from v1.19 to v1.20 affecting the uncore
UNC_CHA_CORE_SNP.REMOTE_GTONE event's umask.

Signed-off-by: Ian Rogers <irogers@google.com>
---
 tools/perf/pmu-events/arch/x86/icelakex/uncore-other.json | 2 +-
 tools/perf/pmu-events/arch/x86/mapfile.csv                | 2 +-
 2 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/tools/perf/pmu-events/arch/x86/icelakex/uncore-other.json b/tools/perf/pmu-events/arch/x86/icelakex/uncore-other.json
index 8210e286eec1..134b54da0869 100644
--- a/tools/perf/pmu-events/arch/x86/icelakex/uncore-other.json
+++ b/tools/perf/pmu-events/arch/x86/icelakex/uncore-other.json
@@ -981,7 +981,7 @@
         "EventName": "UNC_CHA_CORE_SNP.REMOTE_GTONE",
         "PerPkg": "1",
         "PublicDescription": "Core Cross Snoops Issued : Multiple Snoop Targets from Remote : Counts the number of transactions that trigger a configurable number of cross snoops.  Cores are snooped if the transaction looks up the cache and determines that it is necessary based on the operation type and what CoreValid bits are set.  For example, if 2 CV bits are set on a data read, the cores must have the data in S state so it is not necessary to snoop them.  However, if only 1 CV bit is set the core my have modified the data.  If the transaction was an RFO, it would need to invalidate the lines.  This event can be filtered based on who triggered the initial snoop(s).",
-        "UMask": "0x22",
+        "UMask": "0x12",
         "Unit": "CHA"
     },
     {
diff --git a/tools/perf/pmu-events/arch/x86/mapfile.csv b/tools/perf/pmu-events/arch/x86/mapfile.csv
index 9e7545d09b23..58faf18474b5 100644
--- a/tools/perf/pmu-events/arch/x86/mapfile.csv
+++ b/tools/perf/pmu-events/arch/x86/mapfile.csv
@@ -13,7 +13,7 @@ GenuineIntel-6-A[DE],v1.01,graniterapids,core
 GenuineIntel-6-(3C|45|46),v33,haswell,core
 GenuineIntel-6-3F,v27,haswellx,core
 GenuineIntel-6-(7D|7E|A7),v1.17,icelake,core
-GenuineIntel-6-6[AC],v1.19,icelakex,core
+GenuineIntel-6-6[AC],v1.20,icelakex,core
 GenuineIntel-6-3A,v24,ivybridge,core
 GenuineIntel-6-3E,v23,ivytown,core
 GenuineIntel-6-2D,v23,jaketown,core
-- 
2.40.0.577.gac1e443424-goog

Re: [PATCH v1 0/3] Updates to sapphirerapids, alderlake and icelakex events

[Arnaldo Carvalho de Melo]

Em Tue, Apr 11, 2023 at 04:44:37PM -0700, Ian Rogers escreveu:
> Changes largely stemming from:
> https://github.com/intel/perfmon/pull/68
> 
> Changes generated by:
> https://github.com/intel/perfmon/blob/main/scripts/create_perf_json.py

Thanks, applied.

- Arnaldo

 
> Ian Rogers (3):
>   perf vendor events: Update alderlake to v1.20
>   perf vendor events: Update icelakex to v1.20
>   perf vendor events: Update sapphirerapids to v1.12
> 
>  .../pmu-events/arch/x86/alderlake/other.json  |     3 +-
>  .../arch/x86/alderlake/pipeline.json          |     4 +-
>  .../arch/x86/icelakex/uncore-other.json       |     2 +-
>  tools/perf/pmu-events/arch/x86/mapfile.csv    |     8 +-
>  .../arch/x86/sapphirerapids/other.json        |     3 +-
>  .../arch/x86/sapphirerapids/pipeline.json     |     4 +-
>  .../x86/sapphirerapids/uncore-memory.json     |   794 +-
>  .../arch/x86/sapphirerapids/uncore-other.json | 18656 +++++++++++++---
>  .../arch/x86/sapphirerapids/uncore-power.json |   107 +
>  9 files changed, 16977 insertions(+), 2604 deletions(-)
> 
> -- 
> 2.40.0.577.gac1e443424-goog
> 

-- 

- Arnaldo