* [PATCH v3 02/21] perf vendor events intel: Add grandridge
2023-04-13 13:29 [PATCH v3 00/21] Update uncore topics, 1x event updates, 2x new archs Ian Rogers
@ 2023-04-13 13:29 ` Ian Rogers
2023-04-13 13:29 ` [PATCH v3 03/21] perf vendor events intel: Add sierraforest Ian Rogers
` (11 subsequent siblings)
12 siblings, 0 replies; 18+ messages in thread
From: Ian Rogers @ 2023-04-13 13:29 UTC (permalink / raw)
To: Peter Zijlstra, Ingo Molnar, Arnaldo Carvalho de Melo,
Mark Rutland, Alexander Shishkin, Jiri Olsa, Namhyung Kim,
Zhengjun Xing, Kan Liang, linux-perf-users, linux-kernel,
Edward Baker, Perry Taylor, Caleb Biggers
Cc: Stephane Eranian, Ian Rogers
Add v1.00 from:
https://github.com/intel/perfmon/pull/69
Signed-off-by: Ian Rogers <irogers@google.com>
---
.../pmu-events/arch/x86/grandridge/cache.json | 155 ++++++++++++++++++
.../arch/x86/grandridge/frontend.json | 16 ++
.../arch/x86/grandridge/memory.json | 20 +++
.../pmu-events/arch/x86/grandridge/other.json | 20 +++
.../arch/x86/grandridge/pipeline.json | 96 +++++++++++
.../arch/x86/grandridge/virtual-memory.json | 24 +++
tools/perf/pmu-events/arch/x86/mapfile.csv | 1 +
7 files changed, 332 insertions(+)
create mode 100644 tools/perf/pmu-events/arch/x86/grandridge/cache.json
create mode 100644 tools/perf/pmu-events/arch/x86/grandridge/frontend.json
create mode 100644 tools/perf/pmu-events/arch/x86/grandridge/memory.json
create mode 100644 tools/perf/pmu-events/arch/x86/grandridge/other.json
create mode 100644 tools/perf/pmu-events/arch/x86/grandridge/pipeline.json
create mode 100644 tools/perf/pmu-events/arch/x86/grandridge/virtual-memory.json
diff --git a/tools/perf/pmu-events/arch/x86/grandridge/cache.json b/tools/perf/pmu-events/arch/x86/grandridge/cache.json
new file mode 100644
index 000000000000..7f0dc65a55d2
--- /dev/null
+++ b/tools/perf/pmu-events/arch/x86/grandridge/cache.json
@@ -0,0 +1,155 @@
+[
+ {
+ "BriefDescription": "Counts the number of cacheable memory requests that miss in the LLC. Counts on a per core basis.",
+ "EventCode": "0x2e",
+ "EventName": "LONGEST_LAT_CACHE.MISS",
+ "PublicDescription": "Counts the number of cacheable memory requests that miss in the Last Level Cache (LLC). Requests include demand loads, reads for ownership (RFO), instruction fetches and L1 HW prefetches. If the platform has an L3 cache, the LLC is the L3 cache, otherwise it is the L2 cache. Counts on a per core basis.",
+ "SampleAfterValue": "200003",
+ "UMask": "0x41"
+ },
+ {
+ "BriefDescription": "Counts the number of cacheable memory requests that access the LLC. Counts on a per core basis.",
+ "EventCode": "0x2e",
+ "EventName": "LONGEST_LAT_CACHE.REFERENCE",
+ "PublicDescription": "Counts the number of cacheable memory requests that access the Last Level Cache (LLC). Requests include demand loads, reads for ownership (RFO), instruction fetches and L1 HW prefetches. If the platform has an L3 cache, the LLC is the L3 cache, otherwise it is the L2 cache. Counts on a per core basis.",
+ "SampleAfterValue": "200003",
+ "UMask": "0x4f"
+ },
+ {
+ "BriefDescription": "Counts the number of load ops retired.",
+ "Data_LA": "1",
+ "EventCode": "0xd0",
+ "EventName": "MEM_UOPS_RETIRED.ALL_LOADS",
+ "PEBS": "1",
+ "SampleAfterValue": "200003",
+ "UMask": "0x81"
+ },
+ {
+ "BriefDescription": "Counts the number of store ops retired.",
+ "Data_LA": "1",
+ "EventCode": "0xd0",
+ "EventName": "MEM_UOPS_RETIRED.ALL_STORES",
+ "PEBS": "1",
+ "SampleAfterValue": "200003",
+ "UMask": "0x82"
+ },
+ {
+ "BriefDescription": "Counts the number of tagged load uops retired that exceed the latency threshold defined in MEC_CR_PEBS_LD_LAT_THRESHOLD - Only counts with PEBS enabled.",
+ "Data_LA": "1",
+ "EventCode": "0xd0",
+ "EventName": "MEM_UOPS_RETIRED.LOAD_LATENCY_GT_1024",
+ "MSRIndex": "0x3F6",
+ "MSRValue": "0x400",
+ "PEBS": "2",
+ "SampleAfterValue": "1000003",
+ "UMask": "0x5"
+ },
+ {
+ "BriefDescription": "Counts the number of tagged load uops retired that exceed the latency threshold defined in MEC_CR_PEBS_LD_LAT_THRESHOLD - Only counts with PEBS enabled.",
+ "Data_LA": "1",
+ "EventCode": "0xd0",
+ "EventName": "MEM_UOPS_RETIRED.LOAD_LATENCY_GT_128",
+ "MSRIndex": "0x3F6",
+ "MSRValue": "0x80",
+ "PEBS": "2",
+ "SampleAfterValue": "1000003",
+ "UMask": "0x5"
+ },
+ {
+ "BriefDescription": "Counts the number of tagged load uops retired that exceed the latency threshold defined in MEC_CR_PEBS_LD_LAT_THRESHOLD - Only counts with PEBS enabled.",
+ "Data_LA": "1",
+ "EventCode": "0xd0",
+ "EventName": "MEM_UOPS_RETIRED.LOAD_LATENCY_GT_16",
+ "MSRIndex": "0x3F6",
+ "MSRValue": "0x10",
+ "PEBS": "2",
+ "SampleAfterValue": "1000003",
+ "UMask": "0x5"
+ },
+ {
+ "BriefDescription": "Counts the number of tagged load uops retired that exceed the latency threshold defined in MEC_CR_PEBS_LD_LAT_THRESHOLD - Only counts with PEBS enabled.",
+ "Data_LA": "1",
+ "EventCode": "0xd0",
+ "EventName": "MEM_UOPS_RETIRED.LOAD_LATENCY_GT_2048",
+ "MSRIndex": "0x3F6",
+ "MSRValue": "0x800",
+ "PEBS": "2",
+ "SampleAfterValue": "1000003",
+ "UMask": "0x5"
+ },
+ {
+ "BriefDescription": "Counts the number of tagged load uops retired that exceed the latency threshold defined in MEC_CR_PEBS_LD_LAT_THRESHOLD - Only counts with PEBS enabled.",
+ "Data_LA": "1",
+ "EventCode": "0xd0",
+ "EventName": "MEM_UOPS_RETIRED.LOAD_LATENCY_GT_256",
+ "MSRIndex": "0x3F6",
+ "MSRValue": "0x100",
+ "PEBS": "2",
+ "SampleAfterValue": "1000003",
+ "UMask": "0x5"
+ },
+ {
+ "BriefDescription": "Counts the number of tagged load uops retired that exceed the latency threshold defined in MEC_CR_PEBS_LD_LAT_THRESHOLD - Only counts with PEBS enabled.",
+ "Data_LA": "1",
+ "EventCode": "0xd0",
+ "EventName": "MEM_UOPS_RETIRED.LOAD_LATENCY_GT_32",
+ "MSRIndex": "0x3F6",
+ "MSRValue": "0x20",
+ "PEBS": "2",
+ "SampleAfterValue": "1000003",
+ "UMask": "0x5"
+ },
+ {
+ "BriefDescription": "Counts the number of tagged load uops retired that exceed the latency threshold defined in MEC_CR_PEBS_LD_LAT_THRESHOLD - Only counts with PEBS enabled.",
+ "Data_LA": "1",
+ "EventCode": "0xd0",
+ "EventName": "MEM_UOPS_RETIRED.LOAD_LATENCY_GT_4",
+ "MSRIndex": "0x3F6",
+ "MSRValue": "0x4",
+ "PEBS": "2",
+ "SampleAfterValue": "1000003",
+ "UMask": "0x5"
+ },
+ {
+ "BriefDescription": "Counts the number of tagged load uops retired that exceed the latency threshold defined in MEC_CR_PEBS_LD_LAT_THRESHOLD - Only counts with PEBS enabled.",
+ "Data_LA": "1",
+ "EventCode": "0xd0",
+ "EventName": "MEM_UOPS_RETIRED.LOAD_LATENCY_GT_512",
+ "MSRIndex": "0x3F6",
+ "MSRValue": "0x200",
+ "PEBS": "2",
+ "SampleAfterValue": "1000003",
+ "UMask": "0x5"
+ },
+ {
+ "BriefDescription": "Counts the number of tagged load uops retired that exceed the latency threshold defined in MEC_CR_PEBS_LD_LAT_THRESHOLD - Only counts with PEBS enabled.",
+ "Data_LA": "1",
+ "EventCode": "0xd0",
+ "EventName": "MEM_UOPS_RETIRED.LOAD_LATENCY_GT_64",
+ "MSRIndex": "0x3F6",
+ "MSRValue": "0x40",
+ "PEBS": "2",
+ "SampleAfterValue": "1000003",
+ "UMask": "0x5"
+ },
+ {
+ "BriefDescription": "Counts the number of tagged load uops retired that exceed the latency threshold defined in MEC_CR_PEBS_LD_LAT_THRESHOLD - Only counts with PEBS enabled.",
+ "Data_LA": "1",
+ "EventCode": "0xd0",
+ "EventName": "MEM_UOPS_RETIRED.LOAD_LATENCY_GT_8",
+ "MSRIndex": "0x3F6",
+ "MSRValue": "0x8",
+ "PEBS": "2",
+ "SampleAfterValue": "1000003",
+ "UMask": "0x5"
+ },
+ {
+ "BriefDescription": "Counts the number of stores uops retired same as MEM_UOPS_RETIRED.ALL_STORES",
+ "Data_LA": "1",
+ "EventCode": "0xd0",
+ "EventName": "MEM_UOPS_RETIRED.STORE_LATENCY",
+ "PEBS": "2",
+ "SampleAfterValue": "1000003",
+ "UMask": "0x6"
+ }
+]
diff --git a/tools/perf/pmu-events/arch/x86/grandridge/frontend.json b/tools/perf/pmu-events/arch/x86/grandridge/frontend.json
new file mode 100644
index 000000000000..be8f1c7e195c
--- /dev/null
+++ b/tools/perf/pmu-events/arch/x86/grandridge/frontend.json
@@ -0,0 +1,16 @@
+[
+ {
+ "BriefDescription": "Counts every time the code stream enters into a new cache line by walking sequential from the previous line or being redirected by a jump.",
+ "EventCode": "0x80",
+ "EventName": "ICACHE.ACCESSES",
+ "SampleAfterValue": "200003",
+ "UMask": "0x3"
+ },
+ {
+ "BriefDescription": "Counts every time the code stream enters into a new cache line by walking sequential from the previous line or being redirected by a jump and the instruction cache registers bytes are not present. -",
+ "EventCode": "0x80",
+ "EventName": "ICACHE.MISSES",
+ "SampleAfterValue": "200003",
+ "UMask": "0x2"
+ }
+]
diff --git a/tools/perf/pmu-events/arch/x86/grandridge/memory.json b/tools/perf/pmu-events/arch/x86/grandridge/memory.json
new file mode 100644
index 000000000000..79d8af45100c
--- /dev/null
+++ b/tools/perf/pmu-events/arch/x86/grandridge/memory.json
@@ -0,0 +1,20 @@
+[
+ {
+ "BriefDescription": "Counts demand data reads that were not supplied by the L3 cache.",
+ "EventCode": "0xB7",
+ "EventName": "OCR.DEMAND_DATA_RD.L3_MISS",
+ "MSRIndex": "0x1a6,0x1a7",
+ "MSRValue": "0x3FBFC00001",
+ "SampleAfterValue": "100003",
+ "UMask": "0x1"
+ },
+ {
+ "BriefDescription": "Counts demand reads for ownership (RFO) and software prefetches for exclusive ownership (PREFETCHW) that were not supplied by the L3 cache.",
+ "EventCode": "0xB7",
+ "EventName": "OCR.DEMAND_RFO.L3_MISS",
+ "MSRIndex": "0x1a6,0x1a7",
+ "MSRValue": "0x3FBFC00002",
+ "SampleAfterValue": "100003",
+ "UMask": "0x1"
+ }
+]
diff --git a/tools/perf/pmu-events/arch/x86/grandridge/other.json b/tools/perf/pmu-events/arch/x86/grandridge/other.json
new file mode 100644
index 000000000000..2414f6ff53b0
--- /dev/null
+++ b/tools/perf/pmu-events/arch/x86/grandridge/other.json
@@ -0,0 +1,20 @@
+[
+ {
+ "BriefDescription": "Counts demand data reads that have any type of response.",
+ "EventCode": "0xB7",
+ "EventName": "OCR.DEMAND_DATA_RD.ANY_RESPONSE",
+ "MSRIndex": "0x1a6,0x1a7",
+ "MSRValue": "0x10001",
+ "SampleAfterValue": "100003",
+ "UMask": "0x1"
+ },
+ {
+ "BriefDescription": "Counts demand reads for ownership (RFO) and software prefetches for exclusive ownership (PREFETCHW) that have any type of response.",
+ "EventCode": "0xB7",
+ "EventName": "OCR.DEMAND_RFO.ANY_RESPONSE",
+ "MSRIndex": "0x1a6,0x1a7",
+ "MSRValue": "0x10002",
+ "SampleAfterValue": "100003",
+ "UMask": "0x1"
+ }
+]
diff --git a/tools/perf/pmu-events/arch/x86/grandridge/pipeline.json b/tools/perf/pmu-events/arch/x86/grandridge/pipeline.json
new file mode 100644
index 000000000000..41212957ef21
--- /dev/null
+++ b/tools/perf/pmu-events/arch/x86/grandridge/pipeline.json
@@ -0,0 +1,96 @@
+[
+ {
+ "BriefDescription": "Counts the total number of branch instructions retired for all branch types.",
+ "EventCode": "0xc4",
+ "EventName": "BR_INST_RETIRED.ALL_BRANCHES",
+ "PEBS": "1",
+ "PublicDescription": "Counts the total number of instructions in which the instruction pointer (IP) of the processor is resteered due to a branch instruction and the branch instruction successfully retires. All branch type instructions are accounted for.",
+ "SampleAfterValue": "200003"
+ },
+ {
+ "BriefDescription": "Counts the total number of mispredicted branch instructions retired for all branch types.",
+ "EventCode": "0xc5",
+ "EventName": "BR_MISP_RETIRED.ALL_BRANCHES",
+ "PEBS": "1",
+ "PublicDescription": "Counts the total number of mispredicted branch instructions retired. All branch type instructions are accounted for. Prediction of the branch target address enables the processor to begin executing instructions before the non-speculative execution path is known. The branch prediction unit (BPU) predicts the target address based on the instruction pointer (IP) of the branch and on the execution path through which execution reached this IP. A branch misprediction occurs when the prediction is wrong, and results in discarding all instructions executed in the speculative path and re-fetching from the correct path.",
+ "SampleAfterValue": "200003"
+ },
+ {
+ "BriefDescription": "Fixed Counter: Counts the number of unhalted core clock cycles",
+ "EventName": "CPU_CLK_UNHALTED.CORE",
+ "SampleAfterValue": "2000003",
+ "UMask": "0x2"
+ },
+ {
+ "BriefDescription": "Counts the number of unhalted core clock cycles [This event is alias to CPU_CLK_UNHALTED.THREAD_P]",
+ "EventCode": "0x3c",
+ "EventName": "CPU_CLK_UNHALTED.CORE_P",
+ "SampleAfterValue": "2000003"
+ },
+ {
+ "BriefDescription": "Fixed Counter: Counts the number of unhalted reference clock cycles",
+ "EventName": "CPU_CLK_UNHALTED.REF_TSC",
+ "SampleAfterValue": "2000003",
+ "UMask": "0x3"
+ },
+ {
+ "BriefDescription": "Counts the number of unhalted reference clock cycles at TSC frequency.",
+ "EventCode": "0x3c",
+ "EventName": "CPU_CLK_UNHALTED.REF_TSC_P",
+ "PublicDescription": "Counts the number of reference cycles that the core is not in a halt state. The core enters the halt state when it is running the HLT instruction. This event is not affected by core frequency changes and increments at a fixed frequency that is also used for the Time Stamp Counter (TSC). This event uses a programmable general purpose performance counter.",
+ "SampleAfterValue": "2000003",
+ "UMask": "0x1"
+ },
+ {
+ "BriefDescription": "Fixed Counter: Counts the number of unhalted core clock cycles",
+ "EventName": "CPU_CLK_UNHALTED.THREAD",
+ "SampleAfterValue": "2000003",
+ "UMask": "0x2"
+ },
+ {
+ "BriefDescription": "Counts the number of unhalted core clock cycles [This event is alias to CPU_CLK_UNHALTED.CORE_P]",
+ "EventCode": "0x3c",
+ "EventName": "CPU_CLK_UNHALTED.THREAD_P",
+ "SampleAfterValue": "2000003"
+ },
+ {
+ "BriefDescription": "Fixed Counter: Counts the number of instructions retired",
+ "EventName": "INST_RETIRED.ANY",
+ "PEBS": "1",
+ "SampleAfterValue": "2000003",
+ "UMask": "0x1"
+ },
+ {
+ "BriefDescription": "Counts the number of instructions retired",
+ "EventCode": "0xc0",
+ "EventName": "INST_RETIRED.ANY_P",
+ "PEBS": "1",
+ "SampleAfterValue": "2000003"
+ },
+ {
+ "BriefDescription": "Counts the number of issue slots that were not consumed by the backend because allocation is stalled due to a mispredicted jump or a machine clear.",
+ "EventCode": "0x73",
+ "EventName": "TOPDOWN_BAD_SPECULATION.ALL",
+ "PublicDescription": "Counts the total number of issue slots that were not consumed by the backend because allocation is stalled due to a mispredicted jump or a machine clear. Only issue slots wasted due to fast nukes such as memory ordering nukes are counted. Other nukes are not accounted for. Counts all issue slots blocked during this recovery window, including relevant microcode flows, and while uops are not yet available in the instruction queue (IQ) or until an FE_BOUND event occurs besides OTHER and CISC. Also includes the issue slots that were consumed by the backend but were thrown away because they were younger than the mispredict or machine clear.",
+ "SampleAfterValue": "1000003"
+ },
+ {
+ "BriefDescription": "Counts the number of retirement slots not consumed due to backend stalls",
+ "EventCode": "0x74",
+ "EventName": "TOPDOWN_BE_BOUND.ALL",
+ "SampleAfterValue": "1000003"
+ },
+ {
+ "BriefDescription": "Counts the number of retirement slots not consumed due to front end stalls",
+ "EventCode": "0x71",
+ "EventName": "TOPDOWN_FE_BOUND.ALL",
+ "SampleAfterValue": "1000003"
+ },
+ {
+ "BriefDescription": "Counts the number of consumed retirement slots. Similar to UOPS_RETIRED.ALL",
+ "EventCode": "0x72",
+ "EventName": "TOPDOWN_RETIRING.ALL",
+ "PEBS": "1",
+ "SampleAfterValue": "1000003"
+ }
+]
diff --git a/tools/perf/pmu-events/arch/x86/grandridge/virtual-memory.json b/tools/perf/pmu-events/arch/x86/grandridge/virtual-memory.json
new file mode 100644
index 000000000000..bd5f2b634c98
--- /dev/null
+++ b/tools/perf/pmu-events/arch/x86/grandridge/virtual-memory.json
@@ -0,0 +1,24 @@
+[
+ {
+ "BriefDescription": "Counts the number of page walks completed due to load DTLB misses to a 1G page.",
+ "EventCode": "0x08",
+ "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED",
+ "SampleAfterValue": "1000003",
+ "UMask": "0xe"
+ },
+ {
+ "BriefDescription": "Counts the number of page walks completed due to store DTLB misses to a 1G page.",
+ "EventCode": "0x49",
+ "EventName": "DTLB_STORE_MISSES.WALK_COMPLETED",
+ "SampleAfterValue": "1000003",
+ "UMask": "0xe"
+ },
+ {
+ "BriefDescription": "Counts the number of page walks completed due to instruction fetch misses to any page size.",
+ "EventCode": "0x85",
+ "EventName": "ITLB_MISSES.WALK_COMPLETED",
+ "PublicDescription": "Counts the number of page walks completed due to instruction fetches whose address translations missed in all Translation Lookaside Buffer (TLB) levels and were mapped to any page size. Includes page walks that page fault.",
+ "SampleAfterValue": "200003",
+ "UMask": "0xe"
+ }
+]
diff --git a/tools/perf/pmu-events/arch/x86/mapfile.csv b/tools/perf/pmu-events/arch/x86/mapfile.csv
index 437eeecfaf64..c2b83cbae225 100644
--- a/tools/perf/pmu-events/arch/x86/mapfile.csv
+++ b/tools/perf/pmu-events/arch/x86/mapfile.csv
@@ -9,6 +9,7 @@ GenuineIntel-6-55-[56789ABCDEF],v1.17,cascadelakex,core
GenuineIntel-6-9[6C],v1.03,elkhartlake,core
GenuineIntel-6-5[CF],v13,goldmont,core
GenuineIntel-6-7A,v1.01,goldmontplus,core
+GenuineIntel-6-B6,v1.00,grandridge,core
GenuineIntel-6-A[DE],v1.01,graniterapids,core
GenuineIntel-6-(3C|45|46),v33,haswell,core
GenuineIntel-6-3F,v27,haswellx,core
--
2.40.0.577.gac1e443424-goog
^ permalink raw reply related [flat|nested] 18+ messages in thread* [PATCH v3 03/21] perf vendor events intel: Add sierraforest
2023-04-13 13:29 [PATCH v3 00/21] Update uncore topics, 1x event updates, 2x new archs Ian Rogers
2023-04-13 13:29 ` [PATCH v3 02/21] perf vendor events intel: Add grandridge Ian Rogers
@ 2023-04-13 13:29 ` Ian Rogers
2023-04-13 13:29 ` [PATCH v3 04/21] perf vendor events intel: Fix uncore topics for alderlake Ian Rogers
` (10 subsequent siblings)
12 siblings, 0 replies; 18+ messages in thread
From: Ian Rogers @ 2023-04-13 13:29 UTC (permalink / raw)
To: Peter Zijlstra, Ingo Molnar, Arnaldo Carvalho de Melo,
Mark Rutland, Alexander Shishkin, Jiri Olsa, Namhyung Kim,
Zhengjun Xing, Kan Liang, linux-perf-users, linux-kernel,
Edward Baker, Perry Taylor, Caleb Biggers
Cc: Stephane Eranian, Ian Rogers
Add v1.00 from:
https://github.com/intel/perfmon/pull/69
Signed-off-by: Ian Rogers <irogers@google.com>
---
tools/perf/pmu-events/arch/x86/mapfile.csv | 1 +
.../arch/x86/sierraforest/cache.json | 155 ++++++++++++++++++
.../arch/x86/sierraforest/frontend.json | 16 ++
.../arch/x86/sierraforest/memory.json | 20 +++
.../arch/x86/sierraforest/other.json | 20 +++
.../arch/x86/sierraforest/pipeline.json | 96 +++++++++++
.../arch/x86/sierraforest/virtual-memory.json | 24 +++
7 files changed, 332 insertions(+)
create mode 100644 tools/perf/pmu-events/arch/x86/sierraforest/cache.json
create mode 100644 tools/perf/pmu-events/arch/x86/sierraforest/frontend.json
create mode 100644 tools/perf/pmu-events/arch/x86/sierraforest/memory.json
create mode 100644 tools/perf/pmu-events/arch/x86/sierraforest/other.json
create mode 100644 tools/perf/pmu-events/arch/x86/sierraforest/pipeline.json
create mode 100644 tools/perf/pmu-events/arch/x86/sierraforest/virtual-memory.json
diff --git a/tools/perf/pmu-events/arch/x86/mapfile.csv b/tools/perf/pmu-events/arch/x86/mapfile.csv
index c2b83cbae225..66c37a3cbf43 100644
--- a/tools/perf/pmu-events/arch/x86/mapfile.csv
+++ b/tools/perf/pmu-events/arch/x86/mapfile.csv
@@ -24,6 +24,7 @@ GenuineIntel-6-1[AEF],v3,nehalemep,core
GenuineIntel-6-2E,v3,nehalemex,core
GenuineIntel-6-2A,v19,sandybridge,core
GenuineIntel-6-(8F|CF),v1.12,sapphirerapids,core
+GenuineIntel-6-AF,v1.00,sierraforest,core
GenuineIntel-6-(37|4A|4C|4D|5A),v15,silvermont,core
GenuineIntel-6-(4E|5E|8E|9E|A5|A6),v55,skylake,core
GenuineIntel-6-55-[01234],v1.29,skylakex,core
diff --git a/tools/perf/pmu-events/arch/x86/sierraforest/cache.json b/tools/perf/pmu-events/arch/x86/sierraforest/cache.json
new file mode 100644
index 000000000000..7f0dc65a55d2
--- /dev/null
+++ b/tools/perf/pmu-events/arch/x86/sierraforest/cache.json
@@ -0,0 +1,155 @@
+[
+ {
+ "BriefDescription": "Counts the number of cacheable memory requests that miss in the LLC. Counts on a per core basis.",
+ "EventCode": "0x2e",
+ "EventName": "LONGEST_LAT_CACHE.MISS",
+ "PublicDescription": "Counts the number of cacheable memory requests that miss in the Last Level Cache (LLC). Requests include demand loads, reads for ownership (RFO), instruction fetches and L1 HW prefetches. If the platform has an L3 cache, the LLC is the L3 cache, otherwise it is the L2 cache. Counts on a per core basis.",
+ "SampleAfterValue": "200003",
+ "UMask": "0x41"
+ },
+ {
+ "BriefDescription": "Counts the number of cacheable memory requests that access the LLC. Counts on a per core basis.",
+ "EventCode": "0x2e",
+ "EventName": "LONGEST_LAT_CACHE.REFERENCE",
+ "PublicDescription": "Counts the number of cacheable memory requests that access the Last Level Cache (LLC). Requests include demand loads, reads for ownership (RFO), instruction fetches and L1 HW prefetches. If the platform has an L3 cache, the LLC is the L3 cache, otherwise it is the L2 cache. Counts on a per core basis.",
+ "SampleAfterValue": "200003",
+ "UMask": "0x4f"
+ },
+ {
+ "BriefDescription": "Counts the number of load ops retired.",
+ "Data_LA": "1",
+ "EventCode": "0xd0",
+ "EventName": "MEM_UOPS_RETIRED.ALL_LOADS",
+ "PEBS": "1",
+ "SampleAfterValue": "200003",
+ "UMask": "0x81"
+ },
+ {
+ "BriefDescription": "Counts the number of store ops retired.",
+ "Data_LA": "1",
+ "EventCode": "0xd0",
+ "EventName": "MEM_UOPS_RETIRED.ALL_STORES",
+ "PEBS": "1",
+ "SampleAfterValue": "200003",
+ "UMask": "0x82"
+ },
+ {
+ "BriefDescription": "Counts the number of tagged load uops retired that exceed the latency threshold defined in MEC_CR_PEBS_LD_LAT_THRESHOLD - Only counts with PEBS enabled.",
+ "Data_LA": "1",
+ "EventCode": "0xd0",
+ "EventName": "MEM_UOPS_RETIRED.LOAD_LATENCY_GT_1024",
+ "MSRIndex": "0x3F6",
+ "MSRValue": "0x400",
+ "PEBS": "2",
+ "SampleAfterValue": "1000003",
+ "UMask": "0x5"
+ },
+ {
+ "BriefDescription": "Counts the number of tagged load uops retired that exceed the latency threshold defined in MEC_CR_PEBS_LD_LAT_THRESHOLD - Only counts with PEBS enabled.",
+ "Data_LA": "1",
+ "EventCode": "0xd0",
+ "EventName": "MEM_UOPS_RETIRED.LOAD_LATENCY_GT_128",
+ "MSRIndex": "0x3F6",
+ "MSRValue": "0x80",
+ "PEBS": "2",
+ "SampleAfterValue": "1000003",
+ "UMask": "0x5"
+ },
+ {
+ "BriefDescription": "Counts the number of tagged load uops retired that exceed the latency threshold defined in MEC_CR_PEBS_LD_LAT_THRESHOLD - Only counts with PEBS enabled.",
+ "Data_LA": "1",
+ "EventCode": "0xd0",
+ "EventName": "MEM_UOPS_RETIRED.LOAD_LATENCY_GT_16",
+ "MSRIndex": "0x3F6",
+ "MSRValue": "0x10",
+ "PEBS": "2",
+ "SampleAfterValue": "1000003",
+ "UMask": "0x5"
+ },
+ {
+ "BriefDescription": "Counts the number of tagged load uops retired that exceed the latency threshold defined in MEC_CR_PEBS_LD_LAT_THRESHOLD - Only counts with PEBS enabled.",
+ "Data_LA": "1",
+ "EventCode": "0xd0",
+ "EventName": "MEM_UOPS_RETIRED.LOAD_LATENCY_GT_2048",
+ "MSRIndex": "0x3F6",
+ "MSRValue": "0x800",
+ "PEBS": "2",
+ "SampleAfterValue": "1000003",
+ "UMask": "0x5"
+ },
+ {
+ "BriefDescription": "Counts the number of tagged load uops retired that exceed the latency threshold defined in MEC_CR_PEBS_LD_LAT_THRESHOLD - Only counts with PEBS enabled.",
+ "Data_LA": "1",
+ "EventCode": "0xd0",
+ "EventName": "MEM_UOPS_RETIRED.LOAD_LATENCY_GT_256",
+ "MSRIndex": "0x3F6",
+ "MSRValue": "0x100",
+ "PEBS": "2",
+ "SampleAfterValue": "1000003",
+ "UMask": "0x5"
+ },
+ {
+ "BriefDescription": "Counts the number of tagged load uops retired that exceed the latency threshold defined in MEC_CR_PEBS_LD_LAT_THRESHOLD - Only counts with PEBS enabled.",
+ "Data_LA": "1",
+ "EventCode": "0xd0",
+ "EventName": "MEM_UOPS_RETIRED.LOAD_LATENCY_GT_32",
+ "MSRIndex": "0x3F6",
+ "MSRValue": "0x20",
+ "PEBS": "2",
+ "SampleAfterValue": "1000003",
+ "UMask": "0x5"
+ },
+ {
+ "BriefDescription": "Counts the number of tagged load uops retired that exceed the latency threshold defined in MEC_CR_PEBS_LD_LAT_THRESHOLD - Only counts with PEBS enabled.",
+ "Data_LA": "1",
+ "EventCode": "0xd0",
+ "EventName": "MEM_UOPS_RETIRED.LOAD_LATENCY_GT_4",
+ "MSRIndex": "0x3F6",
+ "MSRValue": "0x4",
+ "PEBS": "2",
+ "SampleAfterValue": "1000003",
+ "UMask": "0x5"
+ },
+ {
+ "BriefDescription": "Counts the number of tagged load uops retired that exceed the latency threshold defined in MEC_CR_PEBS_LD_LAT_THRESHOLD - Only counts with PEBS enabled.",
+ "Data_LA": "1",
+ "EventCode": "0xd0",
+ "EventName": "MEM_UOPS_RETIRED.LOAD_LATENCY_GT_512",
+ "MSRIndex": "0x3F6",
+ "MSRValue": "0x200",
+ "PEBS": "2",
+ "SampleAfterValue": "1000003",
+ "UMask": "0x5"
+ },
+ {
+ "BriefDescription": "Counts the number of tagged load uops retired that exceed the latency threshold defined in MEC_CR_PEBS_LD_LAT_THRESHOLD - Only counts with PEBS enabled.",
+ "Data_LA": "1",
+ "EventCode": "0xd0",
+ "EventName": "MEM_UOPS_RETIRED.LOAD_LATENCY_GT_64",
+ "MSRIndex": "0x3F6",
+ "MSRValue": "0x40",
+ "PEBS": "2",
+ "SampleAfterValue": "1000003",
+ "UMask": "0x5"
+ },
+ {
+ "BriefDescription": "Counts the number of tagged load uops retired that exceed the latency threshold defined in MEC_CR_PEBS_LD_LAT_THRESHOLD - Only counts with PEBS enabled.",
+ "Data_LA": "1",
+ "EventCode": "0xd0",
+ "EventName": "MEM_UOPS_RETIRED.LOAD_LATENCY_GT_8",
+ "MSRIndex": "0x3F6",
+ "MSRValue": "0x8",
+ "PEBS": "2",
+ "SampleAfterValue": "1000003",
+ "UMask": "0x5"
+ },
+ {
+ "BriefDescription": "Counts the number of stores uops retired same as MEM_UOPS_RETIRED.ALL_STORES",
+ "Data_LA": "1",
+ "EventCode": "0xd0",
+ "EventName": "MEM_UOPS_RETIRED.STORE_LATENCY",
+ "PEBS": "2",
+ "SampleAfterValue": "1000003",
+ "UMask": "0x6"
+ }
+]
diff --git a/tools/perf/pmu-events/arch/x86/sierraforest/frontend.json b/tools/perf/pmu-events/arch/x86/sierraforest/frontend.json
new file mode 100644
index 000000000000..be8f1c7e195c
--- /dev/null
+++ b/tools/perf/pmu-events/arch/x86/sierraforest/frontend.json
@@ -0,0 +1,16 @@
+[
+ {
+ "BriefDescription": "Counts every time the code stream enters into a new cache line by walking sequential from the previous line or being redirected by a jump.",
+ "EventCode": "0x80",
+ "EventName": "ICACHE.ACCESSES",
+ "SampleAfterValue": "200003",
+ "UMask": "0x3"
+ },
+ {
+ "BriefDescription": "Counts every time the code stream enters into a new cache line by walking sequential from the previous line or being redirected by a jump and the instruction cache registers bytes are not present. -",
+ "EventCode": "0x80",
+ "EventName": "ICACHE.MISSES",
+ "SampleAfterValue": "200003",
+ "UMask": "0x2"
+ }
+]
diff --git a/tools/perf/pmu-events/arch/x86/sierraforest/memory.json b/tools/perf/pmu-events/arch/x86/sierraforest/memory.json
new file mode 100644
index 000000000000..79d8af45100c
--- /dev/null
+++ b/tools/perf/pmu-events/arch/x86/sierraforest/memory.json
@@ -0,0 +1,20 @@
+[
+ {
+ "BriefDescription": "Counts demand data reads that were not supplied by the L3 cache.",
+ "EventCode": "0xB7",
+ "EventName": "OCR.DEMAND_DATA_RD.L3_MISS",
+ "MSRIndex": "0x1a6,0x1a7",
+ "MSRValue": "0x3FBFC00001",
+ "SampleAfterValue": "100003",
+ "UMask": "0x1"
+ },
+ {
+ "BriefDescription": "Counts demand reads for ownership (RFO) and software prefetches for exclusive ownership (PREFETCHW) that were not supplied by the L3 cache.",
+ "EventCode": "0xB7",
+ "EventName": "OCR.DEMAND_RFO.L3_MISS",
+ "MSRIndex": "0x1a6,0x1a7",
+ "MSRValue": "0x3FBFC00002",
+ "SampleAfterValue": "100003",
+ "UMask": "0x1"
+ }
+]
diff --git a/tools/perf/pmu-events/arch/x86/sierraforest/other.json b/tools/perf/pmu-events/arch/x86/sierraforest/other.json
new file mode 100644
index 000000000000..2414f6ff53b0
--- /dev/null
+++ b/tools/perf/pmu-events/arch/x86/sierraforest/other.json
@@ -0,0 +1,20 @@
+[
+ {
+ "BriefDescription": "Counts demand data reads that have any type of response.",
+ "EventCode": "0xB7",
+ "EventName": "OCR.DEMAND_DATA_RD.ANY_RESPONSE",
+ "MSRIndex": "0x1a6,0x1a7",
+ "MSRValue": "0x10001",
+ "SampleAfterValue": "100003",
+ "UMask": "0x1"
+ },
+ {
+ "BriefDescription": "Counts demand reads for ownership (RFO) and software prefetches for exclusive ownership (PREFETCHW) that have any type of response.",
+ "EventCode": "0xB7",
+ "EventName": "OCR.DEMAND_RFO.ANY_RESPONSE",
+ "MSRIndex": "0x1a6,0x1a7",
+ "MSRValue": "0x10002",
+ "SampleAfterValue": "100003",
+ "UMask": "0x1"
+ }
+]
diff --git a/tools/perf/pmu-events/arch/x86/sierraforest/pipeline.json b/tools/perf/pmu-events/arch/x86/sierraforest/pipeline.json
new file mode 100644
index 000000000000..41212957ef21
--- /dev/null
+++ b/tools/perf/pmu-events/arch/x86/sierraforest/pipeline.json
@@ -0,0 +1,96 @@
+[
+ {
+ "BriefDescription": "Counts the total number of branch instructions retired for all branch types.",
+ "EventCode": "0xc4",
+ "EventName": "BR_INST_RETIRED.ALL_BRANCHES",
+ "PEBS": "1",
+ "PublicDescription": "Counts the total number of instructions in which the instruction pointer (IP) of the processor is resteered due to a branch instruction and the branch instruction successfully retires. All branch type instructions are accounted for.",
+ "SampleAfterValue": "200003"
+ },
+ {
+ "BriefDescription": "Counts the total number of mispredicted branch instructions retired for all branch types.",
+ "EventCode": "0xc5",
+ "EventName": "BR_MISP_RETIRED.ALL_BRANCHES",
+ "PEBS": "1",
+ "PublicDescription": "Counts the total number of mispredicted branch instructions retired. All branch type instructions are accounted for. Prediction of the branch target address enables the processor to begin executing instructions before the non-speculative execution path is known. The branch prediction unit (BPU) predicts the target address based on the instruction pointer (IP) of the branch and on the execution path through which execution reached this IP. A branch misprediction occurs when the prediction is wrong, and results in discarding all instructions executed in the speculative path and re-fetching from the correct path.",
+ "SampleAfterValue": "200003"
+ },
+ {
+ "BriefDescription": "Fixed Counter: Counts the number of unhalted core clock cycles",
+ "EventName": "CPU_CLK_UNHALTED.CORE",
+ "SampleAfterValue": "2000003",
+ "UMask": "0x2"
+ },
+ {
+ "BriefDescription": "Counts the number of unhalted core clock cycles [This event is alias to CPU_CLK_UNHALTED.THREAD_P]",
+ "EventCode": "0x3c",
+ "EventName": "CPU_CLK_UNHALTED.CORE_P",
+ "SampleAfterValue": "2000003"
+ },
+ {
+ "BriefDescription": "Fixed Counter: Counts the number of unhalted reference clock cycles",
+ "EventName": "CPU_CLK_UNHALTED.REF_TSC",
+ "SampleAfterValue": "2000003",
+ "UMask": "0x3"
+ },
+ {
+ "BriefDescription": "Counts the number of unhalted reference clock cycles at TSC frequency.",
+ "EventCode": "0x3c",
+ "EventName": "CPU_CLK_UNHALTED.REF_TSC_P",
+ "PublicDescription": "Counts the number of reference cycles that the core is not in a halt state. The core enters the halt state when it is running the HLT instruction. This event is not affected by core frequency changes and increments at a fixed frequency that is also used for the Time Stamp Counter (TSC). This event uses a programmable general purpose performance counter.",
+ "SampleAfterValue": "2000003",
+ "UMask": "0x1"
+ },
+ {
+ "BriefDescription": "Fixed Counter: Counts the number of unhalted core clock cycles",
+ "EventName": "CPU_CLK_UNHALTED.THREAD",
+ "SampleAfterValue": "2000003",
+ "UMask": "0x2"
+ },
+ {
+ "BriefDescription": "Counts the number of unhalted core clock cycles [This event is alias to CPU_CLK_UNHALTED.CORE_P]",
+ "EventCode": "0x3c",
+ "EventName": "CPU_CLK_UNHALTED.THREAD_P",
+ "SampleAfterValue": "2000003"
+ },
+ {
+ "BriefDescription": "Fixed Counter: Counts the number of instructions retired",
+ "EventName": "INST_RETIRED.ANY",
+ "PEBS": "1",
+ "SampleAfterValue": "2000003",
+ "UMask": "0x1"
+ },
+ {
+ "BriefDescription": "Counts the number of instructions retired",
+ "EventCode": "0xc0",
+ "EventName": "INST_RETIRED.ANY_P",
+ "PEBS": "1",
+ "SampleAfterValue": "2000003"
+ },
+ {
+ "BriefDescription": "Counts the number of issue slots that were not consumed by the backend because allocation is stalled due to a mispredicted jump or a machine clear.",
+ "EventCode": "0x73",
+ "EventName": "TOPDOWN_BAD_SPECULATION.ALL",
+ "PublicDescription": "Counts the total number of issue slots that were not consumed by the backend because allocation is stalled due to a mispredicted jump or a machine clear. Only issue slots wasted due to fast nukes such as memory ordering nukes are counted. Other nukes are not accounted for. Counts all issue slots blocked during this recovery window, including relevant microcode flows, and while uops are not yet available in the instruction queue (IQ) or until an FE_BOUND event occurs besides OTHER and CISC. Also includes the issue slots that were consumed by the backend but were thrown away because they were younger than the mispredict or machine clear.",
+ "SampleAfterValue": "1000003"
+ },
+ {
+ "BriefDescription": "Counts the number of retirement slots not consumed due to backend stalls",
+ "EventCode": "0x74",
+ "EventName": "TOPDOWN_BE_BOUND.ALL",
+ "SampleAfterValue": "1000003"
+ },
+ {
+ "BriefDescription": "Counts the number of retirement slots not consumed due to front end stalls",
+ "EventCode": "0x71",
+ "EventName": "TOPDOWN_FE_BOUND.ALL",
+ "SampleAfterValue": "1000003"
+ },
+ {
+ "BriefDescription": "Counts the number of consumed retirement slots. Similar to UOPS_RETIRED.ALL",
+ "EventCode": "0x72",
+ "EventName": "TOPDOWN_RETIRING.ALL",
+ "PEBS": "1",
+ "SampleAfterValue": "1000003"
+ }
+]
diff --git a/tools/perf/pmu-events/arch/x86/sierraforest/virtual-memory.json b/tools/perf/pmu-events/arch/x86/sierraforest/virtual-memory.json
new file mode 100644
index 000000000000..bd5f2b634c98
--- /dev/null
+++ b/tools/perf/pmu-events/arch/x86/sierraforest/virtual-memory.json
@@ -0,0 +1,24 @@
+[
+ {
+ "BriefDescription": "Counts the number of page walks completed due to load DTLB misses to a 1G page.",
+ "EventCode": "0x08",
+ "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED",
+ "SampleAfterValue": "1000003",
+ "UMask": "0xe"
+ },
+ {
+ "BriefDescription": "Counts the number of page walks completed due to store DTLB misses to a 1G page.",
+ "EventCode": "0x49",
+ "EventName": "DTLB_STORE_MISSES.WALK_COMPLETED",
+ "SampleAfterValue": "1000003",
+ "UMask": "0xe"
+ },
+ {
+ "BriefDescription": "Counts the number of page walks completed due to instruction fetch misses to any page size.",
+ "EventCode": "0x85",
+ "EventName": "ITLB_MISSES.WALK_COMPLETED",
+ "PublicDescription": "Counts the number of page walks completed due to instruction fetches whose address translations missed in all Translation Lookaside Buffer (TLB) levels and were mapped to any page size. Includes page walks that page fault.",
+ "SampleAfterValue": "200003",
+ "UMask": "0xe"
+ }
+]
--
2.40.0.577.gac1e443424-goog
^ permalink raw reply related [flat|nested] 18+ messages in thread* [PATCH v3 04/21] perf vendor events intel: Fix uncore topics for alderlake
2023-04-13 13:29 [PATCH v3 00/21] Update uncore topics, 1x event updates, 2x new archs Ian Rogers
2023-04-13 13:29 ` [PATCH v3 02/21] perf vendor events intel: Add grandridge Ian Rogers
2023-04-13 13:29 ` [PATCH v3 03/21] perf vendor events intel: Add sierraforest Ian Rogers
@ 2023-04-13 13:29 ` Ian Rogers
2023-04-13 13:29 ` [PATCH v3 05/21] perf vendor events intel: Fix uncore topics for broadwell Ian Rogers
` (9 subsequent siblings)
12 siblings, 0 replies; 18+ messages in thread
From: Ian Rogers @ 2023-04-13 13:29 UTC (permalink / raw)
To: Peter Zijlstra, Ingo Molnar, Arnaldo Carvalho de Melo,
Mark Rutland, Alexander Shishkin, Jiri Olsa, Namhyung Kim,
Zhengjun Xing, Kan Liang, linux-perf-users, linux-kernel,
Edward Baker, Perry Taylor, Caleb Biggers
Cc: Stephane Eranian, Ian Rogers
Move events from 'uncore-other' topic classification to interconnect.
Signed-off-by: Ian Rogers <irogers@google.com>
---
.../x86/alderlake/uncore-interconnect.json | 90 +++++++++++++++++++
.../arch/x86/alderlake/uncore-other.json | 88 ------------------
.../x86/alderlaken/uncore-interconnect.json | 26 ++++++
.../arch/x86/alderlaken/uncore-other.json | 24 -----
4 files changed, 116 insertions(+), 112 deletions(-)
create mode 100644 tools/perf/pmu-events/arch/x86/alderlake/uncore-interconnect.json
create mode 100644 tools/perf/pmu-events/arch/x86/alderlaken/uncore-interconnect.json
diff --git a/tools/perf/pmu-events/arch/x86/alderlake/uncore-interconnect.json b/tools/perf/pmu-events/arch/x86/alderlake/uncore-interconnect.json
new file mode 100644
index 000000000000..34fc052d00e4
--- /dev/null
+++ b/tools/perf/pmu-events/arch/x86/alderlake/uncore-interconnect.json
@@ -0,0 +1,90 @@
+[
+ {
+ "BriefDescription": "Number of requests allocated in Coherency Tracker.",
+ "EventCode": "0x84",
+ "EventName": "UNC_ARB_COH_TRK_REQUESTS.ALL",
+ "PerPkg": "1",
+ "UMask": "0x1",
+ "Unit": "ARB"
+ },
+ {
+ "BriefDescription": "Each cycle counts number of any coherent request at memory controller that were issued by any core.",
+ "EventCode": "0x85",
+ "EventName": "UNC_ARB_DAT_OCCUPANCY.ALL",
+ "PerPkg": "1",
+ "UMask": "0x1",
+ "Unit": "ARB"
+ },
+ {
+ "BriefDescription": "Each cycle counts number of coherent reads pending on data return from memory controller that were issued by any core.",
+ "EventCode": "0x85",
+ "EventName": "UNC_ARB_DAT_OCCUPANCY.RD",
+ "PerPkg": "1",
+ "UMask": "0x2",
+ "Unit": "ARB"
+ },
+ {
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_ARB_REQ_TRK_REQUEST.DRD",
+ "EventCode": "0x81",
+ "EventName": "UNC_ARB_DAT_REQUESTS.RD",
+ "PerPkg": "1",
+ "UMask": "0x2",
+ "Unit": "ARB"
+ },
+ {
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_ARB_DAT_OCCUPANCY.ALL",
+ "EventCode": "0x85",
+ "EventName": "UNC_ARB_IFA_OCCUPANCY.ALL",
+ "PerPkg": "1",
+ "UMask": "0x1",
+ "Unit": "ARB"
+ },
+ {
+ "BriefDescription": "Each cycle count number of 'valid' coherent Data Read entries . Such entry is defined as valid when it is allocated till deallocation. Doesn't include prefetches [This event is alias to UNC_ARB_TRK_OCCUPANCY.RD]",
+ "EventCode": "0x80",
+ "EventName": "UNC_ARB_REQ_TRK_OCCUPANCY.DRD",
+ "PerPkg": "1",
+ "UMask": "0x2",
+ "Unit": "ARB"
+ },
+ {
+ "BriefDescription": "Number of all coherent Data Read entries. Doesn't include prefetches [This event is alias to UNC_ARB_TRK_REQUESTS.RD]",
+ "EventCode": "0x81",
+ "EventName": "UNC_ARB_REQ_TRK_REQUEST.DRD",
+ "PerPkg": "1",
+ "UMask": "0x2",
+ "Unit": "ARB"
+ },
+ {
+ "BriefDescription": "Each cycle counts number of all outgoing valid entries in ReqTrk. Such entry is defined as valid from its allocation in ReqTrk till deallocation. Accounts for Coherent and non-coherent traffic.",
+ "EventCode": "0x80",
+ "EventName": "UNC_ARB_TRK_OCCUPANCY.ALL",
+ "PerPkg": "1",
+ "UMask": "0x1",
+ "Unit": "ARB"
+ },
+ {
+ "BriefDescription": "Each cycle count number of 'valid' coherent Data Read entries . Such entry is defined as valid when it is allocated till deallocation. Doesn't include prefetches [This event is alias to UNC_ARB_REQ_TRK_OCCUPANCY.DRD]",
+ "EventCode": "0x80",
+ "EventName": "UNC_ARB_TRK_OCCUPANCY.RD",
+ "PerPkg": "1",
+ "UMask": "0x2",
+ "Unit": "ARB"
+ },
+ {
+ "BriefDescription": "Counts the number of coherent and in-coherent requests initiated by IA cores, processor graphic units, or LLC.",
+ "EventCode": "0x81",
+ "EventName": "UNC_ARB_TRK_REQUESTS.ALL",
+ "PerPkg": "1",
+ "UMask": "0x1",
+ "Unit": "ARB"
+ },
+ {
+ "BriefDescription": "Number of all coherent Data Read entries. Doesn't include prefetches [This event is alias to UNC_ARB_REQ_TRK_REQUEST.DRD]",
+ "EventCode": "0x81",
+ "EventName": "UNC_ARB_TRK_REQUESTS.RD",
+ "PerPkg": "1",
+ "UMask": "0x2",
+ "Unit": "ARB"
+ }
+]
diff --git a/tools/perf/pmu-events/arch/x86/alderlake/uncore-other.json b/tools/perf/pmu-events/arch/x86/alderlake/uncore-other.json
index 5f3b4c6e2e39..2af92e43b28a 100644
--- a/tools/perf/pmu-events/arch/x86/alderlake/uncore-other.json
+++ b/tools/perf/pmu-events/arch/x86/alderlake/uncore-other.json
@@ -1,92 +1,4 @@
[
- {
- "BriefDescription": "Number of requests allocated in Coherency Tracker.",
- "EventCode": "0x84",
- "EventName": "UNC_ARB_COH_TRK_REQUESTS.ALL",
- "PerPkg": "1",
- "UMask": "0x1",
- "Unit": "ARB"
- },
- {
- "BriefDescription": "Each cycle counts number of any coherent request at memory controller that were issued by any core.",
- "EventCode": "0x85",
- "EventName": "UNC_ARB_DAT_OCCUPANCY.ALL",
- "PerPkg": "1",
- "UMask": "0x1",
- "Unit": "ARB"
- },
- {
- "BriefDescription": "Each cycle counts number of coherent reads pending on data return from memory controller that were issued by any core.",
- "EventCode": "0x85",
- "EventName": "UNC_ARB_DAT_OCCUPANCY.RD",
- "PerPkg": "1",
- "UMask": "0x2",
- "Unit": "ARB"
- },
- {
- "BriefDescription": "This event is deprecated. Refer to new event UNC_ARB_REQ_TRK_REQUEST.DRD",
- "EventCode": "0x81",
- "EventName": "UNC_ARB_DAT_REQUESTS.RD",
- "PerPkg": "1",
- "UMask": "0x2",
- "Unit": "ARB"
- },
- {
- "BriefDescription": "This event is deprecated. Refer to new event UNC_ARB_DAT_OCCUPANCY.ALL",
- "EventCode": "0x85",
- "EventName": "UNC_ARB_IFA_OCCUPANCY.ALL",
- "PerPkg": "1",
- "UMask": "0x1",
- "Unit": "ARB"
- },
- {
- "BriefDescription": "Each cycle count number of 'valid' coherent Data Read entries . Such entry is defined as valid when it is allocated till deallocation. Doesn't include prefetches [This event is alias to UNC_ARB_TRK_OCCUPANCY.RD]",
- "EventCode": "0x80",
- "EventName": "UNC_ARB_REQ_TRK_OCCUPANCY.DRD",
- "PerPkg": "1",
- "UMask": "0x2",
- "Unit": "ARB"
- },
- {
- "BriefDescription": "Number of all coherent Data Read entries. Doesn't include prefetches [This event is alias to UNC_ARB_TRK_REQUESTS.RD]",
- "EventCode": "0x81",
- "EventName": "UNC_ARB_REQ_TRK_REQUEST.DRD",
- "PerPkg": "1",
- "UMask": "0x2",
- "Unit": "ARB"
- },
- {
- "BriefDescription": "Each cycle counts number of all outgoing valid entries in ReqTrk. Such entry is defined as valid from its allocation in ReqTrk till deallocation. Accounts for Coherent and non-coherent traffic.",
- "EventCode": "0x80",
- "EventName": "UNC_ARB_TRK_OCCUPANCY.ALL",
- "PerPkg": "1",
- "UMask": "0x1",
- "Unit": "ARB"
- },
- {
- "BriefDescription": "Each cycle count number of 'valid' coherent Data Read entries . Such entry is defined as valid when it is allocated till deallocation. Doesn't include prefetches [This event is alias to UNC_ARB_REQ_TRK_OCCUPANCY.DRD]",
- "EventCode": "0x80",
- "EventName": "UNC_ARB_TRK_OCCUPANCY.RD",
- "PerPkg": "1",
- "UMask": "0x2",
- "Unit": "ARB"
- },
- {
- "BriefDescription": "Counts the number of coherent and in-coherent requests initiated by IA cores, processor graphic units, or LLC.",
- "EventCode": "0x81",
- "EventName": "UNC_ARB_TRK_REQUESTS.ALL",
- "PerPkg": "1",
- "UMask": "0x1",
- "Unit": "ARB"
- },
- {
- "BriefDescription": "Number of all coherent Data Read entries. Doesn't include prefetches [This event is alias to UNC_ARB_REQ_TRK_REQUEST.DRD]",
- "EventCode": "0x81",
- "EventName": "UNC_ARB_TRK_REQUESTS.RD",
- "PerPkg": "1",
- "UMask": "0x2",
- "Unit": "ARB"
- },
{
"BriefDescription": "This 48-bit fixed counter counts the UCLK cycles.",
"EventCode": "0xff",
diff --git a/tools/perf/pmu-events/arch/x86/alderlaken/uncore-interconnect.json b/tools/perf/pmu-events/arch/x86/alderlaken/uncore-interconnect.json
new file mode 100644
index 000000000000..4af695a5e755
--- /dev/null
+++ b/tools/perf/pmu-events/arch/x86/alderlaken/uncore-interconnect.json
@@ -0,0 +1,26 @@
+[
+ {
+ "BriefDescription": "Number of requests allocated in Coherency Tracker.",
+ "EventCode": "0x84",
+ "EventName": "UNC_ARB_COH_TRK_REQUESTS.ALL",
+ "PerPkg": "1",
+ "UMask": "0x1",
+ "Unit": "ARB"
+ },
+ {
+ "BriefDescription": "Each cycle counts number of all outgoing valid entries in ReqTrk. Such entry is defined as valid from its allocation in ReqTrk till deallocation. Accounts for Coherent and non-coherent traffic.",
+ "EventCode": "0x80",
+ "EventName": "UNC_ARB_TRK_OCCUPANCY.ALL",
+ "PerPkg": "1",
+ "UMask": "0x1",
+ "Unit": "ARB"
+ },
+ {
+ "BriefDescription": "Counts the number of coherent and in-coherent requests initiated by IA cores, processor graphic units, or LLC.",
+ "EventCode": "0x81",
+ "EventName": "UNC_ARB_TRK_REQUESTS.ALL",
+ "PerPkg": "1",
+ "UMask": "0x1",
+ "Unit": "ARB"
+ }
+]
diff --git a/tools/perf/pmu-events/arch/x86/alderlaken/uncore-other.json b/tools/perf/pmu-events/arch/x86/alderlaken/uncore-other.json
index f9e7777cd2be..2af92e43b28a 100644
--- a/tools/perf/pmu-events/arch/x86/alderlaken/uncore-other.json
+++ b/tools/perf/pmu-events/arch/x86/alderlaken/uncore-other.json
@@ -1,28 +1,4 @@
[
- {
- "BriefDescription": "Number of requests allocated in Coherency Tracker.",
- "EventCode": "0x84",
- "EventName": "UNC_ARB_COH_TRK_REQUESTS.ALL",
- "PerPkg": "1",
- "UMask": "0x1",
- "Unit": "ARB"
- },
- {
- "BriefDescription": "Each cycle counts number of all outgoing valid entries in ReqTrk. Such entry is defined as valid from its allocation in ReqTrk till deallocation. Accounts for Coherent and non-coherent traffic.",
- "EventCode": "0x80",
- "EventName": "UNC_ARB_TRK_OCCUPANCY.ALL",
- "PerPkg": "1",
- "UMask": "0x1",
- "Unit": "ARB"
- },
- {
- "BriefDescription": "Counts the number of coherent and in-coherent requests initiated by IA cores, processor graphic units, or LLC.",
- "EventCode": "0x81",
- "EventName": "UNC_ARB_TRK_REQUESTS.ALL",
- "PerPkg": "1",
- "UMask": "0x1",
- "Unit": "ARB"
- },
{
"BriefDescription": "This 48-bit fixed counter counts the UCLK cycles.",
"EventCode": "0xff",
--
2.40.0.577.gac1e443424-goog
^ permalink raw reply related [flat|nested] 18+ messages in thread* [PATCH v3 05/21] perf vendor events intel: Fix uncore topics for broadwell
2023-04-13 13:29 [PATCH v3 00/21] Update uncore topics, 1x event updates, 2x new archs Ian Rogers
` (2 preceding siblings ...)
2023-04-13 13:29 ` [PATCH v3 04/21] perf vendor events intel: Fix uncore topics for alderlake Ian Rogers
@ 2023-04-13 13:29 ` Ian Rogers
2023-04-13 13:29 ` [PATCH v3 09/21] perf vendor events intel: Fix uncore topics for haswell Ian Rogers
` (8 subsequent siblings)
12 siblings, 0 replies; 18+ messages in thread
From: Ian Rogers @ 2023-04-13 13:29 UTC (permalink / raw)
To: Peter Zijlstra, Ingo Molnar, Arnaldo Carvalho de Melo,
Mark Rutland, Alexander Shishkin, Jiri Olsa, Namhyung Kim,
Zhengjun Xing, Kan Liang, linux-perf-users, linux-kernel,
Edward Baker, Perry Taylor, Caleb Biggers
Cc: Stephane Eranian, Ian Rogers
Reduce the number of 'uncore-other' topic classifications, move to
cache and interconnect.
Signed-off-by: Ian Rogers <irogers@google.com>
---
.../arch/x86/broadwell/uncore-cache.json | 30 ++++-----
.../x86/broadwell/uncore-interconnect.json | 61 +++++++++++++++++++
.../arch/x86/broadwell/uncore-other.json | 59 ------------------
3 files changed, 76 insertions(+), 74 deletions(-)
create mode 100644 tools/perf/pmu-events/arch/x86/broadwell/uncore-interconnect.json
diff --git a/tools/perf/pmu-events/arch/x86/broadwell/uncore-cache.json b/tools/perf/pmu-events/arch/x86/broadwell/uncore-cache.json
index fcb15b880bad..c5cc43825cb9 100644
--- a/tools/perf/pmu-events/arch/x86/broadwell/uncore-cache.json
+++ b/tools/perf/pmu-events/arch/x86/broadwell/uncore-cache.json
@@ -6,7 +6,7 @@
"PerPkg": "1",
"PublicDescription": "L3 Lookup any request that access cache and found line in E or S-state.",
"UMask": "0x86",
- "Unit": "CBO"
+ "Unit": "CBOX"
},
{
"BriefDescription": "L3 Lookup any request that access cache and found line in I-state",
@@ -15,7 +15,7 @@
"PerPkg": "1",
"PublicDescription": "L3 Lookup any request that access cache and found line in I-state.",
"UMask": "0x88",
- "Unit": "CBO"
+ "Unit": "CBOX"
},
{
"BriefDescription": "L3 Lookup any request that access cache and found line in M-state",
@@ -24,7 +24,7 @@
"PerPkg": "1",
"PublicDescription": "L3 Lookup any request that access cache and found line in M-state.",
"UMask": "0x81",
- "Unit": "CBO"
+ "Unit": "CBOX"
},
{
"BriefDescription": "L3 Lookup any request that access cache and found line in MESI-state",
@@ -33,7 +33,7 @@
"PerPkg": "1",
"PublicDescription": "L3 Lookup any request that access cache and found line in MESI-state.",
"UMask": "0x8f",
- "Unit": "CBO"
+ "Unit": "CBOX"
},
{
"BriefDescription": "L3 Lookup read request that access cache and found line in E or S-state",
@@ -42,7 +42,7 @@
"PerPkg": "1",
"PublicDescription": "L3 Lookup read request that access cache and found line in E or S-state.",
"UMask": "0x16",
- "Unit": "CBO"
+ "Unit": "CBOX"
},
{
"BriefDescription": "L3 Lookup read request that access cache and found line in I-state",
@@ -51,7 +51,7 @@
"PerPkg": "1",
"PublicDescription": "L3 Lookup read request that access cache and found line in I-state.",
"UMask": "0x18",
- "Unit": "CBO"
+ "Unit": "CBOX"
},
{
"BriefDescription": "L3 Lookup read request that access cache and found line in M-state",
@@ -60,7 +60,7 @@
"PerPkg": "1",
"PublicDescription": "L3 Lookup read request that access cache and found line in M-state.",
"UMask": "0x11",
- "Unit": "CBO"
+ "Unit": "CBOX"
},
{
"BriefDescription": "L3 Lookup read request that access cache and found line in any MESI-state",
@@ -69,7 +69,7 @@
"PerPkg": "1",
"PublicDescription": "L3 Lookup read request that access cache and found line in any MESI-state.",
"UMask": "0x1f",
- "Unit": "CBO"
+ "Unit": "CBOX"
},
{
"BriefDescription": "L3 Lookup write request that access cache and found line in E or S-state",
@@ -78,7 +78,7 @@
"PerPkg": "1",
"PublicDescription": "L3 Lookup write request that access cache and found line in E or S-state.",
"UMask": "0x26",
- "Unit": "CBO"
+ "Unit": "CBOX"
},
{
"BriefDescription": "L3 Lookup write request that access cache and found line in M-state",
@@ -87,7 +87,7 @@
"PerPkg": "1",
"PublicDescription": "L3 Lookup write request that access cache and found line in M-state.",
"UMask": "0x21",
- "Unit": "CBO"
+ "Unit": "CBOX"
},
{
"BriefDescription": "L3 Lookup write request that access cache and found line in MESI-state",
@@ -96,7 +96,7 @@
"PerPkg": "1",
"PublicDescription": "L3 Lookup write request that access cache and found line in MESI-state.",
"UMask": "0x2f",
- "Unit": "CBO"
+ "Unit": "CBOX"
},
{
"BriefDescription": "A cross-core snoop initiated by this Cbox due to processor core memory request which hits a modified line in some processor core.",
@@ -104,7 +104,7 @@
"EventName": "UNC_CBO_XSNP_RESPONSE.HITM_XCORE",
"PerPkg": "1",
"UMask": "0x48",
- "Unit": "CBO"
+ "Unit": "CBOX"
},
{
"BriefDescription": "A cross-core snoop initiated by this Cbox due to processor core memory request which hits a non-modified line in some processor core.",
@@ -112,7 +112,7 @@
"EventName": "UNC_CBO_XSNP_RESPONSE.HIT_XCORE",
"PerPkg": "1",
"UMask": "0x44",
- "Unit": "CBO"
+ "Unit": "CBOX"
},
{
"BriefDescription": "A cross-core snoop resulted from L3 Eviction which misses in some processor core.",
@@ -120,7 +120,7 @@
"EventName": "UNC_CBO_XSNP_RESPONSE.MISS_EVICTION",
"PerPkg": "1",
"UMask": "0x81",
- "Unit": "CBO"
+ "Unit": "CBOX"
},
{
"BriefDescription": "A cross-core snoop initiated by this Cbox due to processor core memory request which misses in some processor core.",
@@ -128,6 +128,6 @@
"EventName": "UNC_CBO_XSNP_RESPONSE.MISS_XCORE",
"PerPkg": "1",
"UMask": "0x41",
- "Unit": "CBO"
+ "Unit": "CBOX"
}
]
diff --git a/tools/perf/pmu-events/arch/x86/broadwell/uncore-interconnect.json b/tools/perf/pmu-events/arch/x86/broadwell/uncore-interconnect.json
new file mode 100644
index 000000000000..64af685274a2
--- /dev/null
+++ b/tools/perf/pmu-events/arch/x86/broadwell/uncore-interconnect.json
@@ -0,0 +1,61 @@
+[
+ {
+ "BriefDescription": "Number of entries allocated. Account for Any type: e.g. Snoop, Core aperture, etc.",
+ "EventCode": "0x84",
+ "EventName": "UNC_ARB_COH_TRK_REQUESTS.ALL",
+ "PerPkg": "1",
+ "UMask": "0x1",
+ "Unit": "ARB"
+ },
+ {
+ "BriefDescription": "Each cycle counts number of all Core outgoing valid entries. Such entry is defined as valid from its allocation till first of IDI0 or DRS0 messages is sent out. Accounts for Coherent and non-coherent traffic.",
+ "EventCode": "0x80",
+ "EventName": "UNC_ARB_TRK_OCCUPANCY.ALL",
+ "PerPkg": "1",
+ "UMask": "0x1",
+ "Unit": "ARB"
+ },
+ {
+ "BriefDescription": "Cycles with at least one request outstanding is waiting for data return from memory controller. Account for coherent and non-coherent requests initiated by IA Cores, Processor Graphics Unit, or LLC.;",
+ "CounterMask": "1",
+ "EventCode": "0x80",
+ "EventName": "UNC_ARB_TRK_OCCUPANCY.CYCLES_WITH_ANY_REQUEST",
+ "PerPkg": "1",
+ "UMask": "0x1",
+ "Unit": "ARB"
+ },
+ {
+ "BriefDescription": "Each cycle count number of 'valid' coherent Data Read entries that are in DirectData mode. Such entry is defined as valid when it is allocated till data sent to Core (first chunk, IDI0). Applicable for IA Cores' requests in normal case.",
+ "EventCode": "0x80",
+ "EventName": "UNC_ARB_TRK_OCCUPANCY.DRD_DIRECT",
+ "PerPkg": "1",
+ "PublicDescription": "Each cycle count number of valid coherent Data Read entries that are in DirectData mode. Such entry is defined as valid when it is allocated till data sent to Core (first chunk, IDI0). Applicable for IA Cores' requests in normal case.",
+ "UMask": "0x2",
+ "Unit": "ARB"
+ },
+ {
+ "BriefDescription": "Total number of Core outgoing entries allocated. Accounts for Coherent and non-coherent traffic.",
+ "EventCode": "0x81",
+ "EventName": "UNC_ARB_TRK_REQUESTS.ALL",
+ "PerPkg": "1",
+ "UMask": "0x1",
+ "Unit": "ARB"
+ },
+ {
+ "BriefDescription": "Number of Core coherent Data Read entries allocated in DirectData mode",
+ "EventCode": "0x81",
+ "EventName": "UNC_ARB_TRK_REQUESTS.DRD_DIRECT",
+ "PerPkg": "1",
+ "PublicDescription": "Number of Core coherent Data Read entries allocated in DirectData mode.",
+ "UMask": "0x2",
+ "Unit": "ARB"
+ },
+ {
+ "BriefDescription": "Number of Writes allocated - any write transactions: full/partials writes and evictions.",
+ "EventCode": "0x81",
+ "EventName": "UNC_ARB_TRK_REQUESTS.WRITES",
+ "PerPkg": "1",
+ "UMask": "0x20",
+ "Unit": "ARB"
+ }
+]
diff --git a/tools/perf/pmu-events/arch/x86/broadwell/uncore-other.json b/tools/perf/pmu-events/arch/x86/broadwell/uncore-other.json
index 368a958a18a0..58be90d7cc93 100644
--- a/tools/perf/pmu-events/arch/x86/broadwell/uncore-other.json
+++ b/tools/perf/pmu-events/arch/x86/broadwell/uncore-other.json
@@ -1,63 +1,4 @@
[
- {
- "BriefDescription": "Number of entries allocated. Account for Any type: e.g. Snoop, Core aperture, etc.",
- "EventCode": "0x84",
- "EventName": "UNC_ARB_COH_TRK_REQUESTS.ALL",
- "PerPkg": "1",
- "UMask": "0x1",
- "Unit": "ARB"
- },
- {
- "BriefDescription": "Each cycle counts number of all Core outgoing valid entries. Such entry is defined as valid from its allocation till first of IDI0 or DRS0 messages is sent out. Accounts for Coherent and non-coherent traffic.",
- "EventCode": "0x80",
- "EventName": "UNC_ARB_TRK_OCCUPANCY.ALL",
- "PerPkg": "1",
- "UMask": "0x1",
- "Unit": "ARB"
- },
- {
- "BriefDescription": "Cycles with at least one request outstanding is waiting for data return from memory controller. Account for coherent and non-coherent requests initiated by IA Cores, Processor Graphics Unit, or LLC.;",
- "CounterMask": "1",
- "EventCode": "0x80",
- "EventName": "UNC_ARB_TRK_OCCUPANCY.CYCLES_WITH_ANY_REQUEST",
- "PerPkg": "1",
- "UMask": "0x1",
- "Unit": "ARB"
- },
- {
- "BriefDescription": "Each cycle count number of 'valid' coherent Data Read entries that are in DirectData mode. Such entry is defined as valid when it is allocated till data sent to Core (first chunk, IDI0). Applicable for IA Cores' requests in normal case.",
- "EventCode": "0x80",
- "EventName": "UNC_ARB_TRK_OCCUPANCY.DRD_DIRECT",
- "PerPkg": "1",
- "PublicDescription": "Each cycle count number of valid coherent Data Read entries that are in DirectData mode. Such entry is defined as valid when it is allocated till data sent to Core (first chunk, IDI0). Applicable for IA Cores' requests in normal case.",
- "UMask": "0x2",
- "Unit": "ARB"
- },
- {
- "BriefDescription": "Total number of Core outgoing entries allocated. Accounts for Coherent and non-coherent traffic.",
- "EventCode": "0x81",
- "EventName": "UNC_ARB_TRK_REQUESTS.ALL",
- "PerPkg": "1",
- "UMask": "0x1",
- "Unit": "ARB"
- },
- {
- "BriefDescription": "Number of Core coherent Data Read entries allocated in DirectData mode",
- "EventCode": "0x81",
- "EventName": "UNC_ARB_TRK_REQUESTS.DRD_DIRECT",
- "PerPkg": "1",
- "PublicDescription": "Number of Core coherent Data Read entries allocated in DirectData mode.",
- "UMask": "0x2",
- "Unit": "ARB"
- },
- {
- "BriefDescription": "Number of Writes allocated - any write transactions: full/partials writes and evictions.",
- "EventCode": "0x81",
- "EventName": "UNC_ARB_TRK_REQUESTS.WRITES",
- "PerPkg": "1",
- "UMask": "0x20",
- "Unit": "ARB"
- },
{
"BriefDescription": "This 48-bit fixed counter counts the UCLK cycles",
"EventCode": "0xff",
--
2.40.0.577.gac1e443424-goog
^ permalink raw reply related [flat|nested] 18+ messages in thread* [PATCH v3 09/21] perf vendor events intel: Fix uncore topics for haswell
2023-04-13 13:29 [PATCH v3 00/21] Update uncore topics, 1x event updates, 2x new archs Ian Rogers
` (3 preceding siblings ...)
2023-04-13 13:29 ` [PATCH v3 05/21] perf vendor events intel: Fix uncore topics for broadwell Ian Rogers
@ 2023-04-13 13:29 ` Ian Rogers
2023-04-13 13:29 ` [PATCH v3 11/21] perf vendor events intel: Fix uncore topics for icelake Ian Rogers
` (7 subsequent siblings)
12 siblings, 0 replies; 18+ messages in thread
From: Ian Rogers @ 2023-04-13 13:29 UTC (permalink / raw)
To: Peter Zijlstra, Ingo Molnar, Arnaldo Carvalho de Melo,
Mark Rutland, Alexander Shishkin, Jiri Olsa, Namhyung Kim,
Zhengjun Xing, Kan Liang, linux-perf-users, linux-kernel,
Edward Baker, Perry Taylor, Caleb Biggers
Cc: Stephane Eranian, Ian Rogers
Move events from 'uncore-other' topic classification to cache and
interconnect.
Signed-off-by: Ian Rogers <irogers@google.com>
---
.../arch/x86/haswell/uncore-cache.json | 50 +++++++++---------
.../arch/x86/haswell/uncore-interconnect.json | 52 +++++++++++++++++++
.../arch/x86/haswell/uncore-other.json | 50 ------------------
3 files changed, 77 insertions(+), 75 deletions(-)
create mode 100644 tools/perf/pmu-events/arch/x86/haswell/uncore-interconnect.json
diff --git a/tools/perf/pmu-events/arch/x86/haswell/uncore-cache.json b/tools/perf/pmu-events/arch/x86/haswell/uncore-cache.json
index c538557ba4c0..be9a3ed1a940 100644
--- a/tools/perf/pmu-events/arch/x86/haswell/uncore-cache.json
+++ b/tools/perf/pmu-events/arch/x86/haswell/uncore-cache.json
@@ -5,7 +5,7 @@
"EventName": "UNC_CBO_CACHE_LOOKUP.ANY_ES",
"PerPkg": "1",
"UMask": "0x86",
- "Unit": "CBO"
+ "Unit": "CBOX"
},
{
"BriefDescription": "L3 Lookup any request that access cache and found line in I-state.",
@@ -13,7 +13,7 @@
"EventName": "UNC_CBO_CACHE_LOOKUP.ANY_I",
"PerPkg": "1",
"UMask": "0x88",
- "Unit": "CBO"
+ "Unit": "CBOX"
},
{
"BriefDescription": "L3 Lookup any request that access cache and found line in M-state.",
@@ -21,7 +21,7 @@
"EventName": "UNC_CBO_CACHE_LOOKUP.ANY_M",
"PerPkg": "1",
"UMask": "0x81",
- "Unit": "CBO"
+ "Unit": "CBOX"
},
{
"BriefDescription": "L3 Lookup any request that access cache and found line in MESI-state.",
@@ -29,7 +29,7 @@
"EventName": "UNC_CBO_CACHE_LOOKUP.ANY_MESI",
"PerPkg": "1",
"UMask": "0x8f",
- "Unit": "CBO"
+ "Unit": "CBOX"
},
{
"BriefDescription": "L3 Lookup external snoop request that access cache and found line in E or S-state.",
@@ -37,7 +37,7 @@
"EventName": "UNC_CBO_CACHE_LOOKUP.EXTSNP_ES",
"PerPkg": "1",
"UMask": "0x46",
- "Unit": "CBO"
+ "Unit": "CBOX"
},
{
"BriefDescription": "L3 Lookup external snoop request that access cache and found line in I-state.",
@@ -45,7 +45,7 @@
"EventName": "UNC_CBO_CACHE_LOOKUP.EXTSNP_I",
"PerPkg": "1",
"UMask": "0x48",
- "Unit": "CBO"
+ "Unit": "CBOX"
},
{
"BriefDescription": "L3 Lookup external snoop request that access cache and found line in M-state.",
@@ -53,7 +53,7 @@
"EventName": "UNC_CBO_CACHE_LOOKUP.EXTSNP_M",
"PerPkg": "1",
"UMask": "0x41",
- "Unit": "CBO"
+ "Unit": "CBOX"
},
{
"BriefDescription": "L3 Lookup external snoop request that access cache and found line in MESI-state.",
@@ -61,7 +61,7 @@
"EventName": "UNC_CBO_CACHE_LOOKUP.EXTSNP_MESI",
"PerPkg": "1",
"UMask": "0x4f",
- "Unit": "CBO"
+ "Unit": "CBOX"
},
{
"BriefDescription": "L3 Lookup read request that access cache and found line in E or S-state.",
@@ -69,7 +69,7 @@
"EventName": "UNC_CBO_CACHE_LOOKUP.READ_ES",
"PerPkg": "1",
"UMask": "0x16",
- "Unit": "CBO"
+ "Unit": "CBOX"
},
{
"BriefDescription": "L3 Lookup read request that access cache and found line in I-state.",
@@ -77,7 +77,7 @@
"EventName": "UNC_CBO_CACHE_LOOKUP.READ_I",
"PerPkg": "1",
"UMask": "0x18",
- "Unit": "CBO"
+ "Unit": "CBOX"
},
{
"BriefDescription": "L3 Lookup read request that access cache and found line in M-state.",
@@ -85,7 +85,7 @@
"EventName": "UNC_CBO_CACHE_LOOKUP.READ_M",
"PerPkg": "1",
"UMask": "0x11",
- "Unit": "CBO"
+ "Unit": "CBOX"
},
{
"BriefDescription": "L3 Lookup read request that access cache and found line in any MESI-state.",
@@ -93,7 +93,7 @@
"EventName": "UNC_CBO_CACHE_LOOKUP.READ_MESI",
"PerPkg": "1",
"UMask": "0x1f",
- "Unit": "CBO"
+ "Unit": "CBOX"
},
{
"BriefDescription": "L3 Lookup write request that access cache and found line in E or S-state.",
@@ -101,7 +101,7 @@
"EventName": "UNC_CBO_CACHE_LOOKUP.WRITE_ES",
"PerPkg": "1",
"UMask": "0x26",
- "Unit": "CBO"
+ "Unit": "CBOX"
},
{
"BriefDescription": "L3 Lookup write request that access cache and found line in I-state.",
@@ -109,7 +109,7 @@
"EventName": "UNC_CBO_CACHE_LOOKUP.WRITE_I",
"PerPkg": "1",
"UMask": "0x28",
- "Unit": "CBO"
+ "Unit": "CBOX"
},
{
"BriefDescription": "L3 Lookup write request that access cache and found line in M-state.",
@@ -117,7 +117,7 @@
"EventName": "UNC_CBO_CACHE_LOOKUP.WRITE_M",
"PerPkg": "1",
"UMask": "0x21",
- "Unit": "CBO"
+ "Unit": "CBOX"
},
{
"BriefDescription": "L3 Lookup write request that access cache and found line in MESI-state.",
@@ -125,7 +125,7 @@
"EventName": "UNC_CBO_CACHE_LOOKUP.WRITE_MESI",
"PerPkg": "1",
"UMask": "0x2f",
- "Unit": "CBO"
+ "Unit": "CBOX"
},
{
"BriefDescription": "A cross-core snoop resulted from L3 Eviction which hits a modified line in some processor core.",
@@ -133,7 +133,7 @@
"EventName": "UNC_CBO_XSNP_RESPONSE.HITM_EVICTION",
"PerPkg": "1",
"UMask": "0x88",
- "Unit": "CBO"
+ "Unit": "CBOX"
},
{
"BriefDescription": "An external snoop hits a modified line in some processor core.",
@@ -141,7 +141,7 @@
"EventName": "UNC_CBO_XSNP_RESPONSE.HITM_EXTERNAL",
"PerPkg": "1",
"UMask": "0x28",
- "Unit": "CBO"
+ "Unit": "CBOX"
},
{
"BriefDescription": "A cross-core snoop initiated by this Cbox due to processor core memory request which hits a modified line in some processor core.",
@@ -149,7 +149,7 @@
"EventName": "UNC_CBO_XSNP_RESPONSE.HITM_XCORE",
"PerPkg": "1",
"UMask": "0x48",
- "Unit": "CBO"
+ "Unit": "CBOX"
},
{
"BriefDescription": "A cross-core snoop resulted from L3 Eviction which hits a non-modified line in some processor core.",
@@ -157,7 +157,7 @@
"EventName": "UNC_CBO_XSNP_RESPONSE.HIT_EVICTION",
"PerPkg": "1",
"UMask": "0x84",
- "Unit": "CBO"
+ "Unit": "CBOX"
},
{
"BriefDescription": "An external snoop hits a non-modified line in some processor core.",
@@ -165,7 +165,7 @@
"EventName": "UNC_CBO_XSNP_RESPONSE.HIT_EXTERNAL",
"PerPkg": "1",
"UMask": "0x24",
- "Unit": "CBO"
+ "Unit": "CBOX"
},
{
"BriefDescription": "A cross-core snoop initiated by this Cbox due to processor core memory request which hits a non-modified line in some processor core.",
@@ -173,7 +173,7 @@
"EventName": "UNC_CBO_XSNP_RESPONSE.HIT_XCORE",
"PerPkg": "1",
"UMask": "0x44",
- "Unit": "CBO"
+ "Unit": "CBOX"
},
{
"BriefDescription": "A cross-core snoop resulted from L3 Eviction which misses in some processor core.",
@@ -181,7 +181,7 @@
"EventName": "UNC_CBO_XSNP_RESPONSE.MISS_EVICTION",
"PerPkg": "1",
"UMask": "0x81",
- "Unit": "CBO"
+ "Unit": "CBOX"
},
{
"BriefDescription": "An external snoop misses in some processor core.",
@@ -189,7 +189,7 @@
"EventName": "UNC_CBO_XSNP_RESPONSE.MISS_EXTERNAL",
"PerPkg": "1",
"UMask": "0x21",
- "Unit": "CBO"
+ "Unit": "CBOX"
},
{
"BriefDescription": "A cross-core snoop initiated by this Cbox due to processor core memory request which misses in some processor core.",
@@ -197,6 +197,6 @@
"EventName": "UNC_CBO_XSNP_RESPONSE.MISS_XCORE",
"PerPkg": "1",
"UMask": "0x41",
- "Unit": "CBO"
+ "Unit": "CBOX"
}
]
diff --git a/tools/perf/pmu-events/arch/x86/haswell/uncore-interconnect.json b/tools/perf/pmu-events/arch/x86/haswell/uncore-interconnect.json
new file mode 100644
index 000000000000..8da28239ebf9
--- /dev/null
+++ b/tools/perf/pmu-events/arch/x86/haswell/uncore-interconnect.json
@@ -0,0 +1,52 @@
+[
+ {
+ "BriefDescription": "Each cycle count number of valid entries in Coherency Tracker queue from allocation till deallocation. Aperture requests (snoops) appear as NC decoded internally and become coherent (snoop L3, access memory)",
+ "EventCode": "0x83",
+ "EventName": "UNC_ARB_COH_TRK_OCCUPANCY.All",
+ "PerPkg": "1",
+ "PublicDescription": "Each cycle count number of valid entries in Coherency Tracker queue from allocation till deallocation. Aperture requests (snoops) appear as NC decoded internally and become coherent (snoop L3, access memory).",
+ "UMask": "0x1",
+ "Unit": "ARB"
+ },
+ {
+ "BriefDescription": "Number of entries allocated. Account for Any type: e.g. Snoop, Core aperture, etc.",
+ "EventCode": "0x84",
+ "EventName": "UNC_ARB_COH_TRK_REQUESTS.ALL",
+ "PerPkg": "1",
+ "UMask": "0x1",
+ "Unit": "ARB"
+ },
+ {
+ "BriefDescription": "Each cycle counts number of all Core outgoing valid entries. Such entry is defined as valid from its allocation till first of IDI0 or DRS0 messages is sent out. Accounts for Coherent and non-coherent traffic.",
+ "EventCode": "0x80",
+ "EventName": "UNC_ARB_TRK_OCCUPANCY.ALL",
+ "PerPkg": "1",
+ "UMask": "0x1",
+ "Unit": "ARB"
+ },
+ {
+ "BriefDescription": "Cycles with at least one request outstanding is waiting for data return from memory controller. Account for coherent and non-coherent requests initiated by IA Cores, Processor Graphics Unit, or LLC.",
+ "CounterMask": "1",
+ "EventCode": "0x80",
+ "EventName": "UNC_ARB_TRK_OCCUPANCY.CYCLES_WITH_ANY_REQUEST",
+ "PerPkg": "1",
+ "UMask": "0x1",
+ "Unit": "ARB"
+ },
+ {
+ "BriefDescription": "Total number of Core outgoing entries allocated. Accounts for Coherent and non-coherent traffic.",
+ "EventCode": "0x81",
+ "EventName": "UNC_ARB_TRK_REQUESTS.ALL",
+ "PerPkg": "1",
+ "UMask": "0x1",
+ "Unit": "ARB"
+ },
+ {
+ "BriefDescription": "Number of Writes allocated - any write transactions: full/partials writes and evictions.",
+ "EventCode": "0x81",
+ "EventName": "UNC_ARB_TRK_REQUESTS.WRITES",
+ "PerPkg": "1",
+ "UMask": "0x20",
+ "Unit": "ARB"
+ }
+]
diff --git a/tools/perf/pmu-events/arch/x86/haswell/uncore-other.json b/tools/perf/pmu-events/arch/x86/haswell/uncore-other.json
index 84cc2536de69..2af92e43b28a 100644
--- a/tools/perf/pmu-events/arch/x86/haswell/uncore-other.json
+++ b/tools/perf/pmu-events/arch/x86/haswell/uncore-other.json
@@ -1,54 +1,4 @@
[
- {
- "BriefDescription": "Each cycle count number of valid entries in Coherency Tracker queue from allocation till deallocation. Aperture requests (snoops) appear as NC decoded internally and become coherent (snoop L3, access memory)",
- "EventCode": "0x83",
- "EventName": "UNC_ARB_COH_TRK_OCCUPANCY.All",
- "PerPkg": "1",
- "PublicDescription": "Each cycle count number of valid entries in Coherency Tracker queue from allocation till deallocation. Aperture requests (snoops) appear as NC decoded internally and become coherent (snoop L3, access memory).",
- "UMask": "0x1",
- "Unit": "ARB"
- },
- {
- "BriefDescription": "Number of entries allocated. Account for Any type: e.g. Snoop, Core aperture, etc.",
- "EventCode": "0x84",
- "EventName": "UNC_ARB_COH_TRK_REQUESTS.ALL",
- "PerPkg": "1",
- "UMask": "0x1",
- "Unit": "ARB"
- },
- {
- "BriefDescription": "Each cycle counts number of all Core outgoing valid entries. Such entry is defined as valid from its allocation till first of IDI0 or DRS0 messages is sent out. Accounts for Coherent and non-coherent traffic.",
- "EventCode": "0x80",
- "EventName": "UNC_ARB_TRK_OCCUPANCY.ALL",
- "PerPkg": "1",
- "UMask": "0x1",
- "Unit": "ARB"
- },
- {
- "BriefDescription": "Cycles with at least one request outstanding is waiting for data return from memory controller. Account for coherent and non-coherent requests initiated by IA Cores, Processor Graphics Unit, or LLC.",
- "CounterMask": "1",
- "EventCode": "0x80",
- "EventName": "UNC_ARB_TRK_OCCUPANCY.CYCLES_WITH_ANY_REQUEST",
- "PerPkg": "1",
- "UMask": "0x1",
- "Unit": "ARB"
- },
- {
- "BriefDescription": "Total number of Core outgoing entries allocated. Accounts for Coherent and non-coherent traffic.",
- "EventCode": "0x81",
- "EventName": "UNC_ARB_TRK_REQUESTS.ALL",
- "PerPkg": "1",
- "UMask": "0x1",
- "Unit": "ARB"
- },
- {
- "BriefDescription": "Number of Writes allocated - any write transactions: full/partials writes and evictions.",
- "EventCode": "0x81",
- "EventName": "UNC_ARB_TRK_REQUESTS.WRITES",
- "PerPkg": "1",
- "UMask": "0x20",
- "Unit": "ARB"
- },
{
"BriefDescription": "This 48-bit fixed counter counts the UCLK cycles.",
"EventCode": "0xff",
--
2.40.0.577.gac1e443424-goog
^ permalink raw reply related [flat|nested] 18+ messages in thread* [PATCH v3 11/21] perf vendor events intel: Fix uncore topics for icelake
2023-04-13 13:29 [PATCH v3 00/21] Update uncore topics, 1x event updates, 2x new archs Ian Rogers
` (4 preceding siblings ...)
2023-04-13 13:29 ` [PATCH v3 09/21] perf vendor events intel: Fix uncore topics for haswell Ian Rogers
@ 2023-04-13 13:29 ` Ian Rogers
2023-04-13 13:29 ` [PATCH v3 13/21] perf vendor events intel: Fix uncore topics for ivybridge Ian Rogers
` (6 subsequent siblings)
12 siblings, 0 replies; 18+ messages in thread
From: Ian Rogers @ 2023-04-13 13:29 UTC (permalink / raw)
To: Peter Zijlstra, Ingo Molnar, Arnaldo Carvalho de Melo,
Mark Rutland, Alexander Shishkin, Jiri Olsa, Namhyung Kim,
Zhengjun Xing, Kan Liang, linux-perf-users, linux-kernel,
Edward Baker, Perry Taylor, Caleb Biggers
Cc: Stephane Eranian, Ian Rogers
Move events from 'uncore-other' topic classification to interconnect.
Signed-off-by: Ian Rogers <irogers@google.com>
---
.../arch/x86/icelake/uncore-interconnect.json | 74 +++++++++++++++++++
.../arch/x86/icelake/uncore-other.json | 72 ------------------
2 files changed, 74 insertions(+), 72 deletions(-)
create mode 100644 tools/perf/pmu-events/arch/x86/icelake/uncore-interconnect.json
diff --git a/tools/perf/pmu-events/arch/x86/icelake/uncore-interconnect.json b/tools/perf/pmu-events/arch/x86/icelake/uncore-interconnect.json
new file mode 100644
index 000000000000..8027590f1776
--- /dev/null
+++ b/tools/perf/pmu-events/arch/x86/icelake/uncore-interconnect.json
@@ -0,0 +1,74 @@
+[
+ {
+ "BriefDescription": "Number of entries allocated. Account for Any type: e.g. Snoop, etc.",
+ "EventCode": "0x84",
+ "EventName": "UNC_ARB_COH_TRK_REQUESTS.ALL",
+ "PerPkg": "1",
+ "UMask": "0x1",
+ "Unit": "ARB"
+ },
+ {
+ "BriefDescription": "Each cycle counts number of any coherent request at memory controller that were issued by any core. This event is not supported on ICL products but is supported on RKL products.",
+ "EventCode": "0x85",
+ "EventName": "UNC_ARB_DAT_OCCUPANCY.ALL",
+ "PerPkg": "1",
+ "UMask": "0x1",
+ "Unit": "ARB"
+ },
+ {
+ "BriefDescription": "Each cycle counts number of coherent reads pending on data return from memory controller that were issued by any core. This event is not supported on ICL products but is supported on RKL products.",
+ "EventCode": "0x85",
+ "EventName": "UNC_ARB_DAT_OCCUPANCY.RD",
+ "PerPkg": "1",
+ "UMask": "0x2",
+ "Unit": "ARB"
+ },
+ {
+ "BriefDescription": "Each cycle count number of 'valid' coherent Data Read entries . Such entry is defined as valid when it is allocated till deallocation. Doesn't include prefetches. This event is not supported on ICL products but is supported on RKL products.",
+ "EventCode": "0x80",
+ "EventName": "UNC_ARB_REQ_TRK_OCCUPANCY.DRD",
+ "PerPkg": "1",
+ "UMask": "0x2",
+ "Unit": "ARB"
+ },
+ {
+ "BriefDescription": "Number of all coherent Data Read entries. Doesn't include prefetches",
+ "EventCode": "0x81",
+ "EventName": "UNC_ARB_REQ_TRK_REQUEST.DRD",
+ "PerPkg": "1",
+ "UMask": "0x2",
+ "Unit": "ARB"
+ },
+ {
+ "BriefDescription": "Each cycle counts number of all outgoing valid entries in ReqTrk. Such entry is defined as valid from its allocation in ReqTrk till deallocation. Accounts for Coherent and non-coherent traffic. This event is not supported on ICL products but is supported on RKL products.",
+ "EventCode": "0x80",
+ "EventName": "UNC_ARB_TRK_OCCUPANCY.ALL",
+ "PerPkg": "1",
+ "UMask": "0x1",
+ "Unit": "ARB"
+ },
+ {
+ "BriefDescription": "Each cycle count number of 'valid' coherent Data Read entries . Such entry is defined as valid when it is allocated till deallocation. Doesn't include prefetches. This event is not supported on ICL products but is supported on RKL products.",
+ "EventCode": "0x80",
+ "EventName": "UNC_ARB_TRK_OCCUPANCY.RD",
+ "PerPkg": "1",
+ "UMask": "0x2",
+ "Unit": "ARB"
+ },
+ {
+ "BriefDescription": "Total number of all outgoing entries allocated. Accounts for Coherent and non-coherent traffic.",
+ "EventCode": "0x81",
+ "EventName": "UNC_ARB_TRK_REQUESTS.ALL",
+ "PerPkg": "1",
+ "UMask": "0x1",
+ "Unit": "ARB"
+ },
+ {
+ "BriefDescription": "Number of all coherent Data Read entries. Doesn't include prefetches. This event is not supported on ICL products but is supported on RKL products.",
+ "EventCode": "0x81",
+ "EventName": "UNC_ARB_TRK_REQUESTS.RD",
+ "PerPkg": "1",
+ "UMask": "0x2",
+ "Unit": "ARB"
+ }
+]
diff --git a/tools/perf/pmu-events/arch/x86/icelake/uncore-other.json b/tools/perf/pmu-events/arch/x86/icelake/uncore-other.json
index b27d95b2c857..c6596ba09195 100644
--- a/tools/perf/pmu-events/arch/x86/icelake/uncore-other.json
+++ b/tools/perf/pmu-events/arch/x86/icelake/uncore-other.json
@@ -1,76 +1,4 @@
[
- {
- "BriefDescription": "Number of entries allocated. Account for Any type: e.g. Snoop, etc.",
- "EventCode": "0x84",
- "EventName": "UNC_ARB_COH_TRK_REQUESTS.ALL",
- "PerPkg": "1",
- "UMask": "0x1",
- "Unit": "ARB"
- },
- {
- "BriefDescription": "Each cycle counts number of any coherent request at memory controller that were issued by any core. This event is not supported on ICL products but is supported on RKL products.",
- "EventCode": "0x85",
- "EventName": "UNC_ARB_DAT_OCCUPANCY.ALL",
- "PerPkg": "1",
- "UMask": "0x1",
- "Unit": "ARB"
- },
- {
- "BriefDescription": "Each cycle counts number of coherent reads pending on data return from memory controller that were issued by any core. This event is not supported on ICL products but is supported on RKL products.",
- "EventCode": "0x85",
- "EventName": "UNC_ARB_DAT_OCCUPANCY.RD",
- "PerPkg": "1",
- "UMask": "0x2",
- "Unit": "ARB"
- },
- {
- "BriefDescription": "Each cycle count number of 'valid' coherent Data Read entries . Such entry is defined as valid when it is allocated till deallocation. Doesn't include prefetches. This event is not supported on ICL products but is supported on RKL products.",
- "EventCode": "0x80",
- "EventName": "UNC_ARB_REQ_TRK_OCCUPANCY.DRD",
- "PerPkg": "1",
- "UMask": "0x2",
- "Unit": "ARB"
- },
- {
- "BriefDescription": "Number of all coherent Data Read entries. Doesn't include prefetches",
- "EventCode": "0x81",
- "EventName": "UNC_ARB_REQ_TRK_REQUEST.DRD",
- "PerPkg": "1",
- "UMask": "0x2",
- "Unit": "ARB"
- },
- {
- "BriefDescription": "Each cycle counts number of all outgoing valid entries in ReqTrk. Such entry is defined as valid from its allocation in ReqTrk till deallocation. Accounts for Coherent and non-coherent traffic. This event is not supported on ICL products but is supported on RKL products.",
- "EventCode": "0x80",
- "EventName": "UNC_ARB_TRK_OCCUPANCY.ALL",
- "PerPkg": "1",
- "UMask": "0x1",
- "Unit": "ARB"
- },
- {
- "BriefDescription": "Each cycle count number of 'valid' coherent Data Read entries . Such entry is defined as valid when it is allocated till deallocation. Doesn't include prefetches. This event is not supported on ICL products but is supported on RKL products.",
- "EventCode": "0x80",
- "EventName": "UNC_ARB_TRK_OCCUPANCY.RD",
- "PerPkg": "1",
- "UMask": "0x2",
- "Unit": "ARB"
- },
- {
- "BriefDescription": "Total number of all outgoing entries allocated. Accounts for Coherent and non-coherent traffic.",
- "EventCode": "0x81",
- "EventName": "UNC_ARB_TRK_REQUESTS.ALL",
- "PerPkg": "1",
- "UMask": "0x1",
- "Unit": "ARB"
- },
- {
- "BriefDescription": "Number of all coherent Data Read entries. Doesn't include prefetches. This event is not supported on ICL products but is supported on RKL products.",
- "EventCode": "0x81",
- "EventName": "UNC_ARB_TRK_REQUESTS.RD",
- "PerPkg": "1",
- "UMask": "0x2",
- "Unit": "ARB"
- },
{
"BriefDescription": "UNC_CLOCK.SOCKET",
"EventCode": "0xff",
--
2.40.0.577.gac1e443424-goog
^ permalink raw reply related [flat|nested] 18+ messages in thread* [PATCH v3 13/21] perf vendor events intel: Fix uncore topics for ivybridge
2023-04-13 13:29 [PATCH v3 00/21] Update uncore topics, 1x event updates, 2x new archs Ian Rogers
` (5 preceding siblings ...)
2023-04-13 13:29 ` [PATCH v3 11/21] perf vendor events intel: Fix uncore topics for icelake Ian Rogers
@ 2023-04-13 13:29 ` Ian Rogers
2023-04-13 13:29 ` [PATCH v3 16/21] perf vendor events intel: Fix uncore topics for knightslanding Ian Rogers
` (5 subsequent siblings)
12 siblings, 0 replies; 18+ messages in thread
From: Ian Rogers @ 2023-04-13 13:29 UTC (permalink / raw)
To: Peter Zijlstra, Ingo Molnar, Arnaldo Carvalho de Melo,
Mark Rutland, Alexander Shishkin, Jiri Olsa, Namhyung Kim,
Zhengjun Xing, Kan Liang, linux-perf-users, linux-kernel,
Edward Baker, Perry Taylor, Caleb Biggers
Cc: Stephane Eranian, Ian Rogers
Remove 'uncore-other' topic classification, move to cache and
interconnect.
Signed-off-by: Ian Rogers <irogers@google.com>
---
.../arch/x86/ivybridge/uncore-cache.json | 50 +++++++++----------
...re-other.json => uncore-interconnect.json} | 0
2 files changed, 25 insertions(+), 25 deletions(-)
rename tools/perf/pmu-events/arch/x86/ivybridge/{uncore-other.json => uncore-interconnect.json} (100%)
diff --git a/tools/perf/pmu-events/arch/x86/ivybridge/uncore-cache.json b/tools/perf/pmu-events/arch/x86/ivybridge/uncore-cache.json
index c538557ba4c0..be9a3ed1a940 100644
--- a/tools/perf/pmu-events/arch/x86/ivybridge/uncore-cache.json
+++ b/tools/perf/pmu-events/arch/x86/ivybridge/uncore-cache.json
@@ -5,7 +5,7 @@
"EventName": "UNC_CBO_CACHE_LOOKUP.ANY_ES",
"PerPkg": "1",
"UMask": "0x86",
- "Unit": "CBO"
+ "Unit": "CBOX"
},
{
"BriefDescription": "L3 Lookup any request that access cache and found line in I-state.",
@@ -13,7 +13,7 @@
"EventName": "UNC_CBO_CACHE_LOOKUP.ANY_I",
"PerPkg": "1",
"UMask": "0x88",
- "Unit": "CBO"
+ "Unit": "CBOX"
},
{
"BriefDescription": "L3 Lookup any request that access cache and found line in M-state.",
@@ -21,7 +21,7 @@
"EventName": "UNC_CBO_CACHE_LOOKUP.ANY_M",
"PerPkg": "1",
"UMask": "0x81",
- "Unit": "CBO"
+ "Unit": "CBOX"
},
{
"BriefDescription": "L3 Lookup any request that access cache and found line in MESI-state.",
@@ -29,7 +29,7 @@
"EventName": "UNC_CBO_CACHE_LOOKUP.ANY_MESI",
"PerPkg": "1",
"UMask": "0x8f",
- "Unit": "CBO"
+ "Unit": "CBOX"
},
{
"BriefDescription": "L3 Lookup external snoop request that access cache and found line in E or S-state.",
@@ -37,7 +37,7 @@
"EventName": "UNC_CBO_CACHE_LOOKUP.EXTSNP_ES",
"PerPkg": "1",
"UMask": "0x46",
- "Unit": "CBO"
+ "Unit": "CBOX"
},
{
"BriefDescription": "L3 Lookup external snoop request that access cache and found line in I-state.",
@@ -45,7 +45,7 @@
"EventName": "UNC_CBO_CACHE_LOOKUP.EXTSNP_I",
"PerPkg": "1",
"UMask": "0x48",
- "Unit": "CBO"
+ "Unit": "CBOX"
},
{
"BriefDescription": "L3 Lookup external snoop request that access cache and found line in M-state.",
@@ -53,7 +53,7 @@
"EventName": "UNC_CBO_CACHE_LOOKUP.EXTSNP_M",
"PerPkg": "1",
"UMask": "0x41",
- "Unit": "CBO"
+ "Unit": "CBOX"
},
{
"BriefDescription": "L3 Lookup external snoop request that access cache and found line in MESI-state.",
@@ -61,7 +61,7 @@
"EventName": "UNC_CBO_CACHE_LOOKUP.EXTSNP_MESI",
"PerPkg": "1",
"UMask": "0x4f",
- "Unit": "CBO"
+ "Unit": "CBOX"
},
{
"BriefDescription": "L3 Lookup read request that access cache and found line in E or S-state.",
@@ -69,7 +69,7 @@
"EventName": "UNC_CBO_CACHE_LOOKUP.READ_ES",
"PerPkg": "1",
"UMask": "0x16",
- "Unit": "CBO"
+ "Unit": "CBOX"
},
{
"BriefDescription": "L3 Lookup read request that access cache and found line in I-state.",
@@ -77,7 +77,7 @@
"EventName": "UNC_CBO_CACHE_LOOKUP.READ_I",
"PerPkg": "1",
"UMask": "0x18",
- "Unit": "CBO"
+ "Unit": "CBOX"
},
{
"BriefDescription": "L3 Lookup read request that access cache and found line in M-state.",
@@ -85,7 +85,7 @@
"EventName": "UNC_CBO_CACHE_LOOKUP.READ_M",
"PerPkg": "1",
"UMask": "0x11",
- "Unit": "CBO"
+ "Unit": "CBOX"
},
{
"BriefDescription": "L3 Lookup read request that access cache and found line in any MESI-state.",
@@ -93,7 +93,7 @@
"EventName": "UNC_CBO_CACHE_LOOKUP.READ_MESI",
"PerPkg": "1",
"UMask": "0x1f",
- "Unit": "CBO"
+ "Unit": "CBOX"
},
{
"BriefDescription": "L3 Lookup write request that access cache and found line in E or S-state.",
@@ -101,7 +101,7 @@
"EventName": "UNC_CBO_CACHE_LOOKUP.WRITE_ES",
"PerPkg": "1",
"UMask": "0x26",
- "Unit": "CBO"
+ "Unit": "CBOX"
},
{
"BriefDescription": "L3 Lookup write request that access cache and found line in I-state.",
@@ -109,7 +109,7 @@
"EventName": "UNC_CBO_CACHE_LOOKUP.WRITE_I",
"PerPkg": "1",
"UMask": "0x28",
- "Unit": "CBO"
+ "Unit": "CBOX"
},
{
"BriefDescription": "L3 Lookup write request that access cache and found line in M-state.",
@@ -117,7 +117,7 @@
"EventName": "UNC_CBO_CACHE_LOOKUP.WRITE_M",
"PerPkg": "1",
"UMask": "0x21",
- "Unit": "CBO"
+ "Unit": "CBOX"
},
{
"BriefDescription": "L3 Lookup write request that access cache and found line in MESI-state.",
@@ -125,7 +125,7 @@
"EventName": "UNC_CBO_CACHE_LOOKUP.WRITE_MESI",
"PerPkg": "1",
"UMask": "0x2f",
- "Unit": "CBO"
+ "Unit": "CBOX"
},
{
"BriefDescription": "A cross-core snoop resulted from L3 Eviction which hits a modified line in some processor core.",
@@ -133,7 +133,7 @@
"EventName": "UNC_CBO_XSNP_RESPONSE.HITM_EVICTION",
"PerPkg": "1",
"UMask": "0x88",
- "Unit": "CBO"
+ "Unit": "CBOX"
},
{
"BriefDescription": "An external snoop hits a modified line in some processor core.",
@@ -141,7 +141,7 @@
"EventName": "UNC_CBO_XSNP_RESPONSE.HITM_EXTERNAL",
"PerPkg": "1",
"UMask": "0x28",
- "Unit": "CBO"
+ "Unit": "CBOX"
},
{
"BriefDescription": "A cross-core snoop initiated by this Cbox due to processor core memory request which hits a modified line in some processor core.",
@@ -149,7 +149,7 @@
"EventName": "UNC_CBO_XSNP_RESPONSE.HITM_XCORE",
"PerPkg": "1",
"UMask": "0x48",
- "Unit": "CBO"
+ "Unit": "CBOX"
},
{
"BriefDescription": "A cross-core snoop resulted from L3 Eviction which hits a non-modified line in some processor core.",
@@ -157,7 +157,7 @@
"EventName": "UNC_CBO_XSNP_RESPONSE.HIT_EVICTION",
"PerPkg": "1",
"UMask": "0x84",
- "Unit": "CBO"
+ "Unit": "CBOX"
},
{
"BriefDescription": "An external snoop hits a non-modified line in some processor core.",
@@ -165,7 +165,7 @@
"EventName": "UNC_CBO_XSNP_RESPONSE.HIT_EXTERNAL",
"PerPkg": "1",
"UMask": "0x24",
- "Unit": "CBO"
+ "Unit": "CBOX"
},
{
"BriefDescription": "A cross-core snoop initiated by this Cbox due to processor core memory request which hits a non-modified line in some processor core.",
@@ -173,7 +173,7 @@
"EventName": "UNC_CBO_XSNP_RESPONSE.HIT_XCORE",
"PerPkg": "1",
"UMask": "0x44",
- "Unit": "CBO"
+ "Unit": "CBOX"
},
{
"BriefDescription": "A cross-core snoop resulted from L3 Eviction which misses in some processor core.",
@@ -181,7 +181,7 @@
"EventName": "UNC_CBO_XSNP_RESPONSE.MISS_EVICTION",
"PerPkg": "1",
"UMask": "0x81",
- "Unit": "CBO"
+ "Unit": "CBOX"
},
{
"BriefDescription": "An external snoop misses in some processor core.",
@@ -189,7 +189,7 @@
"EventName": "UNC_CBO_XSNP_RESPONSE.MISS_EXTERNAL",
"PerPkg": "1",
"UMask": "0x21",
- "Unit": "CBO"
+ "Unit": "CBOX"
},
{
"BriefDescription": "A cross-core snoop initiated by this Cbox due to processor core memory request which misses in some processor core.",
@@ -197,6 +197,6 @@
"EventName": "UNC_CBO_XSNP_RESPONSE.MISS_XCORE",
"PerPkg": "1",
"UMask": "0x41",
- "Unit": "CBO"
+ "Unit": "CBOX"
}
]
diff --git a/tools/perf/pmu-events/arch/x86/ivybridge/uncore-other.json b/tools/perf/pmu-events/arch/x86/ivybridge/uncore-interconnect.json
similarity index 100%
rename from tools/perf/pmu-events/arch/x86/ivybridge/uncore-other.json
rename to tools/perf/pmu-events/arch/x86/ivybridge/uncore-interconnect.json
--
2.40.0.577.gac1e443424-goog
^ permalink raw reply related [flat|nested] 18+ messages in thread* [PATCH v3 16/21] perf vendor events intel: Fix uncore topics for knightslanding
2023-04-13 13:29 [PATCH v3 00/21] Update uncore topics, 1x event updates, 2x new archs Ian Rogers
` (6 preceding siblings ...)
2023-04-13 13:29 ` [PATCH v3 13/21] perf vendor events intel: Fix uncore topics for ivybridge Ian Rogers
@ 2023-04-13 13:29 ` Ian Rogers
2023-04-13 13:29 ` [PATCH v3 17/21] perf vendor events intel: Fix uncore topics for sandybridge Ian Rogers
` (4 subsequent siblings)
12 siblings, 0 replies; 18+ messages in thread
From: Ian Rogers @ 2023-04-13 13:29 UTC (permalink / raw)
To: Peter Zijlstra, Ingo Molnar, Arnaldo Carvalho de Melo,
Mark Rutland, Alexander Shishkin, Jiri Olsa, Namhyung Kim,
Zhengjun Xing, Kan Liang, linux-perf-users, linux-kernel,
Edward Baker, Perry Taylor, Caleb Biggers
Cc: Stephane Eranian, Ian Rogers
Remove 'uncore-other' topic classification, move to cache, io and
memory.
Signed-off-by: Ian Rogers <irogers@google.com>
---
.../{uncore-other.json => uncore-cache.json} | 260 ------------------
.../arch/x86/knightslanding/uncore-io.json | 194 +++++++++++++
.../x86/knightslanding/uncore-memory.json | 68 +++++
3 files changed, 262 insertions(+), 260 deletions(-)
rename tools/perf/pmu-events/arch/x86/knightslanding/{uncore-other.json => uncore-cache.json} (91%)
create mode 100644 tools/perf/pmu-events/arch/x86/knightslanding/uncore-io.json
diff --git a/tools/perf/pmu-events/arch/x86/knightslanding/uncore-other.json b/tools/perf/pmu-events/arch/x86/knightslanding/uncore-cache.json
similarity index 91%
rename from tools/perf/pmu-events/arch/x86/knightslanding/uncore-other.json
rename to tools/perf/pmu-events/arch/x86/knightslanding/uncore-cache.json
index fc85e0c95318..1b8dcfa5461c 100644
--- a/tools/perf/pmu-events/arch/x86/knightslanding/uncore-other.json
+++ b/tools/perf/pmu-events/arch/x86/knightslanding/uncore-cache.json
@@ -55,74 +55,6 @@
"UMask": "0x24",
"Unit": "CHA"
},
- {
- "BriefDescription": "Counts the number of read requests and streaming stores that hit in MCDRAM cache and the data in MCDRAM is clean with respect to DDR. This event is only valid in cache and hybrid memory mode.",
- "EventCode": "0x02",
- "EventName": "UNC_E_EDC_ACCESS.HIT_CLEAN",
- "PerPkg": "1",
- "UMask": "0x1",
- "Unit": "EDC_UCLK"
- },
- {
- "BriefDescription": "Counts the number of read requests and streaming stores that hit in MCDRAM cache and the data in MCDRAM is dirty with respect to DDR. This event is only valid in cache and hybrid memory mode.",
- "EventCode": "0x02",
- "EventName": "UNC_E_EDC_ACCESS.HIT_DIRTY",
- "PerPkg": "1",
- "UMask": "0x2",
- "Unit": "EDC_UCLK"
- },
- {
- "BriefDescription": "Counts the number of read requests and streaming stores that miss in MCDRAM cache and the data evicted from the MCDRAM is clean with respect to DDR. This event is only valid in cache and hybrid memory mode.",
- "EventCode": "0x02",
- "EventName": "UNC_E_EDC_ACCESS.MISS_CLEAN",
- "PerPkg": "1",
- "UMask": "0x4",
- "Unit": "EDC_UCLK"
- },
- {
- "BriefDescription": "Counts the number of read requests and streaming stores that miss in MCDRAM cache and the data evicted from the MCDRAM is dirty with respect to DDR. This event is only valid in cache and hybrid memory mode.",
- "EventCode": "0x02",
- "EventName": "UNC_E_EDC_ACCESS.MISS_DIRTY",
- "PerPkg": "1",
- "UMask": "0x8",
- "Unit": "EDC_UCLK"
- },
- {
- "BriefDescription": "Number of EDC Hits or Misses. Miss I",
- "EventCode": "0x02",
- "EventName": "UNC_E_EDC_ACCESS.MISS_INVALID",
- "PerPkg": "1",
- "UMask": "0x10",
- "Unit": "EDC_UCLK"
- },
- {
- "BriefDescription": "ECLK count",
- "EventName": "UNC_E_E_CLOCKTICKS",
- "PerPkg": "1",
- "Unit": "EDC_ECLK"
- },
- {
- "BriefDescription": "Counts the number of read requests received by the MCDRAM controller. This event is valid in all three memory modes: flat, cache and hybrid. In cache and hybrid memory mode, this event counts all read requests as well as streaming stores that hit or miss in the MCDRAM cache.",
- "EventCode": "0x01",
- "EventName": "UNC_E_RPQ_INSERTS",
- "PerPkg": "1",
- "UMask": "0x1",
- "Unit": "EDC_ECLK"
- },
- {
- "BriefDescription": "UCLK count",
- "EventName": "UNC_E_U_CLOCKTICKS",
- "PerPkg": "1",
- "Unit": "EDC_UCLK"
- },
- {
- "BriefDescription": "Counts the number of write requests received by the MCDRAM controller. This event is valid in all three memory modes: flat, cache and hybrid. In cache and hybrid memory mode, this event counts all streaming stores, writebacks and, read requests that miss in MCDRAM cache.",
- "EventCode": "0x02",
- "EventName": "UNC_E_WPQ_INSERTS",
- "PerPkg": "1",
- "UMask": "0x1",
- "Unit": "EDC_ECLK"
- },
{
"BriefDescription": "CMS Agent0 AD Credits Acquired For Transgress 0",
"EventCode": "0x80",
@@ -3429,197 +3361,5 @@
"PerPkg": "1",
"UMask": "0x1",
"Unit": "CHA"
- },
- {
- "BriefDescription": "Egress (to CMS) Cycles Full. Counts the number of cycles when the M2PCIe Egress is full. AD_0",
- "EventCode": "0x25",
- "EventName": "UNC_M2P_EGRESS_CYCLES_FULL.AD_0",
- "PerPkg": "1",
- "UMask": "0x1",
- "Unit": "M2PCIe"
- },
- {
- "BriefDescription": "Egress (to CMS) Cycles Full. Counts the number of cycles when the M2PCIe Egress is full. AD_1",
- "EventCode": "0x25",
- "EventName": "UNC_M2P_EGRESS_CYCLES_FULL.AD_1",
- "PerPkg": "1",
- "UMask": "0x8",
- "Unit": "M2PCIe"
- },
- {
- "BriefDescription": "Egress (to CMS) Cycles Full. Counts the number of cycles when the M2PCIe Egress is full. AK_0",
- "EventCode": "0x25",
- "EventName": "UNC_M2P_EGRESS_CYCLES_FULL.AK_0",
- "PerPkg": "1",
- "UMask": "0x2",
- "Unit": "M2PCIe"
- },
- {
- "BriefDescription": "Egress (to CMS) Cycles Full. Counts the number of cycles when the M2PCIe Egress is full. AK_1",
- "EventCode": "0x25",
- "EventName": "UNC_M2P_EGRESS_CYCLES_FULL.AK_1",
- "PerPkg": "1",
- "UMask": "0x10",
- "Unit": "M2PCIe"
- },
- {
- "BriefDescription": "Egress (to CMS) Cycles Full. Counts the number of cycles when the M2PCIe Egress is full. BL_0",
- "EventCode": "0x25",
- "EventName": "UNC_M2P_EGRESS_CYCLES_FULL.BL_0",
- "PerPkg": "1",
- "UMask": "0x4",
- "Unit": "M2PCIe"
- },
- {
- "BriefDescription": "Egress (to CMS) Cycles Full. Counts the number of cycles when the M2PCIe Egress is full. BL_1",
- "EventCode": "0x25",
- "EventName": "UNC_M2P_EGRESS_CYCLES_FULL.BL_1",
- "PerPkg": "1",
- "UMask": "0x20",
- "Unit": "M2PCIe"
- },
- {
- "BriefDescription": "Egress (to CMS) Cycles Not Empty. Counts the number of cycles when the M2PCIe Egress is not empty. AD_0",
- "EventCode": "0x23",
- "EventName": "UNC_M2P_EGRESS_CYCLES_NE.AD_0",
- "PerPkg": "1",
- "UMask": "0x1",
- "Unit": "M2PCIe"
- },
- {
- "BriefDescription": "Egress (to CMS) Cycles Not Empty. Counts the number of cycles when the M2PCIe Egress is not empty. AD_1",
- "EventCode": "0x23",
- "EventName": "UNC_M2P_EGRESS_CYCLES_NE.AD_1",
- "PerPkg": "1",
- "UMask": "0x8",
- "Unit": "M2PCIe"
- },
- {
- "BriefDescription": "Egress (to CMS) Cycles Not Empty. Counts the number of cycles when the M2PCIe Egress is not empty. AK_0",
- "EventCode": "0x23",
- "EventName": "UNC_M2P_EGRESS_CYCLES_NE.AK_0",
- "PerPkg": "1",
- "UMask": "0x2",
- "Unit": "M2PCIe"
- },
- {
- "BriefDescription": "Egress (to CMS) Cycles Not Empty. Counts the number of cycles when the M2PCIe Egress is not empty. AK_1",
- "EventCode": "0x23",
- "EventName": "UNC_M2P_EGRESS_CYCLES_NE.AK_1",
- "PerPkg": "1",
- "UMask": "0x10",
- "Unit": "M2PCIe"
- },
- {
- "BriefDescription": "Egress (to CMS) Cycles Not Empty. Counts the number of cycles when the M2PCIe Egress is not empty. BL_0",
- "EventCode": "0x23",
- "EventName": "UNC_M2P_EGRESS_CYCLES_NE.BL_0",
- "PerPkg": "1",
- "UMask": "0x4",
- "Unit": "M2PCIe"
- },
- {
- "BriefDescription": "Egress (to CMS) Cycles Not Empty. Counts the number of cycles when the M2PCIe Egress is not empty. BL_1",
- "EventCode": "0x23",
- "EventName": "UNC_M2P_EGRESS_CYCLES_NE.BL_1",
- "PerPkg": "1",
- "UMask": "0x20",
- "Unit": "M2PCIe"
- },
- {
- "BriefDescription": "Egress (to CMS) Ingress. Counts the number of number of messages inserted into the the M2PCIe Egress queue. AD_0",
- "EventCode": "0x24",
- "EventName": "UNC_M2P_EGRESS_INSERTS.AD_0",
- "PerPkg": "1",
- "UMask": "0x1",
- "Unit": "M2PCIe"
- },
- {
- "BriefDescription": "Egress (to CMS) Ingress. Counts the number of number of messages inserted into the the M2PCIe Egress queue. AD_1",
- "EventCode": "0x24",
- "EventName": "UNC_M2P_EGRESS_INSERTS.AD_1",
- "PerPkg": "1",
- "UMask": "0x10",
- "Unit": "M2PCIe"
- },
- {
- "BriefDescription": "Egress (to CMS) Ingress. Counts the number of number of messages inserted into the the M2PCIe Egress queue. AK_0",
- "EventCode": "0x24",
- "EventName": "UNC_M2P_EGRESS_INSERTS.AK_0",
- "PerPkg": "1",
- "UMask": "0x2",
- "Unit": "M2PCIe"
- },
- {
- "BriefDescription": "Egress (to CMS) Ingress. Counts the number of number of messages inserted into the the M2PCIe Egress queue. AK_1",
- "EventCode": "0x24",
- "EventName": "UNC_M2P_EGRESS_INSERTS.AK_1",
- "PerPkg": "1",
- "UMask": "0x20",
- "Unit": "M2PCIe"
- },
- {
- "BriefDescription": "Egress (to CMS) Ingress. Counts the number of number of messages inserted into the the M2PCIe Egress queue. AK_CRD_0",
- "EventCode": "0x24",
- "EventName": "UNC_M2P_EGRESS_INSERTS.AK_CRD_0",
- "PerPkg": "1",
- "UMask": "0x8",
- "Unit": "M2PCIe"
- },
- {
- "BriefDescription": "Egress (to CMS) Ingress. Counts the number of number of messages inserted into the the M2PCIe Egress queue. AK_CRD_1",
- "EventCode": "0x24",
- "EventName": "UNC_M2P_EGRESS_INSERTS.AK_CRD_1",
- "PerPkg": "1",
- "UMask": "0x80",
- "Unit": "M2PCIe"
- },
- {
- "BriefDescription": "Egress (to CMS) Ingress. Counts the number of number of messages inserted into the the M2PCIe Egress queue. BL_0",
- "EventCode": "0x24",
- "EventName": "UNC_M2P_EGRESS_INSERTS.BL_0",
- "PerPkg": "1",
- "UMask": "0x4",
- "Unit": "M2PCIe"
- },
- {
- "BriefDescription": "Egress (to CMS) Ingress. Counts the number of number of messages inserted into the the M2PCIe Egress queue. BL_1",
- "EventCode": "0x24",
- "EventName": "UNC_M2P_EGRESS_INSERTS.BL_1",
- "PerPkg": "1",
- "UMask": "0x40",
- "Unit": "M2PCIe"
- },
- {
- "BriefDescription": "Ingress Queue Cycles Not Empty. Counts the number of cycles when the M2PCIe Ingress is not empty.ALL",
- "EventCode": "0x10",
- "EventName": "UNC_M2P_INGRESS_CYCLES_NE.ALL",
- "PerPkg": "1",
- "UMask": "0x80",
- "Unit": "M2PCIe"
- },
- {
- "BriefDescription": "Ingress Queue Cycles Not Empty. Counts the number of cycles when the M2PCIe Ingress is not empty.CBO_IDI",
- "EventCode": "0x10",
- "EventName": "UNC_M2P_INGRESS_CYCLES_NE.CBO_IDI",
- "PerPkg": "1",
- "UMask": "0x1",
- "Unit": "M2PCIe"
- },
- {
- "BriefDescription": "Ingress Queue Cycles Not Empty. Counts the number of cycles when the M2PCIe Ingress is not empty.CBO_NCB",
- "EventCode": "0x10",
- "EventName": "UNC_M2P_INGRESS_CYCLES_NE.CBO_NCB",
- "PerPkg": "1",
- "UMask": "0x2",
- "Unit": "M2PCIe"
- },
- {
- "BriefDescription": "Ingress Queue Cycles Not Empty. Counts the number of cycles when the M2PCIe Ingress is not empty.CBO_NCS",
- "EventCode": "0x10",
- "EventName": "UNC_M2P_INGRESS_CYCLES_NE.CBO_NCS",
- "PerPkg": "1",
- "UMask": "0x4",
- "Unit": "M2PCIe"
}
]
diff --git a/tools/perf/pmu-events/arch/x86/knightslanding/uncore-io.json b/tools/perf/pmu-events/arch/x86/knightslanding/uncore-io.json
new file mode 100644
index 000000000000..898f7e425cd4
--- /dev/null
+++ b/tools/perf/pmu-events/arch/x86/knightslanding/uncore-io.json
@@ -0,0 +1,194 @@
+[
+ {
+ "BriefDescription": "Egress (to CMS) Cycles Full. Counts the number of cycles when the M2PCIe Egress is full. AD_0",
+ "EventCode": "0x25",
+ "EventName": "UNC_M2P_EGRESS_CYCLES_FULL.AD_0",
+ "PerPkg": "1",
+ "UMask": "0x1",
+ "Unit": "M2PCIe"
+ },
+ {
+ "BriefDescription": "Egress (to CMS) Cycles Full. Counts the number of cycles when the M2PCIe Egress is full. AD_1",
+ "EventCode": "0x25",
+ "EventName": "UNC_M2P_EGRESS_CYCLES_FULL.AD_1",
+ "PerPkg": "1",
+ "UMask": "0x8",
+ "Unit": "M2PCIe"
+ },
+ {
+ "BriefDescription": "Egress (to CMS) Cycles Full. Counts the number of cycles when the M2PCIe Egress is full. AK_0",
+ "EventCode": "0x25",
+ "EventName": "UNC_M2P_EGRESS_CYCLES_FULL.AK_0",
+ "PerPkg": "1",
+ "UMask": "0x2",
+ "Unit": "M2PCIe"
+ },
+ {
+ "BriefDescription": "Egress (to CMS) Cycles Full. Counts the number of cycles when the M2PCIe Egress is full. AK_1",
+ "EventCode": "0x25",
+ "EventName": "UNC_M2P_EGRESS_CYCLES_FULL.AK_1",
+ "PerPkg": "1",
+ "UMask": "0x10",
+ "Unit": "M2PCIe"
+ },
+ {
+ "BriefDescription": "Egress (to CMS) Cycles Full. Counts the number of cycles when the M2PCIe Egress is full. BL_0",
+ "EventCode": "0x25",
+ "EventName": "UNC_M2P_EGRESS_CYCLES_FULL.BL_0",
+ "PerPkg": "1",
+ "UMask": "0x4",
+ "Unit": "M2PCIe"
+ },
+ {
+ "BriefDescription": "Egress (to CMS) Cycles Full. Counts the number of cycles when the M2PCIe Egress is full. BL_1",
+ "EventCode": "0x25",
+ "EventName": "UNC_M2P_EGRESS_CYCLES_FULL.BL_1",
+ "PerPkg": "1",
+ "UMask": "0x20",
+ "Unit": "M2PCIe"
+ },
+ {
+ "BriefDescription": "Egress (to CMS) Cycles Not Empty. Counts the number of cycles when the M2PCIe Egress is not empty. AD_0",
+ "EventCode": "0x23",
+ "EventName": "UNC_M2P_EGRESS_CYCLES_NE.AD_0",
+ "PerPkg": "1",
+ "UMask": "0x1",
+ "Unit": "M2PCIe"
+ },
+ {
+ "BriefDescription": "Egress (to CMS) Cycles Not Empty. Counts the number of cycles when the M2PCIe Egress is not empty. AD_1",
+ "EventCode": "0x23",
+ "EventName": "UNC_M2P_EGRESS_CYCLES_NE.AD_1",
+ "PerPkg": "1",
+ "UMask": "0x8",
+ "Unit": "M2PCIe"
+ },
+ {
+ "BriefDescription": "Egress (to CMS) Cycles Not Empty. Counts the number of cycles when the M2PCIe Egress is not empty. AK_0",
+ "EventCode": "0x23",
+ "EventName": "UNC_M2P_EGRESS_CYCLES_NE.AK_0",
+ "PerPkg": "1",
+ "UMask": "0x2",
+ "Unit": "M2PCIe"
+ },
+ {
+ "BriefDescription": "Egress (to CMS) Cycles Not Empty. Counts the number of cycles when the M2PCIe Egress is not empty. AK_1",
+ "EventCode": "0x23",
+ "EventName": "UNC_M2P_EGRESS_CYCLES_NE.AK_1",
+ "PerPkg": "1",
+ "UMask": "0x10",
+ "Unit": "M2PCIe"
+ },
+ {
+ "BriefDescription": "Egress (to CMS) Cycles Not Empty. Counts the number of cycles when the M2PCIe Egress is not empty. BL_0",
+ "EventCode": "0x23",
+ "EventName": "UNC_M2P_EGRESS_CYCLES_NE.BL_0",
+ "PerPkg": "1",
+ "UMask": "0x4",
+ "Unit": "M2PCIe"
+ },
+ {
+ "BriefDescription": "Egress (to CMS) Cycles Not Empty. Counts the number of cycles when the M2PCIe Egress is not empty. BL_1",
+ "EventCode": "0x23",
+ "EventName": "UNC_M2P_EGRESS_CYCLES_NE.BL_1",
+ "PerPkg": "1",
+ "UMask": "0x20",
+ "Unit": "M2PCIe"
+ },
+ {
+ "BriefDescription": "Egress (to CMS) Ingress. Counts the number of number of messages inserted into the the M2PCIe Egress queue. AD_0",
+ "EventCode": "0x24",
+ "EventName": "UNC_M2P_EGRESS_INSERTS.AD_0",
+ "PerPkg": "1",
+ "UMask": "0x1",
+ "Unit": "M2PCIe"
+ },
+ {
+ "BriefDescription": "Egress (to CMS) Ingress. Counts the number of number of messages inserted into the the M2PCIe Egress queue. AD_1",
+ "EventCode": "0x24",
+ "EventName": "UNC_M2P_EGRESS_INSERTS.AD_1",
+ "PerPkg": "1",
+ "UMask": "0x10",
+ "Unit": "M2PCIe"
+ },
+ {
+ "BriefDescription": "Egress (to CMS) Ingress. Counts the number of number of messages inserted into the the M2PCIe Egress queue. AK_0",
+ "EventCode": "0x24",
+ "EventName": "UNC_M2P_EGRESS_INSERTS.AK_0",
+ "PerPkg": "1",
+ "UMask": "0x2",
+ "Unit": "M2PCIe"
+ },
+ {
+ "BriefDescription": "Egress (to CMS) Ingress. Counts the number of number of messages inserted into the the M2PCIe Egress queue. AK_1",
+ "EventCode": "0x24",
+ "EventName": "UNC_M2P_EGRESS_INSERTS.AK_1",
+ "PerPkg": "1",
+ "UMask": "0x20",
+ "Unit": "M2PCIe"
+ },
+ {
+ "BriefDescription": "Egress (to CMS) Ingress. Counts the number of number of messages inserted into the the M2PCIe Egress queue. AK_CRD_0",
+ "EventCode": "0x24",
+ "EventName": "UNC_M2P_EGRESS_INSERTS.AK_CRD_0",
+ "PerPkg": "1",
+ "UMask": "0x8",
+ "Unit": "M2PCIe"
+ },
+ {
+ "BriefDescription": "Egress (to CMS) Ingress. Counts the number of number of messages inserted into the the M2PCIe Egress queue. AK_CRD_1",
+ "EventCode": "0x24",
+ "EventName": "UNC_M2P_EGRESS_INSERTS.AK_CRD_1",
+ "PerPkg": "1",
+ "UMask": "0x80",
+ "Unit": "M2PCIe"
+ },
+ {
+ "BriefDescription": "Egress (to CMS) Ingress. Counts the number of number of messages inserted into the the M2PCIe Egress queue. BL_0",
+ "EventCode": "0x24",
+ "EventName": "UNC_M2P_EGRESS_INSERTS.BL_0",
+ "PerPkg": "1",
+ "UMask": "0x4",
+ "Unit": "M2PCIe"
+ },
+ {
+ "BriefDescription": "Egress (to CMS) Ingress. Counts the number of number of messages inserted into the the M2PCIe Egress queue. BL_1",
+ "EventCode": "0x24",
+ "EventName": "UNC_M2P_EGRESS_INSERTS.BL_1",
+ "PerPkg": "1",
+ "UMask": "0x40",
+ "Unit": "M2PCIe"
+ },
+ {
+ "BriefDescription": "Ingress Queue Cycles Not Empty. Counts the number of cycles when the M2PCIe Ingress is not empty.ALL",
+ "EventCode": "0x10",
+ "EventName": "UNC_M2P_INGRESS_CYCLES_NE.ALL",
+ "PerPkg": "1",
+ "UMask": "0x80",
+ "Unit": "M2PCIe"
+ },
+ {
+ "BriefDescription": "Ingress Queue Cycles Not Empty. Counts the number of cycles when the M2PCIe Ingress is not empty.CBO_IDI",
+ "EventCode": "0x10",
+ "EventName": "UNC_M2P_INGRESS_CYCLES_NE.CBO_IDI",
+ "PerPkg": "1",
+ "UMask": "0x1",
+ "Unit": "M2PCIe"
+ },
+ {
+ "BriefDescription": "Ingress Queue Cycles Not Empty. Counts the number of cycles when the M2PCIe Ingress is not empty.CBO_NCB",
+ "EventCode": "0x10",
+ "EventName": "UNC_M2P_INGRESS_CYCLES_NE.CBO_NCB",
+ "PerPkg": "1",
+ "UMask": "0x2",
+ "Unit": "M2PCIe"
+ },
+ {
+ "BriefDescription": "Ingress Queue Cycles Not Empty. Counts the number of cycles when the M2PCIe Ingress is not empty.CBO_NCS",
+ "EventCode": "0x10",
+ "EventName": "UNC_M2P_INGRESS_CYCLES_NE.CBO_NCS",
+ "PerPkg": "1",
+ "UMask": "0x4",
+ "Unit": "M2PCIe"
+ }
+]
diff --git a/tools/perf/pmu-events/arch/x86/knightslanding/uncore-memory.json b/tools/perf/pmu-events/arch/x86/knightslanding/uncore-memory.json
index 47da947b1a6e..fb752974179b 100644
--- a/tools/perf/pmu-events/arch/x86/knightslanding/uncore-memory.json
+++ b/tools/perf/pmu-events/arch/x86/knightslanding/uncore-memory.json
@@ -1,4 +1,72 @@
[
+ {
+ "BriefDescription": "Counts the number of read requests and streaming stores that hit in MCDRAM cache and the data in MCDRAM is clean with respect to DDR. This event is only valid in cache and hybrid memory mode.",
+ "EventCode": "0x02",
+ "EventName": "UNC_E_EDC_ACCESS.HIT_CLEAN",
+ "PerPkg": "1",
+ "UMask": "0x1",
+ "Unit": "EDC_UCLK"
+ },
+ {
+ "BriefDescription": "Counts the number of read requests and streaming stores that hit in MCDRAM cache and the data in MCDRAM is dirty with respect to DDR. This event is only valid in cache and hybrid memory mode.",
+ "EventCode": "0x02",
+ "EventName": "UNC_E_EDC_ACCESS.HIT_DIRTY",
+ "PerPkg": "1",
+ "UMask": "0x2",
+ "Unit": "EDC_UCLK"
+ },
+ {
+ "BriefDescription": "Counts the number of read requests and streaming stores that miss in MCDRAM cache and the data evicted from the MCDRAM is clean with respect to DDR. This event is only valid in cache and hybrid memory mode.",
+ "EventCode": "0x02",
+ "EventName": "UNC_E_EDC_ACCESS.MISS_CLEAN",
+ "PerPkg": "1",
+ "UMask": "0x4",
+ "Unit": "EDC_UCLK"
+ },
+ {
+ "BriefDescription": "Counts the number of read requests and streaming stores that miss in MCDRAM cache and the data evicted from the MCDRAM is dirty with respect to DDR. This event is only valid in cache and hybrid memory mode.",
+ "EventCode": "0x02",
+ "EventName": "UNC_E_EDC_ACCESS.MISS_DIRTY",
+ "PerPkg": "1",
+ "UMask": "0x8",
+ "Unit": "EDC_UCLK"
+ },
+ {
+ "BriefDescription": "Number of EDC Hits or Misses. Miss I",
+ "EventCode": "0x02",
+ "EventName": "UNC_E_EDC_ACCESS.MISS_INVALID",
+ "PerPkg": "1",
+ "UMask": "0x10",
+ "Unit": "EDC_UCLK"
+ },
+ {
+ "BriefDescription": "ECLK count",
+ "EventName": "UNC_E_E_CLOCKTICKS",
+ "PerPkg": "1",
+ "Unit": "EDC_ECLK"
+ },
+ {
+ "BriefDescription": "Counts the number of read requests received by the MCDRAM controller. This event is valid in all three memory modes: flat, cache and hybrid. In cache and hybrid memory mode, this event counts all read requests as well as streaming stores that hit or miss in the MCDRAM cache.",
+ "EventCode": "0x01",
+ "EventName": "UNC_E_RPQ_INSERTS",
+ "PerPkg": "1",
+ "UMask": "0x1",
+ "Unit": "EDC_ECLK"
+ },
+ {
+ "BriefDescription": "UCLK count",
+ "EventName": "UNC_E_U_CLOCKTICKS",
+ "PerPkg": "1",
+ "Unit": "EDC_UCLK"
+ },
+ {
+ "BriefDescription": "Counts the number of write requests received by the MCDRAM controller. This event is valid in all three memory modes: flat, cache and hybrid. In cache and hybrid memory mode, this event counts all streaming stores, writebacks and, read requests that miss in MCDRAM cache.",
+ "EventCode": "0x02",
+ "EventName": "UNC_E_WPQ_INSERTS",
+ "PerPkg": "1",
+ "UMask": "0x1",
+ "Unit": "EDC_ECLK"
+ },
{
"BriefDescription": "CAS All",
"EventCode": "0x03",
--
2.40.0.577.gac1e443424-goog
^ permalink raw reply related [flat|nested] 18+ messages in thread* [PATCH v3 17/21] perf vendor events intel: Fix uncore topics for sandybridge
2023-04-13 13:29 [PATCH v3 00/21] Update uncore topics, 1x event updates, 2x new archs Ian Rogers
` (7 preceding siblings ...)
2023-04-13 13:29 ` [PATCH v3 16/21] perf vendor events intel: Fix uncore topics for knightslanding Ian Rogers
@ 2023-04-13 13:29 ` Ian Rogers
2023-04-13 13:29 ` [PATCH v3 18/21] perf vendor events intel: Fix uncore topics for skylake Ian Rogers
` (3 subsequent siblings)
12 siblings, 0 replies; 18+ messages in thread
From: Ian Rogers @ 2023-04-13 13:29 UTC (permalink / raw)
To: Peter Zijlstra, Ingo Molnar, Arnaldo Carvalho de Melo,
Mark Rutland, Alexander Shishkin, Jiri Olsa, Namhyung Kim,
Zhengjun Xing, Kan Liang, linux-perf-users, linux-kernel,
Edward Baker, Perry Taylor, Caleb Biggers
Cc: Stephane Eranian, Ian Rogers
Remove 'uncore-other' topic classification, move to cache and
interconnect.
Signed-off-by: Ian Rogers <irogers@google.com>
---
.../arch/x86/sandybridge/uncore-cache.json | 50 +++++++++----------
...re-other.json => uncore-interconnect.json} | 0
2 files changed, 25 insertions(+), 25 deletions(-)
rename tools/perf/pmu-events/arch/x86/sandybridge/{uncore-other.json => uncore-interconnect.json} (100%)
diff --git a/tools/perf/pmu-events/arch/x86/sandybridge/uncore-cache.json b/tools/perf/pmu-events/arch/x86/sandybridge/uncore-cache.json
index c538557ba4c0..be9a3ed1a940 100644
--- a/tools/perf/pmu-events/arch/x86/sandybridge/uncore-cache.json
+++ b/tools/perf/pmu-events/arch/x86/sandybridge/uncore-cache.json
@@ -5,7 +5,7 @@
"EventName": "UNC_CBO_CACHE_LOOKUP.ANY_ES",
"PerPkg": "1",
"UMask": "0x86",
- "Unit": "CBO"
+ "Unit": "CBOX"
},
{
"BriefDescription": "L3 Lookup any request that access cache and found line in I-state.",
@@ -13,7 +13,7 @@
"EventName": "UNC_CBO_CACHE_LOOKUP.ANY_I",
"PerPkg": "1",
"UMask": "0x88",
- "Unit": "CBO"
+ "Unit": "CBOX"
},
{
"BriefDescription": "L3 Lookup any request that access cache and found line in M-state.",
@@ -21,7 +21,7 @@
"EventName": "UNC_CBO_CACHE_LOOKUP.ANY_M",
"PerPkg": "1",
"UMask": "0x81",
- "Unit": "CBO"
+ "Unit": "CBOX"
},
{
"BriefDescription": "L3 Lookup any request that access cache and found line in MESI-state.",
@@ -29,7 +29,7 @@
"EventName": "UNC_CBO_CACHE_LOOKUP.ANY_MESI",
"PerPkg": "1",
"UMask": "0x8f",
- "Unit": "CBO"
+ "Unit": "CBOX"
},
{
"BriefDescription": "L3 Lookup external snoop request that access cache and found line in E or S-state.",
@@ -37,7 +37,7 @@
"EventName": "UNC_CBO_CACHE_LOOKUP.EXTSNP_ES",
"PerPkg": "1",
"UMask": "0x46",
- "Unit": "CBO"
+ "Unit": "CBOX"
},
{
"BriefDescription": "L3 Lookup external snoop request that access cache and found line in I-state.",
@@ -45,7 +45,7 @@
"EventName": "UNC_CBO_CACHE_LOOKUP.EXTSNP_I",
"PerPkg": "1",
"UMask": "0x48",
- "Unit": "CBO"
+ "Unit": "CBOX"
},
{
"BriefDescription": "L3 Lookup external snoop request that access cache and found line in M-state.",
@@ -53,7 +53,7 @@
"EventName": "UNC_CBO_CACHE_LOOKUP.EXTSNP_M",
"PerPkg": "1",
"UMask": "0x41",
- "Unit": "CBO"
+ "Unit": "CBOX"
},
{
"BriefDescription": "L3 Lookup external snoop request that access cache and found line in MESI-state.",
@@ -61,7 +61,7 @@
"EventName": "UNC_CBO_CACHE_LOOKUP.EXTSNP_MESI",
"PerPkg": "1",
"UMask": "0x4f",
- "Unit": "CBO"
+ "Unit": "CBOX"
},
{
"BriefDescription": "L3 Lookup read request that access cache and found line in E or S-state.",
@@ -69,7 +69,7 @@
"EventName": "UNC_CBO_CACHE_LOOKUP.READ_ES",
"PerPkg": "1",
"UMask": "0x16",
- "Unit": "CBO"
+ "Unit": "CBOX"
},
{
"BriefDescription": "L3 Lookup read request that access cache and found line in I-state.",
@@ -77,7 +77,7 @@
"EventName": "UNC_CBO_CACHE_LOOKUP.READ_I",
"PerPkg": "1",
"UMask": "0x18",
- "Unit": "CBO"
+ "Unit": "CBOX"
},
{
"BriefDescription": "L3 Lookup read request that access cache and found line in M-state.",
@@ -85,7 +85,7 @@
"EventName": "UNC_CBO_CACHE_LOOKUP.READ_M",
"PerPkg": "1",
"UMask": "0x11",
- "Unit": "CBO"
+ "Unit": "CBOX"
},
{
"BriefDescription": "L3 Lookup read request that access cache and found line in any MESI-state.",
@@ -93,7 +93,7 @@
"EventName": "UNC_CBO_CACHE_LOOKUP.READ_MESI",
"PerPkg": "1",
"UMask": "0x1f",
- "Unit": "CBO"
+ "Unit": "CBOX"
},
{
"BriefDescription": "L3 Lookup write request that access cache and found line in E or S-state.",
@@ -101,7 +101,7 @@
"EventName": "UNC_CBO_CACHE_LOOKUP.WRITE_ES",
"PerPkg": "1",
"UMask": "0x26",
- "Unit": "CBO"
+ "Unit": "CBOX"
},
{
"BriefDescription": "L3 Lookup write request that access cache and found line in I-state.",
@@ -109,7 +109,7 @@
"EventName": "UNC_CBO_CACHE_LOOKUP.WRITE_I",
"PerPkg": "1",
"UMask": "0x28",
- "Unit": "CBO"
+ "Unit": "CBOX"
},
{
"BriefDescription": "L3 Lookup write request that access cache and found line in M-state.",
@@ -117,7 +117,7 @@
"EventName": "UNC_CBO_CACHE_LOOKUP.WRITE_M",
"PerPkg": "1",
"UMask": "0x21",
- "Unit": "CBO"
+ "Unit": "CBOX"
},
{
"BriefDescription": "L3 Lookup write request that access cache and found line in MESI-state.",
@@ -125,7 +125,7 @@
"EventName": "UNC_CBO_CACHE_LOOKUP.WRITE_MESI",
"PerPkg": "1",
"UMask": "0x2f",
- "Unit": "CBO"
+ "Unit": "CBOX"
},
{
"BriefDescription": "A cross-core snoop resulted from L3 Eviction which hits a modified line in some processor core.",
@@ -133,7 +133,7 @@
"EventName": "UNC_CBO_XSNP_RESPONSE.HITM_EVICTION",
"PerPkg": "1",
"UMask": "0x88",
- "Unit": "CBO"
+ "Unit": "CBOX"
},
{
"BriefDescription": "An external snoop hits a modified line in some processor core.",
@@ -141,7 +141,7 @@
"EventName": "UNC_CBO_XSNP_RESPONSE.HITM_EXTERNAL",
"PerPkg": "1",
"UMask": "0x28",
- "Unit": "CBO"
+ "Unit": "CBOX"
},
{
"BriefDescription": "A cross-core snoop initiated by this Cbox due to processor core memory request which hits a modified line in some processor core.",
@@ -149,7 +149,7 @@
"EventName": "UNC_CBO_XSNP_RESPONSE.HITM_XCORE",
"PerPkg": "1",
"UMask": "0x48",
- "Unit": "CBO"
+ "Unit": "CBOX"
},
{
"BriefDescription": "A cross-core snoop resulted from L3 Eviction which hits a non-modified line in some processor core.",
@@ -157,7 +157,7 @@
"EventName": "UNC_CBO_XSNP_RESPONSE.HIT_EVICTION",
"PerPkg": "1",
"UMask": "0x84",
- "Unit": "CBO"
+ "Unit": "CBOX"
},
{
"BriefDescription": "An external snoop hits a non-modified line in some processor core.",
@@ -165,7 +165,7 @@
"EventName": "UNC_CBO_XSNP_RESPONSE.HIT_EXTERNAL",
"PerPkg": "1",
"UMask": "0x24",
- "Unit": "CBO"
+ "Unit": "CBOX"
},
{
"BriefDescription": "A cross-core snoop initiated by this Cbox due to processor core memory request which hits a non-modified line in some processor core.",
@@ -173,7 +173,7 @@
"EventName": "UNC_CBO_XSNP_RESPONSE.HIT_XCORE",
"PerPkg": "1",
"UMask": "0x44",
- "Unit": "CBO"
+ "Unit": "CBOX"
},
{
"BriefDescription": "A cross-core snoop resulted from L3 Eviction which misses in some processor core.",
@@ -181,7 +181,7 @@
"EventName": "UNC_CBO_XSNP_RESPONSE.MISS_EVICTION",
"PerPkg": "1",
"UMask": "0x81",
- "Unit": "CBO"
+ "Unit": "CBOX"
},
{
"BriefDescription": "An external snoop misses in some processor core.",
@@ -189,7 +189,7 @@
"EventName": "UNC_CBO_XSNP_RESPONSE.MISS_EXTERNAL",
"PerPkg": "1",
"UMask": "0x21",
- "Unit": "CBO"
+ "Unit": "CBOX"
},
{
"BriefDescription": "A cross-core snoop initiated by this Cbox due to processor core memory request which misses in some processor core.",
@@ -197,6 +197,6 @@
"EventName": "UNC_CBO_XSNP_RESPONSE.MISS_XCORE",
"PerPkg": "1",
"UMask": "0x41",
- "Unit": "CBO"
+ "Unit": "CBOX"
}
]
diff --git a/tools/perf/pmu-events/arch/x86/sandybridge/uncore-other.json b/tools/perf/pmu-events/arch/x86/sandybridge/uncore-interconnect.json
similarity index 100%
rename from tools/perf/pmu-events/arch/x86/sandybridge/uncore-other.json
rename to tools/perf/pmu-events/arch/x86/sandybridge/uncore-interconnect.json
--
2.40.0.577.gac1e443424-goog
^ permalink raw reply related [flat|nested] 18+ messages in thread* [PATCH v3 18/21] perf vendor events intel: Fix uncore topics for skylake
2023-04-13 13:29 [PATCH v3 00/21] Update uncore topics, 1x event updates, 2x new archs Ian Rogers
` (8 preceding siblings ...)
2023-04-13 13:29 ` [PATCH v3 17/21] perf vendor events intel: Fix uncore topics for sandybridge Ian Rogers
@ 2023-04-13 13:29 ` Ian Rogers
2023-04-13 13:29 ` [PATCH v3 21/21] perf vendor events intel: Fix uncore topics for tigerlake Ian Rogers
` (2 subsequent siblings)
12 siblings, 0 replies; 18+ messages in thread
From: Ian Rogers @ 2023-04-13 13:29 UTC (permalink / raw)
To: Peter Zijlstra, Ingo Molnar, Arnaldo Carvalho de Melo,
Mark Rutland, Alexander Shishkin, Jiri Olsa, Namhyung Kim,
Zhengjun Xing, Kan Liang, linux-perf-users, linux-kernel,
Edward Baker, Perry Taylor, Caleb Biggers
Cc: Stephane Eranian, Ian Rogers
Move events from 'uncore-other' topic classification to cache and
interconnect.
Signed-off-by: Ian Rogers <irogers@google.com>
---
.../arch/x86/skylake/uncore-cache.json | 28 ++++----
.../arch/x86/skylake/uncore-interconnect.json | 67 +++++++++++++++++++
.../arch/x86/skylake/uncore-other.json | 65 ------------------
3 files changed, 81 insertions(+), 79 deletions(-)
create mode 100644 tools/perf/pmu-events/arch/x86/skylake/uncore-interconnect.json
diff --git a/tools/perf/pmu-events/arch/x86/skylake/uncore-cache.json b/tools/perf/pmu-events/arch/x86/skylake/uncore-cache.json
index ec9463c94ffe..b4e061477c1a 100644
--- a/tools/perf/pmu-events/arch/x86/skylake/uncore-cache.json
+++ b/tools/perf/pmu-events/arch/x86/skylake/uncore-cache.json
@@ -6,7 +6,7 @@
"PerPkg": "1",
"PublicDescription": "L3 Lookup any request that access cache and found line in E or S-state.",
"UMask": "0x86",
- "Unit": "CBO"
+ "Unit": "CBOX"
},
{
"BriefDescription": "L3 Lookup any request that access cache and found line in I-state",
@@ -15,7 +15,7 @@
"PerPkg": "1",
"PublicDescription": "L3 Lookup any request that access cache and found line in I-state.",
"UMask": "0x88",
- "Unit": "CBO"
+ "Unit": "CBOX"
},
{
"BriefDescription": "L3 Lookup any request that access cache and found line in M-state",
@@ -24,7 +24,7 @@
"PerPkg": "1",
"PublicDescription": "L3 Lookup any request that access cache and found line in M-state.",
"UMask": "0x81",
- "Unit": "CBO"
+ "Unit": "CBOX"
},
{
"BriefDescription": "L3 Lookup any request that access cache and found line in MESI-state",
@@ -33,7 +33,7 @@
"PerPkg": "1",
"PublicDescription": "L3 Lookup any request that access cache and found line in MESI-state.",
"UMask": "0x8f",
- "Unit": "CBO"
+ "Unit": "CBOX"
},
{
"BriefDescription": "L3 Lookup read request that access cache and found line in E or S-state",
@@ -42,7 +42,7 @@
"PerPkg": "1",
"PublicDescription": "L3 Lookup read request that access cache and found line in E or S-state.",
"UMask": "0x16",
- "Unit": "CBO"
+ "Unit": "CBOX"
},
{
"BriefDescription": "L3 Lookup read request that access cache and found line in I-state",
@@ -51,7 +51,7 @@
"PerPkg": "1",
"PublicDescription": "L3 Lookup read request that access cache and found line in I-state.",
"UMask": "0x18",
- "Unit": "CBO"
+ "Unit": "CBOX"
},
{
"BriefDescription": "L3 Lookup read request that access cache and found line in any MESI-state",
@@ -60,7 +60,7 @@
"PerPkg": "1",
"PublicDescription": "L3 Lookup read request that access cache and found line in any MESI-state.",
"UMask": "0x1f",
- "Unit": "CBO"
+ "Unit": "CBOX"
},
{
"BriefDescription": "L3 Lookup write request that access cache and found line in E or S-state",
@@ -69,7 +69,7 @@
"PerPkg": "1",
"PublicDescription": "L3 Lookup write request that access cache and found line in E or S-state.",
"UMask": "0x26",
- "Unit": "CBO"
+ "Unit": "CBOX"
},
{
"BriefDescription": "L3 Lookup write request that access cache and found line in M-state",
@@ -78,7 +78,7 @@
"PerPkg": "1",
"PublicDescription": "L3 Lookup write request that access cache and found line in M-state.",
"UMask": "0x21",
- "Unit": "CBO"
+ "Unit": "CBOX"
},
{
"BriefDescription": "L3 Lookup write request that access cache and found line in MESI-state",
@@ -87,7 +87,7 @@
"PerPkg": "1",
"PublicDescription": "L3 Lookup write request that access cache and found line in MESI-state.",
"UMask": "0x2f",
- "Unit": "CBO"
+ "Unit": "CBOX"
},
{
"BriefDescription": "A cross-core snoop initiated by this Cbox due to processor core memory request which hits a modified line in some processor core.",
@@ -95,7 +95,7 @@
"EventName": "UNC_CBO_XSNP_RESPONSE.HITM_XCORE",
"PerPkg": "1",
"UMask": "0x48",
- "Unit": "CBO"
+ "Unit": "CBOX"
},
{
"BriefDescription": "A cross-core snoop initiated by this Cbox due to processor core memory request which hits a non-modified line in some processor core.",
@@ -103,7 +103,7 @@
"EventName": "UNC_CBO_XSNP_RESPONSE.HIT_XCORE",
"PerPkg": "1",
"UMask": "0x44",
- "Unit": "CBO"
+ "Unit": "CBOX"
},
{
"BriefDescription": "A cross-core snoop resulted from L3 Eviction which misses in some processor core.",
@@ -111,7 +111,7 @@
"EventName": "UNC_CBO_XSNP_RESPONSE.MISS_EVICTION",
"PerPkg": "1",
"UMask": "0x81",
- "Unit": "CBO"
+ "Unit": "CBOX"
},
{
"BriefDescription": "A cross-core snoop initiated by this Cbox due to processor core memory request which misses in some processor core.",
@@ -119,6 +119,6 @@
"EventName": "UNC_CBO_XSNP_RESPONSE.MISS_XCORE",
"PerPkg": "1",
"UMask": "0x41",
- "Unit": "CBO"
+ "Unit": "CBOX"
}
]
diff --git a/tools/perf/pmu-events/arch/x86/skylake/uncore-interconnect.json b/tools/perf/pmu-events/arch/x86/skylake/uncore-interconnect.json
new file mode 100644
index 000000000000..fe7e19717371
--- /dev/null
+++ b/tools/perf/pmu-events/arch/x86/skylake/uncore-interconnect.json
@@ -0,0 +1,67 @@
+[
+ {
+ "BriefDescription": "Number of entries allocated. Account for Any type: e.g. Snoop, Core aperture, etc.",
+ "EventCode": "0x84",
+ "EventName": "UNC_ARB_COH_TRK_REQUESTS.ALL",
+ "PerPkg": "1",
+ "UMask": "0x1",
+ "Unit": "ARB"
+ },
+ {
+ "BriefDescription": "Number of all Core entries outstanding for the memory controller. The outstanding interval starts after LLC miss till return of first data chunk. Accounts for Coherent and non-coherent traffic.",
+ "EventCode": "0x80",
+ "EventName": "UNC_ARB_TRK_OCCUPANCY.ALL",
+ "PerPkg": "1",
+ "UMask": "0x1",
+ "Unit": "ARB"
+ },
+ {
+ "BriefDescription": "Cycles with at least one request outstanding is waiting for data return from memory controller. Account for coherent and non-coherent requests initiated by IA Cores, Processor Graphics Unit, or LLC.",
+ "CounterMask": "1",
+ "EventCode": "0x80",
+ "EventName": "UNC_ARB_TRK_OCCUPANCY.CYCLES_WITH_ANY_REQUEST",
+ "PerPkg": "1",
+ "UMask": "0x1",
+ "Unit": "ARB"
+ },
+ {
+ "BriefDescription": "Number of Core Data Read entries outstanding for the memory controller. The outstanding interval starts after LLC miss till return of first data chunk.",
+ "EventCode": "0x80",
+ "EventName": "UNC_ARB_TRK_OCCUPANCY.DATA_READ",
+ "PerPkg": "1",
+ "UMask": "0x2",
+ "Unit": "ARB"
+ },
+ {
+ "BriefDescription": "UNC_ARB_TRK_REQUESTS.ALL",
+ "EventCode": "0x81",
+ "EventName": "UNC_ARB_TRK_REQUESTS.ALL",
+ "PerPkg": "1",
+ "UMask": "0x1",
+ "Unit": "ARB"
+ },
+ {
+ "BriefDescription": "Number of Core coherent Data Read requests sent to memory controller whose data is returned directly to requesting agent.",
+ "EventCode": "0x81",
+ "EventName": "UNC_ARB_TRK_REQUESTS.DATA_READ",
+ "PerPkg": "1",
+ "UMask": "0x2",
+ "Unit": "ARB"
+ },
+ {
+ "BriefDescription": "Number of Core coherent Data Read requests sent to memory controller whose data is returned directly to requesting agent.",
+ "EventCode": "0x81",
+ "EventName": "UNC_ARB_TRK_REQUESTS.DRD_DIRECT",
+ "PerPkg": "1",
+ "UMask": "0x2",
+ "Unit": "ARB"
+ },
+ {
+ "BriefDescription": "Number of Writes allocated - any write transactions: full/partials writes and evictions.",
+ "EventCode": "0x81",
+ "EventName": "UNC_ARB_TRK_REQUESTS.WRITES",
+ "PerPkg": "1",
+ "UMask": "0x20",
+ "Unit": "ARB"
+ }
+]
diff --git a/tools/perf/pmu-events/arch/x86/skylake/uncore-other.json b/tools/perf/pmu-events/arch/x86/skylake/uncore-other.json
index ef804df3f41e..58be90d7cc93 100644
--- a/tools/perf/pmu-events/arch/x86/skylake/uncore-other.json
+++ b/tools/perf/pmu-events/arch/x86/skylake/uncore-other.json
@@ -1,69 +1,4 @@
[
- {
- "BriefDescription": "Number of entries allocated. Account for Any type: e.g. Snoop, Core aperture, etc.",
- "EventCode": "0x84",
- "EventName": "UNC_ARB_COH_TRK_REQUESTS.ALL",
- "PerPkg": "1",
- "UMask": "0x1",
- "Unit": "ARB"
- },
- {
- "BriefDescription": "Number of all Core entries outstanding for the memory controller. The outstanding interval starts after LLC miss till return of first data chunk. Accounts for Coherent and non-coherent traffic.",
- "EventCode": "0x80",
- "EventName": "UNC_ARB_TRK_OCCUPANCY.ALL",
- "PerPkg": "1",
- "UMask": "0x1",
- "Unit": "ARB"
- },
- {
- "BriefDescription": "Cycles with at least one request outstanding is waiting for data return from memory controller. Account for coherent and non-coherent requests initiated by IA Cores, Processor Graphics Unit, or LLC.",
- "CounterMask": "1",
- "EventCode": "0x80",
- "EventName": "UNC_ARB_TRK_OCCUPANCY.CYCLES_WITH_ANY_REQUEST",
- "PerPkg": "1",
- "UMask": "0x1",
- "Unit": "ARB"
- },
- {
- "BriefDescription": "Number of Core Data Read entries outstanding for the memory controller. The outstanding interval starts after LLC miss till return of first data chunk.",
- "EventCode": "0x80",
- "EventName": "UNC_ARB_TRK_OCCUPANCY.DATA_READ",
- "PerPkg": "1",
- "UMask": "0x2",
- "Unit": "ARB"
- },
- {
- "BriefDescription": "UNC_ARB_TRK_REQUESTS.ALL",
- "EventCode": "0x81",
- "EventName": "UNC_ARB_TRK_REQUESTS.ALL",
- "PerPkg": "1",
- "UMask": "0x1",
- "Unit": "ARB"
- },
- {
- "BriefDescription": "Number of Core coherent Data Read requests sent to memory controller whose data is returned directly to requesting agent.",
- "EventCode": "0x81",
- "EventName": "UNC_ARB_TRK_REQUESTS.DATA_READ",
- "PerPkg": "1",
- "UMask": "0x2",
- "Unit": "ARB"
- },
- {
- "BriefDescription": "Number of Core coherent Data Read requests sent to memory controller whose data is returned directly to requesting agent.",
- "EventCode": "0x81",
- "EventName": "UNC_ARB_TRK_REQUESTS.DRD_DIRECT",
- "PerPkg": "1",
- "UMask": "0x2",
- "Unit": "ARB"
- },
- {
- "BriefDescription": "Number of Writes allocated - any write transactions: full/partials writes and evictions.",
- "EventCode": "0x81",
- "EventName": "UNC_ARB_TRK_REQUESTS.WRITES",
- "PerPkg": "1",
- "UMask": "0x20",
- "Unit": "ARB"
- },
{
"BriefDescription": "This 48-bit fixed counter counts the UCLK cycles",
"EventCode": "0xff",
--
2.40.0.577.gac1e443424-goog
^ permalink raw reply related [flat|nested] 18+ messages in thread* [PATCH v3 21/21] perf vendor events intel: Fix uncore topics for tigerlake
2023-04-13 13:29 [PATCH v3 00/21] Update uncore topics, 1x event updates, 2x new archs Ian Rogers
` (9 preceding siblings ...)
2023-04-13 13:29 ` [PATCH v3 18/21] perf vendor events intel: Fix uncore topics for skylake Ian Rogers
@ 2023-04-13 13:29 ` Ian Rogers
2023-04-13 14:04 ` [PATCH v3 00/21] Update uncore topics, 1x event updates, 2x new archs Arnaldo Carvalho de Melo
2023-04-13 21:57 ` Arnaldo Carvalho de Melo
12 siblings, 0 replies; 18+ messages in thread
From: Ian Rogers @ 2023-04-13 13:29 UTC (permalink / raw)
To: Peter Zijlstra, Ingo Molnar, Arnaldo Carvalho de Melo,
Mark Rutland, Alexander Shishkin, Jiri Olsa, Namhyung Kim,
Zhengjun Xing, Kan Liang, linux-perf-users, linux-kernel,
Edward Baker, Perry Taylor, Caleb Biggers
Cc: Stephane Eranian, Ian Rogers
Move events from 'uncore-other' topic classification to interconnect.
Signed-off-by: Ian Rogers <irogers@google.com>
---
.../x86/tigerlake/uncore-interconnect.json | 90 +++++++++++++++++++
.../arch/x86/tigerlake/uncore-other.json | 88 ------------------
2 files changed, 90 insertions(+), 88 deletions(-)
create mode 100644 tools/perf/pmu-events/arch/x86/tigerlake/uncore-interconnect.json
diff --git a/tools/perf/pmu-events/arch/x86/tigerlake/uncore-interconnect.json b/tools/perf/pmu-events/arch/x86/tigerlake/uncore-interconnect.json
new file mode 100644
index 000000000000..eed1b90a2779
--- /dev/null
+++ b/tools/perf/pmu-events/arch/x86/tigerlake/uncore-interconnect.json
@@ -0,0 +1,90 @@
+[
+ {
+ "BriefDescription": "UNC_ARB_COH_TRK_REQUESTS.ALL",
+ "EventCode": "0x84",
+ "EventName": "UNC_ARB_COH_TRK_REQUESTS.ALL",
+ "PerPkg": "1",
+ "UMask": "0x1",
+ "Unit": "ARB"
+ },
+ {
+ "BriefDescription": "Each cycle counts number of any coherent request at memory controller that were issued by any core.",
+ "EventCode": "0x85",
+ "EventName": "UNC_ARB_DAT_OCCUPANCY.ALL",
+ "PerPkg": "1",
+ "UMask": "0x1",
+ "Unit": "ARB"
+ },
+ {
+ "BriefDescription": "Each cycle counts number of coherent reads pending on data return from memory controller that were issued by any core.",
+ "EventCode": "0x85",
+ "EventName": "UNC_ARB_DAT_OCCUPANCY.RD",
+ "PerPkg": "1",
+ "UMask": "0x2",
+ "Unit": "ARB"
+ },
+ {
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_ARB_REQ_TRK_REQUEST.DRD",
+ "EventCode": "0x81",
+ "EventName": "UNC_ARB_DAT_REQUESTS.RD",
+ "PerPkg": "1",
+ "UMask": "0x2",
+ "Unit": "ARB"
+ },
+ {
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_ARB_DAT_OCCUPANCY.ALL",
+ "EventCode": "0x85",
+ "EventName": "UNC_ARB_IFA_OCCUPANCY.ALL",
+ "PerPkg": "1",
+ "UMask": "0x1",
+ "Unit": "ARB"
+ },
+ {
+ "BriefDescription": "Each cycle count number of 'valid' coherent Data Read entries . Such entry is defined as valid when it is allocated till deallocation. Doesn't include prefetches [This event is alias to UNC_ARB_TRK_OCCUPANCY.RD]",
+ "EventCode": "0x80",
+ "EventName": "UNC_ARB_REQ_TRK_OCCUPANCY.DRD",
+ "PerPkg": "1",
+ "UMask": "0x2",
+ "Unit": "ARB"
+ },
+ {
+ "BriefDescription": "Number of all coherent Data Read entries. Doesn't include prefetches [This event is alias to UNC_ARB_TRK_REQUESTS.RD]",
+ "EventCode": "0x81",
+ "EventName": "UNC_ARB_REQ_TRK_REQUEST.DRD",
+ "PerPkg": "1",
+ "UMask": "0x2",
+ "Unit": "ARB"
+ },
+ {
+ "BriefDescription": "Each cycle count number of all outgoing valid entries in ReqTrk. Such entry is defined as valid from it's allocation in ReqTrk till deallocation. Accounts for Coherent and non-coherent traffic.",
+ "EventCode": "0x80",
+ "EventName": "UNC_ARB_TRK_OCCUPANCY.ALL",
+ "PerPkg": "1",
+ "UMask": "0x1",
+ "Unit": "ARB"
+ },
+ {
+ "BriefDescription": "Each cycle count number of 'valid' coherent Data Read entries . Such entry is defined as valid when it is allocated till deallocation. Doesn't include prefetches [This event is alias to UNC_ARB_REQ_TRK_OCCUPANCY.DRD]",
+ "EventCode": "0x80",
+ "EventName": "UNC_ARB_TRK_OCCUPANCY.RD",
+ "PerPkg": "1",
+ "UMask": "0x2",
+ "Unit": "ARB"
+ },
+ {
+ "BriefDescription": "UNC_ARB_TRK_REQUESTS.ALL",
+ "EventCode": "0x81",
+ "EventName": "UNC_ARB_TRK_REQUESTS.ALL",
+ "PerPkg": "1",
+ "UMask": "0x1",
+ "Unit": "ARB"
+ },
+ {
+ "BriefDescription": "Number of all coherent Data Read entries. Doesn't include prefetches [This event is alias to UNC_ARB_REQ_TRK_REQUEST.DRD]",
+ "EventCode": "0x81",
+ "EventName": "UNC_ARB_TRK_REQUESTS.RD",
+ "PerPkg": "1",
+ "UMask": "0x2",
+ "Unit": "ARB"
+ }
+]
diff --git a/tools/perf/pmu-events/arch/x86/tigerlake/uncore-other.json b/tools/perf/pmu-events/arch/x86/tigerlake/uncore-other.json
index 6e43aaf64e28..c6596ba09195 100644
--- a/tools/perf/pmu-events/arch/x86/tigerlake/uncore-other.json
+++ b/tools/perf/pmu-events/arch/x86/tigerlake/uncore-other.json
@@ -1,92 +1,4 @@
[
- {
- "BriefDescription": "UNC_ARB_COH_TRK_REQUESTS.ALL",
- "EventCode": "0x84",
- "EventName": "UNC_ARB_COH_TRK_REQUESTS.ALL",
- "PerPkg": "1",
- "UMask": "0x1",
- "Unit": "ARB"
- },
- {
- "BriefDescription": "Each cycle counts number of any coherent request at memory controller that were issued by any core.",
- "EventCode": "0x85",
- "EventName": "UNC_ARB_DAT_OCCUPANCY.ALL",
- "PerPkg": "1",
- "UMask": "0x1",
- "Unit": "ARB"
- },
- {
- "BriefDescription": "Each cycle counts number of coherent reads pending on data return from memory controller that were issued by any core.",
- "EventCode": "0x85",
- "EventName": "UNC_ARB_DAT_OCCUPANCY.RD",
- "PerPkg": "1",
- "UMask": "0x2",
- "Unit": "ARB"
- },
- {
- "BriefDescription": "This event is deprecated. Refer to new event UNC_ARB_REQ_TRK_REQUEST.DRD",
- "EventCode": "0x81",
- "EventName": "UNC_ARB_DAT_REQUESTS.RD",
- "PerPkg": "1",
- "UMask": "0x2",
- "Unit": "ARB"
- },
- {
- "BriefDescription": "This event is deprecated. Refer to new event UNC_ARB_DAT_OCCUPANCY.ALL",
- "EventCode": "0x85",
- "EventName": "UNC_ARB_IFA_OCCUPANCY.ALL",
- "PerPkg": "1",
- "UMask": "0x1",
- "Unit": "ARB"
- },
- {
- "BriefDescription": "Each cycle count number of 'valid' coherent Data Read entries . Such entry is defined as valid when it is allocated till deallocation. Doesn't include prefetches [This event is alias to UNC_ARB_TRK_OCCUPANCY.RD]",
- "EventCode": "0x80",
- "EventName": "UNC_ARB_REQ_TRK_OCCUPANCY.DRD",
- "PerPkg": "1",
- "UMask": "0x2",
- "Unit": "ARB"
- },
- {
- "BriefDescription": "Number of all coherent Data Read entries. Doesn't include prefetches [This event is alias to UNC_ARB_TRK_REQUESTS.RD]",
- "EventCode": "0x81",
- "EventName": "UNC_ARB_REQ_TRK_REQUEST.DRD",
- "PerPkg": "1",
- "UMask": "0x2",
- "Unit": "ARB"
- },
- {
- "BriefDescription": "Each cycle count number of all outgoing valid entries in ReqTrk. Such entry is defined as valid from it's allocation in ReqTrk till deallocation. Accounts for Coherent and non-coherent traffic.",
- "EventCode": "0x80",
- "EventName": "UNC_ARB_TRK_OCCUPANCY.ALL",
- "PerPkg": "1",
- "UMask": "0x1",
- "Unit": "ARB"
- },
- {
- "BriefDescription": "Each cycle count number of 'valid' coherent Data Read entries . Such entry is defined as valid when it is allocated till deallocation. Doesn't include prefetches [This event is alias to UNC_ARB_REQ_TRK_OCCUPANCY.DRD]",
- "EventCode": "0x80",
- "EventName": "UNC_ARB_TRK_OCCUPANCY.RD",
- "PerPkg": "1",
- "UMask": "0x2",
- "Unit": "ARB"
- },
- {
- "BriefDescription": "UNC_ARB_TRK_REQUESTS.ALL",
- "EventCode": "0x81",
- "EventName": "UNC_ARB_TRK_REQUESTS.ALL",
- "PerPkg": "1",
- "UMask": "0x1",
- "Unit": "ARB"
- },
- {
- "BriefDescription": "Number of all coherent Data Read entries. Doesn't include prefetches [This event is alias to UNC_ARB_REQ_TRK_REQUEST.DRD]",
- "EventCode": "0x81",
- "EventName": "UNC_ARB_TRK_REQUESTS.RD",
- "PerPkg": "1",
- "UMask": "0x2",
- "Unit": "ARB"
- },
{
"BriefDescription": "UNC_CLOCK.SOCKET",
"EventCode": "0xff",
--
2.40.0.577.gac1e443424-goog
^ permalink raw reply related [flat|nested] 18+ messages in thread* Re: [PATCH v3 00/21] Update uncore topics, 1x event updates, 2x new archs.
2023-04-13 13:29 [PATCH v3 00/21] Update uncore topics, 1x event updates, 2x new archs Ian Rogers
` (10 preceding siblings ...)
2023-04-13 13:29 ` [PATCH v3 21/21] perf vendor events intel: Fix uncore topics for tigerlake Ian Rogers
@ 2023-04-13 14:04 ` Arnaldo Carvalho de Melo
2023-04-13 15:34 ` Ian Rogers
2023-04-14 8:18 ` Peter Zijlstra
2023-04-13 21:57 ` Arnaldo Carvalho de Melo
12 siblings, 2 replies; 18+ messages in thread
From: Arnaldo Carvalho de Melo @ 2023-04-13 14:04 UTC (permalink / raw)
To: Ian Rogers
Cc: Peter Zijlstra, Ingo Molnar, Mark Rutland, Alexander Shishkin,
Jiri Olsa, Namhyung Kim, Zhengjun Xing, Kan Liang,
linux-perf-users, linux-kernel, Edward Baker, Perry Taylor,
Caleb Biggers, Stephane Eranian
Em Thu, Apr 13, 2023 at 06:29:28AM -0700, Ian Rogers escreveu:
> Update the uncore PMUs and topic classification as created by:
> https://github.com/intel/perfmon/pull/70
>
> Event updates stem from:
> https://github.com/intel/perfmon/pull/68
> impacting alderlake, icelakex and sapphirerapids.
>
> Grand Ridge and Sierra Forest events stem from:
> https://github.com/intel/perfmon/pull/69
>
> Changes generated by with PR70 in place:
> https://github.com/intel/perfmon/blob/main/scripts/create_perf_json.py
>
> v3. Rebase over the update of alderlake and icelakex events.
> v2. Adds improvements to uncore topics, uncore PMU name fixes and
> fixes a trigraph issue from ??? being in the json.
b4 isn't liking it:
⬢[acme@toolbox perf-tools-next]$ b4 am -ctsl --cc-trailers 20230413132949.3487664-1-irogers@google.com
Grabbing thread from lore.kernel.org/all/20230413132949.3487664-1-irogers%40google.com/t.mbox.gz
Checking for newer revisions
Grabbing search results from lore.kernel.org
Analyzing 14 messages in the thread
Checking attestation on all messages, may take a moment...
---
ERROR: missing [1/21]!
✓ [PATCH v3 2/21] perf vendor events intel: Add grandridge
✓ Signed: DKIM/google.com
+ Link: https://lore.kernel.org/r/20230413132949.3487664-3-irogers@google.com
+ Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com>
✓ [PATCH v3 3/21] perf vendor events intel: Add sierraforest
✓ Signed: DKIM/google.com
+ Link: https://lore.kernel.org/r/20230413132949.3487664-3-irogers@google.com
+ Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com>
✓ [PATCH v3 4/21] perf vendor events intel: Fix uncore topics for alderlake
✓ Signed: DKIM/google.com
+ Link: https://lore.kernel.org/r/20230413132949.3487664-3-irogers@google.com
+ Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com>
✓ [PATCH v3 5/21] perf vendor events intel: Fix uncore topics for broadwell
✓ Signed: DKIM/google.com
+ Link: https://lore.kernel.org/r/20230413132949.3487664-3-irogers@google.com
+ Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com>
✓ [PATCH v3 6/21] perf vendor events intel: Fix uncore topics for broadwellde
✓ Signed: DKIM/google.com
+ Link: https://lore.kernel.org/r/20230413132949.3487664-3-irogers@google.com
+ Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com>
ERROR: missing [7/21]!
ERROR: missing [8/21]!
✓ [PATCH v3 9/21] perf vendor events intel: Fix uncore topics for haswell
✓ Signed: DKIM/google.com
+ Link: https://lore.kernel.org/r/20230413132949.3487664-3-irogers@google.com
+ Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com>
ERROR: missing [10/21]!
✓ [PATCH v3 11/21] perf vendor events intel: Fix uncore topics for icelake
✓ Signed: DKIM/google.com
+ Link: https://lore.kernel.org/r/20230413132949.3487664-3-irogers@google.com
+ Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com>
ERROR: missing [12/21]!
✓ [PATCH v3 13/21] perf vendor events intel: Fix uncore topics for ivybridge
✓ Signed: DKIM/google.com
+ Link: https://lore.kernel.org/r/20230413132949.3487664-3-irogers@google.com
+ Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com>
ERROR: missing [14/21]!
✓ [PATCH v3 15/21] perf vendor events intel: Fix uncore topics for jaketown
✓ Signed: DKIM/google.com
+ Link: https://lore.kernel.org/r/20230413132949.3487664-3-irogers@google.com
+ Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com>
✓ [PATCH v3 16/21] perf vendor events intel: Fix uncore topics for knightslanding
✓ Signed: DKIM/google.com
+ Link: https://lore.kernel.org/r/20230413132949.3487664-3-irogers@google.com
+ Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com>
✓ [PATCH v3 17/21] perf vendor events intel: Fix uncore topics for sandybridge
✓ Signed: DKIM/google.com
+ Link: https://lore.kernel.org/r/20230413132949.3487664-3-irogers@google.com
+ Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com>
✓ [PATCH v3 18/21] perf vendor events intel: Fix uncore topics for skylake
✓ Signed: DKIM/google.com
+ Link: https://lore.kernel.org/r/20230413132949.3487664-3-irogers@google.com
+ Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com>
ERROR: missing [19/21]!
ERROR: missing [20/21]!
✓ [PATCH v3 21/21] perf vendor events intel: Fix uncore topics for tigerlake
✓ Signed: DKIM/google.com
+ Link: https://lore.kernel.org/r/20230413132949.3487664-3-irogers@google.com
+ Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com>
---
Total patches: 13
---
WARNING: Thread incomplete!
Cover: ./v3_20230413_irogers_update_uncore_topics_1x_event_updates_2x_new_archs.cover
Link: https://lore.kernel.org/r/20230413132949.3487664-1-irogers@google.com
Base: not specified
git am ./v3_20230413_irogers_update_uncore_topics_1x_event_updates_2x_new_archs.mbx
⬢[acme@toolbox perf-tools-next]$
Lemme try to update it to see if it copes... nope:
⬢[acme@toolbox b4]$ git pull
Updating 041d10b7f628fa08..00303592f25693cb
Fast-forward
b4/__init__.py | 54 ++++++++++++++++++++++++++++++++----------------------
b4/command.py | 4 ++--
b4/ez.py | 15 ++++++++++++---
b4/ty.py | 10 ++++++----
docs/config.rst | 19 +++++++++++++++++++
man/b4.5 | 6 +++++-
man/b4.5.rst | 2 ++
tests/samples/trailers-followup-with-cover-ref-addlink.txt | 67 +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
tests/test___init__.py | 1 +
9 files changed, 146 insertions(+), 32 deletions(-)
create mode 100644 tests/samples/trailers-followup-with-cover-ref-addlink.txt
⬢[acme@toolbox b4]$ git diff
⬢[acme@toolbox b4]$ cd -
/var/home/acme/git/perf-tools-next
⬢[acme@toolbox perf-tools-next]$ b4 am -ctsl --cc-trailers 20230413132949.3487664-1-irogers@google.com
Grabbing thread from lore.kernel.org/all/20230413132949.3487664-1-irogers%40google.com/t.mbox.gz
Checking for newer revisions
Grabbing search results from lore.kernel.org
Analyzing 14 messages in the thread
Checking attestation on all messages, may take a moment...
---
ERROR: missing [1/21]!
✓ [PATCH v3 2/21] perf vendor events intel: Add grandridge
✓ Signed: DKIM/google.com
+ Link: https://lore.kernel.org/r/20230413132949.3487664-3-irogers@google.com
+ Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com>
✓ [PATCH v3 3/21] perf vendor events intel: Add sierraforest
✓ Signed: DKIM/google.com
+ Link: https://lore.kernel.org/r/20230413132949.3487664-4-irogers@google.com
+ Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com>
✓ [PATCH v3 4/21] perf vendor events intel: Fix uncore topics for alderlake
✓ Signed: DKIM/google.com
+ Link: https://lore.kernel.org/r/20230413132949.3487664-5-irogers@google.com
+ Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com>
✓ [PATCH v3 5/21] perf vendor events intel: Fix uncore topics for broadwell
✓ Signed: DKIM/google.com
+ Link: https://lore.kernel.org/r/20230413132949.3487664-6-irogers@google.com
+ Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com>
✓ [PATCH v3 6/21] perf vendor events intel: Fix uncore topics for broadwellde
✓ Signed: DKIM/google.com
+ Link: https://lore.kernel.org/r/20230413132949.3487664-7-irogers@google.com
+ Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com>
ERROR: missing [7/21]!
ERROR: missing [8/21]!
✓ [PATCH v3 9/21] perf vendor events intel: Fix uncore topics for haswell
✓ Signed: DKIM/google.com
+ Link: https://lore.kernel.org/r/20230413132949.3487664-10-irogers@google.com
+ Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com>
ERROR: missing [10/21]!
✓ [PATCH v3 11/21] perf vendor events intel: Fix uncore topics for icelake
✓ Signed: DKIM/google.com
+ Link: https://lore.kernel.org/r/20230413132949.3487664-12-irogers@google.com
+ Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com>
ERROR: missing [12/21]!
✓ [PATCH v3 13/21] perf vendor events intel: Fix uncore topics for ivybridge
✓ Signed: DKIM/google.com
+ Link: https://lore.kernel.org/r/20230413132949.3487664-14-irogers@google.com
+ Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com>
ERROR: missing [14/21]!
✓ [PATCH v3 15/21] perf vendor events intel: Fix uncore topics for jaketown
✓ Signed: DKIM/google.com
+ Link: https://lore.kernel.org/r/20230413132949.3487664-16-irogers@google.com
+ Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com>
✓ [PATCH v3 16/21] perf vendor events intel: Fix uncore topics for knightslanding
✓ Signed: DKIM/google.com
+ Link: https://lore.kernel.org/r/20230413132949.3487664-17-irogers@google.com
+ Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com>
✓ [PATCH v3 17/21] perf vendor events intel: Fix uncore topics for sandybridge
✓ Signed: DKIM/google.com
+ Link: https://lore.kernel.org/r/20230413132949.3487664-18-irogers@google.com
+ Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com>
✓ [PATCH v3 18/21] perf vendor events intel: Fix uncore topics for skylake
✓ Signed: DKIM/google.com
+ Link: https://lore.kernel.org/r/20230413132949.3487664-19-irogers@google.com
+ Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com>
ERROR: missing [19/21]!
ERROR: missing [20/21]!
✓ [PATCH v3 21/21] perf vendor events intel: Fix uncore topics for tigerlake
✓ Signed: DKIM/google.com
+ Link: https://lore.kernel.org/r/20230413132949.3487664-22-irogers@google.com
+ Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com>
---
Total patches: 13
---
WARNING: Thread incomplete!
Cover: ./v3_20230413_irogers_update_uncore_topics_1x_event_updates_2x_new_archs.cover
Link: https://lore.kernel.org/r/20230413132949.3487664-1-irogers@google.com
Base: not specified
git am ./v3_20230413_irogers_update_uncore_topics_1x_event_updates_2x_new_archs.mbx
⬢[acme@toolbox perf-tools-next]$
^ permalink raw reply [flat|nested] 18+ messages in thread* Re: [PATCH v3 00/21] Update uncore topics, 1x event updates, 2x new archs.
2023-04-13 14:04 ` [PATCH v3 00/21] Update uncore topics, 1x event updates, 2x new archs Arnaldo Carvalho de Melo
@ 2023-04-13 15:34 ` Ian Rogers
2023-04-14 8:18 ` Peter Zijlstra
1 sibling, 0 replies; 18+ messages in thread
From: Ian Rogers @ 2023-04-13 15:34 UTC (permalink / raw)
To: Arnaldo Carvalho de Melo
Cc: Peter Zijlstra, Ingo Molnar, Mark Rutland, Alexander Shishkin,
Jiri Olsa, Namhyung Kim, Zhengjun Xing, Kan Liang,
linux-perf-users, linux-kernel, Edward Baker, Perry Taylor,
Caleb Biggers, Stephane Eranian
On Thu, Apr 13, 2023 at 7:04 AM Arnaldo Carvalho de Melo
<acme@kernel.org> wrote:
>
> Em Thu, Apr 13, 2023 at 06:29:28AM -0700, Ian Rogers escreveu:
> > Update the uncore PMUs and topic classification as created by:
> > https://github.com/intel/perfmon/pull/70
> >
> > Event updates stem from:
> > https://github.com/intel/perfmon/pull/68
> > impacting alderlake, icelakex and sapphirerapids.
> >
> > Grand Ridge and Sierra Forest events stem from:
> > https://github.com/intel/perfmon/pull/69
> >
> > Changes generated by with PR70 in place:
> > https://github.com/intel/perfmon/blob/main/scripts/create_perf_json.py
> >
> > v3. Rebase over the update of alderlake and icelakex events.
> > v2. Adds improvements to uncore topics, uncore PMU name fixes and
> > fixes a trigraph issue from ??? being in the json.
>
> b4 isn't liking it:
>
> ⬢[acme@toolbox perf-tools-next]$ b4 am -ctsl --cc-trailers 20230413132949.3487664-1-irogers@google.com
> Grabbing thread from lore.kernel.org/all/20230413132949.3487664-1-irogers%40google.com/t.mbox.gz
> Checking for newer revisions
> Grabbing search results from lore.kernel.org
> Analyzing 14 messages in the thread
> Checking attestation on all messages, may take a moment...
> ---
> ERROR: missing [1/21]!
> ✓ [PATCH v3 2/21] perf vendor events intel: Add grandridge
> ✓ Signed: DKIM/google.com
> + Link: https://lore.kernel.org/r/20230413132949.3487664-3-irogers@google.com
> + Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com>
> ✓ [PATCH v3 3/21] perf vendor events intel: Add sierraforest
> ✓ Signed: DKIM/google.com
> + Link: https://lore.kernel.org/r/20230413132949.3487664-3-irogers@google.com
> + Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com>
> ✓ [PATCH v3 4/21] perf vendor events intel: Fix uncore topics for alderlake
> ✓ Signed: DKIM/google.com
> + Link: https://lore.kernel.org/r/20230413132949.3487664-3-irogers@google.com
> + Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com>
> ✓ [PATCH v3 5/21] perf vendor events intel: Fix uncore topics for broadwell
> ✓ Signed: DKIM/google.com
> + Link: https://lore.kernel.org/r/20230413132949.3487664-3-irogers@google.com
> + Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com>
> ✓ [PATCH v3 6/21] perf vendor events intel: Fix uncore topics for broadwellde
> ✓ Signed: DKIM/google.com
> + Link: https://lore.kernel.org/r/20230413132949.3487664-3-irogers@google.com
> + Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com>
> ERROR: missing [7/21]!
> ERROR: missing [8/21]!
> ✓ [PATCH v3 9/21] perf vendor events intel: Fix uncore topics for haswell
> ✓ Signed: DKIM/google.com
> + Link: https://lore.kernel.org/r/20230413132949.3487664-3-irogers@google.com
> + Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com>
> ERROR: missing [10/21]!
> ✓ [PATCH v3 11/21] perf vendor events intel: Fix uncore topics for icelake
> ✓ Signed: DKIM/google.com
> + Link: https://lore.kernel.org/r/20230413132949.3487664-3-irogers@google.com
> + Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com>
> ERROR: missing [12/21]!
> ✓ [PATCH v3 13/21] perf vendor events intel: Fix uncore topics for ivybridge
> ✓ Signed: DKIM/google.com
> + Link: https://lore.kernel.org/r/20230413132949.3487664-3-irogers@google.com
> + Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com>
> ERROR: missing [14/21]!
> ✓ [PATCH v3 15/21] perf vendor events intel: Fix uncore topics for jaketown
> ✓ Signed: DKIM/google.com
> + Link: https://lore.kernel.org/r/20230413132949.3487664-3-irogers@google.com
> + Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com>
> ✓ [PATCH v3 16/21] perf vendor events intel: Fix uncore topics for knightslanding
> ✓ Signed: DKIM/google.com
> + Link: https://lore.kernel.org/r/20230413132949.3487664-3-irogers@google.com
> + Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com>
> ✓ [PATCH v3 17/21] perf vendor events intel: Fix uncore topics for sandybridge
> ✓ Signed: DKIM/google.com
> + Link: https://lore.kernel.org/r/20230413132949.3487664-3-irogers@google.com
> + Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com>
> ✓ [PATCH v3 18/21] perf vendor events intel: Fix uncore topics for skylake
> ✓ Signed: DKIM/google.com
> + Link: https://lore.kernel.org/r/20230413132949.3487664-3-irogers@google.com
> + Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com>
> ERROR: missing [19/21]!
> ERROR: missing [20/21]!
> ✓ [PATCH v3 21/21] perf vendor events intel: Fix uncore topics for tigerlake
> ✓ Signed: DKIM/google.com
> + Link: https://lore.kernel.org/r/20230413132949.3487664-3-irogers@google.com
> + Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com>
> ---
> Total patches: 13
> ---
> WARNING: Thread incomplete!
> Cover: ./v3_20230413_irogers_update_uncore_topics_1x_event_updates_2x_new_archs.cover
> Link: https://lore.kernel.org/r/20230413132949.3487664-1-irogers@google.com
> Base: not specified
> git am ./v3_20230413_irogers_update_uncore_topics_1x_event_updates_2x_new_archs.mbx
> ⬢[acme@toolbox perf-tools-next]$
>
>
> Lemme try to update it to see if it copes... nope:
>
> ⬢[acme@toolbox b4]$ git pull
> Updating 041d10b7f628fa08..00303592f25693cb
> Fast-forward
> b4/__init__.py | 54 ++++++++++++++++++++++++++++++++----------------------
> b4/command.py | 4 ++--
> b4/ez.py | 15 ++++++++++++---
> b4/ty.py | 10 ++++++----
> docs/config.rst | 19 +++++++++++++++++++
> man/b4.5 | 6 +++++-
> man/b4.5.rst | 2 ++
> tests/samples/trailers-followup-with-cover-ref-addlink.txt | 67 +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
> tests/test___init__.py | 1 +
> 9 files changed, 146 insertions(+), 32 deletions(-)
> create mode 100644 tests/samples/trailers-followup-with-cover-ref-addlink.txt
> ⬢[acme@toolbox b4]$ git diff
> ⬢[acme@toolbox b4]$ cd -
> /var/home/acme/git/perf-tools-next
> ⬢[acme@toolbox perf-tools-next]$ b4 am -ctsl --cc-trailers 20230413132949.3487664-1-irogers@google.com
> Grabbing thread from lore.kernel.org/all/20230413132949.3487664-1-irogers%40google.com/t.mbox.gz
> Checking for newer revisions
> Grabbing search results from lore.kernel.org
> Analyzing 14 messages in the thread
> Checking attestation on all messages, may take a moment...
> ---
> ERROR: missing [1/21]!
> ✓ [PATCH v3 2/21] perf vendor events intel: Add grandridge
> ✓ Signed: DKIM/google.com
> + Link: https://lore.kernel.org/r/20230413132949.3487664-3-irogers@google.com
> + Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com>
> ✓ [PATCH v3 3/21] perf vendor events intel: Add sierraforest
> ✓ Signed: DKIM/google.com
> + Link: https://lore.kernel.org/r/20230413132949.3487664-4-irogers@google.com
> + Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com>
> ✓ [PATCH v3 4/21] perf vendor events intel: Fix uncore topics for alderlake
> ✓ Signed: DKIM/google.com
> + Link: https://lore.kernel.org/r/20230413132949.3487664-5-irogers@google.com
> + Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com>
> ✓ [PATCH v3 5/21] perf vendor events intel: Fix uncore topics for broadwell
> ✓ Signed: DKIM/google.com
> + Link: https://lore.kernel.org/r/20230413132949.3487664-6-irogers@google.com
> + Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com>
> ✓ [PATCH v3 6/21] perf vendor events intel: Fix uncore topics for broadwellde
> ✓ Signed: DKIM/google.com
> + Link: https://lore.kernel.org/r/20230413132949.3487664-7-irogers@google.com
> + Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com>
> ERROR: missing [7/21]!
> ERROR: missing [8/21]!
> ✓ [PATCH v3 9/21] perf vendor events intel: Fix uncore topics for haswell
> ✓ Signed: DKIM/google.com
> + Link: https://lore.kernel.org/r/20230413132949.3487664-10-irogers@google.com
> + Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com>
> ERROR: missing [10/21]!
> ✓ [PATCH v3 11/21] perf vendor events intel: Fix uncore topics for icelake
> ✓ Signed: DKIM/google.com
> + Link: https://lore.kernel.org/r/20230413132949.3487664-12-irogers@google.com
> + Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com>
> ERROR: missing [12/21]!
> ✓ [PATCH v3 13/21] perf vendor events intel: Fix uncore topics for ivybridge
> ✓ Signed: DKIM/google.com
> + Link: https://lore.kernel.org/r/20230413132949.3487664-14-irogers@google.com
> + Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com>
> ERROR: missing [14/21]!
> ✓ [PATCH v3 15/21] perf vendor events intel: Fix uncore topics for jaketown
> ✓ Signed: DKIM/google.com
> + Link: https://lore.kernel.org/r/20230413132949.3487664-16-irogers@google.com
> + Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com>
> ✓ [PATCH v3 16/21] perf vendor events intel: Fix uncore topics for knightslanding
> ✓ Signed: DKIM/google.com
> + Link: https://lore.kernel.org/r/20230413132949.3487664-17-irogers@google.com
> + Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com>
> ✓ [PATCH v3 17/21] perf vendor events intel: Fix uncore topics for sandybridge
> ✓ Signed: DKIM/google.com
> + Link: https://lore.kernel.org/r/20230413132949.3487664-18-irogers@google.com
> + Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com>
> ✓ [PATCH v3 18/21] perf vendor events intel: Fix uncore topics for skylake
> ✓ Signed: DKIM/google.com
> + Link: https://lore.kernel.org/r/20230413132949.3487664-19-irogers@google.com
> + Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com>
> ERROR: missing [19/21]!
> ERROR: missing [20/21]!
> ✓ [PATCH v3 21/21] perf vendor events intel: Fix uncore topics for tigerlake
> ✓ Signed: DKIM/google.com
> + Link: https://lore.kernel.org/r/20230413132949.3487664-22-irogers@google.com
> + Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com>
> ---
> Total patches: 13
> ---
> WARNING: Thread incomplete!
> Cover: ./v3_20230413_irogers_update_uncore_topics_1x_event_updates_2x_new_archs.cover
> Link: https://lore.kernel.org/r/20230413132949.3487664-1-irogers@google.com
> Base: not specified
> git am ./v3_20230413_irogers_update_uncore_topics_1x_event_updates_2x_new_archs.mbx
> ⬢[acme@toolbox perf-tools-next]$
>
Apologies for this. I think it is some size related LKML thing. All
the missing patches are > 0.5MB:
11438 v3-0000-cover-letter.patch
1176292 v3-0001-perf-vendor-events-intel-Update-sapphirerapids-to.patch
19044 v3-0002-perf-vendor-events-intel-Add-grandridge.patch
19106 v3-0003-perf-vendor-events-intel-Add-sierraforest.patch
11481 v3-0004-perf-vendor-events-intel-Fix-uncore-topics-for-al.patch
12384 v3-0005-perf-vendor-events-intel-Fix-uncore-topics-for-br.patch
152976 v3-0006-perf-vendor-events-intel-Fix-uncore-topics-for-br.patch
720813 v3-0007-perf-vendor-events-intel-Fix-uncore-topics-for-br.patch
2415854 v3-0008-perf-vendor-events-intel-Fix-uncore-topics-for-ca.patch
13924 v3-0009-perf-vendor-events-intel-Fix-uncore-topics-for-ha.patch
710442 v3-0010-perf-vendor-events-intel-Fix-uncore-topics-for-ha.patch
8000 v3-0011-perf-vendor-events-intel-Fix-uncore-topics-for-ic.patch
3660614 v3-0012-perf-vendor-events-intel-Fix-uncore-topics-for-ic.patch
8662 v3-0013-perf-vendor-events-intel-Fix-uncore-topics-for-iv.patch
516723 v3-0014-perf-vendor-events-intel-Fix-uncore-topics-for-iv.patch
299475 v3-0015-perf-vendor-events-intel-Fix-uncore-topics-for-ja.patch
23644 v3-0016-perf-vendor-events-intel-Fix-uncore-topics-for-kn.patch
8682 v3-0017-perf-vendor-events-intel-Fix-uncore-topics-for-sa.patch
11676 v3-0018-perf-vendor-events-intel-Fix-uncore-topics-for-sk.patch
2398312 v3-0019-perf-vendor-events-intel-Fix-uncore-topics-for-sk.patch
2378858 v3-0020-perf-vendor-events-intel-Fix-uncore-topics-for-sn.patch
8352 v3-0021-perf-vendor-events-intel-Fix-uncore-topics-for-ti.patch
I also see them missing on lore:
https://lore.kernel.org/lkml/20230413132949.3487664-1-irogers@google.com/
Hopefully somebody just needs to allow the patches through onto LKML.
Thanks,
Ian
^ permalink raw reply [flat|nested] 18+ messages in thread
* Re: [PATCH v3 00/21] Update uncore topics, 1x event updates, 2x new archs.
2023-04-13 14:04 ` [PATCH v3 00/21] Update uncore topics, 1x event updates, 2x new archs Arnaldo Carvalho de Melo
2023-04-13 15:34 ` Ian Rogers
@ 2023-04-14 8:18 ` Peter Zijlstra
2023-04-14 23:14 ` Ian Rogers
1 sibling, 1 reply; 18+ messages in thread
From: Peter Zijlstra @ 2023-04-14 8:18 UTC (permalink / raw)
To: Arnaldo Carvalho de Melo
Cc: Ian Rogers, Ingo Molnar, Mark Rutland, Alexander Shishkin,
Jiri Olsa, Namhyung Kim, Zhengjun Xing, Kan Liang,
linux-perf-users, linux-kernel, Edward Baker, Perry Taylor,
Caleb Biggers, Stephane Eranian
On Thu, Apr 13, 2023 at 11:04:05AM -0300, Arnaldo Carvalho de Melo wrote:
> Em Thu, Apr 13, 2023 at 06:29:28AM -0700, Ian Rogers escreveu:
> > Update the uncore PMUs and topic classification as created by:
> > https://github.com/intel/perfmon/pull/70
> >
> > Event updates stem from:
> > https://github.com/intel/perfmon/pull/68
> > impacting alderlake, icelakex and sapphirerapids.
> >
> > Grand Ridge and Sierra Forest events stem from:
> > https://github.com/intel/perfmon/pull/69
> >
> > Changes generated by with PR70 in place:
> > https://github.com/intel/perfmon/blob/main/scripts/create_perf_json.py
> >
> > v3. Rebase over the update of alderlake and icelakex events.
> > v2. Adds improvements to uncore topics, uncore PMU name fixes and
> > fixes a trigraph issue from ??? being in the json.
>
> b4 isn't liking it:
Fwiw, the way I've set up b4 it takes the patches from my local
mailstore and it doesn't matter what made it out to lkml. Specifically,
I pipe the patches from mutt directly into b4.
I think there's some information in the b4 docs on how to set that up,
but let me know if you want more info.
^ permalink raw reply [flat|nested] 18+ messages in thread
* Re: [PATCH v3 00/21] Update uncore topics, 1x event updates, 2x new archs.
2023-04-14 8:18 ` Peter Zijlstra
@ 2023-04-14 23:14 ` Ian Rogers
2023-04-15 0:07 ` Arnaldo Carvalho de Melo
0 siblings, 1 reply; 18+ messages in thread
From: Ian Rogers @ 2023-04-14 23:14 UTC (permalink / raw)
To: Peter Zijlstra
Cc: Arnaldo Carvalho de Melo, Ingo Molnar, Mark Rutland,
Alexander Shishkin, Jiri Olsa, Namhyung Kim, Zhengjun Xing,
Kan Liang, linux-perf-users, linux-kernel, Edward Baker,
Perry Taylor, Caleb Biggers, Stephane Eranian
On Fri, Apr 14, 2023 at 1:20 AM Peter Zijlstra <peterz@infradead.org> wrote:
>
> On Thu, Apr 13, 2023 at 11:04:05AM -0300, Arnaldo Carvalho de Melo wrote:
> > Em Thu, Apr 13, 2023 at 06:29:28AM -0700, Ian Rogers escreveu:
> > > Update the uncore PMUs and topic classification as created by:
> > > https://github.com/intel/perfmon/pull/70
> > >
> > > Event updates stem from:
> > > https://github.com/intel/perfmon/pull/68
> > > impacting alderlake, icelakex and sapphirerapids.
> > >
> > > Grand Ridge and Sierra Forest events stem from:
> > > https://github.com/intel/perfmon/pull/69
> > >
> > > Changes generated by with PR70 in place:
> > > https://github.com/intel/perfmon/blob/main/scripts/create_perf_json.py
> > >
> > > v3. Rebase over the update of alderlake and icelakex events.
> > > v2. Adds improvements to uncore topics, uncore PMU name fixes and
> > > fixes a trigraph issue from ??? being in the json.
> >
> > b4 isn't liking it:
>
> Fwiw, the way I've set up b4 it takes the patches from my local
> mailstore and it doesn't matter what made it out to lkml. Specifically,
> I pipe the patches from mutt directly into b4.
>
> I think there's some information in the b4 docs on how to set that up,
> but let me know if you want more info.
Thanks Peter! I'm using gmail for everything and I suspect I won't be
able to reproduce your setup easily. I think the right thing is for me
to set up a public git repository. I got about half-way through the
kernel.org documentation before getting distracted. I should finish it
off :-) Perhaps Arnaldo can use the set up though.
Thanks,
Ian
^ permalink raw reply [flat|nested] 18+ messages in thread
* Re: [PATCH v3 00/21] Update uncore topics, 1x event updates, 2x new archs.
2023-04-14 23:14 ` Ian Rogers
@ 2023-04-15 0:07 ` Arnaldo Carvalho de Melo
0 siblings, 0 replies; 18+ messages in thread
From: Arnaldo Carvalho de Melo @ 2023-04-15 0:07 UTC (permalink / raw)
To: Ian Rogers, Peter Zijlstra
Cc: Arnaldo Carvalho de Melo, Ingo Molnar, Mark Rutland,
Alexander Shishkin, Jiri Olsa, Namhyung Kim, Zhengjun Xing,
Kan Liang, linux-perf-users, linux-kernel, Edward Baker,
Perry Taylor, Caleb Biggers, Stephane Eranian
On April 14, 2023 8:14:54 PM GMT-03:00, Ian Rogers <irogers@google.com> wrote:
>On Fri, Apr 14, 2023 at 1:20 AM Peter Zijlstra <peterz@infradead.org> wrote:
>>
>> On Thu, Apr 13, 2023 at 11:04:05AM -0300, Arnaldo Carvalho de Melo wrote:
>> > Em Thu, Apr 13, 2023 at 06:29:28AM -0700, Ian Rogers escreveu:
>> > > Update the uncore PMUs and topic classification as created by:
>> > > https://github.com/intel/perfmon/pull/70
>> > >
>> > > Event updates stem from:
>> > > https://github.com/intel/perfmon/pull/68
>> > > impacting alderlake, icelakex and sapphirerapids.
>> > >
>> > > Grand Ridge and Sierra Forest events stem from:
>> > > https://github.com/intel/perfmon/pull/69
>> > >
>> > > Changes generated by with PR70 in place:
>> > > https://github.com/intel/perfmon/blob/main/scripts/create_perf_json.py
>> > >
>> > > v3. Rebase over the update of alderlake and icelakex events.
>> > > v2. Adds improvements to uncore topics, uncore PMU name fixes and
>> > > fixes a trigraph issue from ??? being in the json.
>> >
>> > b4 isn't liking it:
>>
>> Fwiw, the way I've set up b4 it takes the patches from my local
>> mailstore and it doesn't matter what made it out to lkml. Specifically,
>> I pipe the patches from mutt directly into b4.
>>
>> I think there's some information in the b4 docs on how to set that up,
>> but let me know if you want more info.
>
>Thanks Peter! I'm using gmail for everything and I suspect I won't be
>able to reproduce your setup easily. I think the right thing is for me
>to set up a public git repository. I got about half-way through the
>kernel.org documentation before getting distracted. I should finish it
>off :-) Perhaps Arnaldo can use the set up though.
Yeah, thanks for the info, I use mutt and will try Peter's B4 setup.
- Arnaldo
>Thanks,
>Ian
^ permalink raw reply [flat|nested] 18+ messages in thread
* Re: [PATCH v3 00/21] Update uncore topics, 1x event updates, 2x new archs.
2023-04-13 13:29 [PATCH v3 00/21] Update uncore topics, 1x event updates, 2x new archs Ian Rogers
` (11 preceding siblings ...)
2023-04-13 14:04 ` [PATCH v3 00/21] Update uncore topics, 1x event updates, 2x new archs Arnaldo Carvalho de Melo
@ 2023-04-13 21:57 ` Arnaldo Carvalho de Melo
12 siblings, 0 replies; 18+ messages in thread
From: Arnaldo Carvalho de Melo @ 2023-04-13 21:57 UTC (permalink / raw)
To: Ian Rogers
Cc: Peter Zijlstra, Ingo Molnar, Mark Rutland, Alexander Shishkin,
Jiri Olsa, Namhyung Kim, Zhengjun Xing, Kan Liang,
linux-perf-users, linux-kernel, Edward Baker, Perry Taylor,
Caleb Biggers, Stephane Eranian
Em Thu, Apr 13, 2023 at 06:29:28AM -0700, Ian Rogers escreveu:
> Update the uncore PMUs and topic classification as created by:
> https://github.com/intel/perfmon/pull/70
>
> Event updates stem from:
> https://github.com/intel/perfmon/pull/68
> impacting alderlake, icelakex and sapphirerapids.
>
> Grand Ridge and Sierra Forest events stem from:
> https://github.com/intel/perfmon/pull/69
>
> Changes generated by with PR70 in place:
> https://github.com/intel/perfmon/blob/main/scripts/create_perf_json.py
Thanks, pulling teeth but applied,
- Arnaldo
> v3. Rebase over the update of alderlake and icelakex events.
> v2. Adds improvements to uncore topics, uncore PMU name fixes and
> fixes a trigraph issue from ??? being in the json.
>
> Ian Rogers (21):
> perf vendor events intel: Update sapphirerapids to v1.12
> perf vendor events intel: Add grandridge
> perf vendor events intel: Add sierraforest
> perf vendor events intel: Fix uncore topics for alderlake
> perf vendor events intel: Fix uncore topics for broadwell
> perf vendor events intel: Fix uncore topics for broadwellde
> perf vendor events intel: Fix uncore topics for broadwellx
> perf vendor events intel: Fix uncore topics for cascadelakex
> perf vendor events intel: Fix uncore topics for haswell
> perf vendor events intel: Fix uncore topics for haswellx
> perf vendor events intel: Fix uncore topics for icelake
> perf vendor events intel: Fix uncore topics for icelakex
> perf vendor events intel: Fix uncore topics for ivybridge
> perf vendor events intel: Fix uncore topics for ivytown
> perf vendor events intel: Fix uncore topics for jaketown
> perf vendor events intel: Fix uncore topics for knightslanding
> perf vendor events intel: Fix uncore topics for sandybridge
> perf vendor events intel: Fix uncore topics for skylake
> perf vendor events intel: Fix uncore topics for skylakex
> perf vendor events intel: Fix uncore topics for snowridgex
> perf vendor events intel: Fix uncore topics for tigerlake
>
> .../x86/alderlake/uncore-interconnect.json | 90 +
> .../arch/x86/alderlake/uncore-other.json | 88 -
> .../x86/alderlaken/uncore-interconnect.json | 26 +
> .../arch/x86/alderlaken/uncore-other.json | 24 -
> .../arch/x86/broadwell/uncore-cache.json | 30 +-
> .../x86/broadwell/uncore-interconnect.json | 61 +
> .../arch/x86/broadwell/uncore-other.json | 59 -
> .../arch/x86/broadwellde/uncore-cache.json | 324 +-
> .../x86/broadwellde/uncore-interconnect.json | 614 +
> .../{uncore-other.json => uncore-io.json} | 612 -
> .../arch/x86/broadwellx/uncore-cache.json | 358 +-
> .../x86/broadwellx/uncore-interconnect.json | 4297 +-
> .../arch/x86/broadwellx/uncore-io.json | 555 +
> .../arch/x86/broadwellx/uncore-other.json | 3242 --
> .../arch/x86/cascadelakex/uncore-cache.json | 10764 +++++
> .../x86/cascadelakex/uncore-interconnect.json | 11334 ++++++
> .../arch/x86/cascadelakex/uncore-io.json | 4250 ++
> .../arch/x86/cascadelakex/uncore-memory.json | 2 +-
> .../arch/x86/cascadelakex/uncore-other.json | 26344 ------------
> .../pmu-events/arch/x86/grandridge/cache.json | 155 +
> .../arch/x86/grandridge/frontend.json | 16 +
> .../arch/x86/grandridge/memory.json | 20 +
> .../pmu-events/arch/x86/grandridge/other.json | 20 +
> .../arch/x86/grandridge/pipeline.json | 96 +
> .../arch/x86/grandridge/virtual-memory.json | 24 +
> .../arch/x86/haswell/uncore-cache.json | 50 +-
> .../arch/x86/haswell/uncore-interconnect.json | 52 +
> .../arch/x86/haswell/uncore-other.json | 50 -
> .../arch/x86/haswellx/uncore-cache.json | 360 +-
> .../x86/haswellx/uncore-interconnect.json | 4242 +-
> .../arch/x86/haswellx/uncore-io.json | 528 +
> .../arch/x86/haswellx/uncore-other.json | 3160 --
> .../arch/x86/icelake/uncore-interconnect.json | 74 +
> .../arch/x86/icelake/uncore-other.json | 72 -
> .../arch/x86/icelakex/uncore-cache.json | 9860 +++++
> .../x86/icelakex/uncore-interconnect.json | 14571 +++++++
> .../arch/x86/icelakex/uncore-io.json | 9270 +++++
> .../arch/x86/icelakex/uncore-other.json | 33697 ----------------
> .../arch/x86/ivybridge/uncore-cache.json | 50 +-
> ...re-other.json => uncore-interconnect.json} | 0
> .../arch/x86/ivytown/uncore-cache.json | 314 +-
> .../arch/x86/ivytown/uncore-interconnect.json | 2025 +-
> .../arch/x86/ivytown/uncore-io.json | 549 +
> .../arch/x86/ivytown/uncore-other.json | 2174 -
> .../arch/x86/jaketown/uncore-cache.json | 194 +-
> .../x86/jaketown/uncore-interconnect.json | 1237 +-
> .../arch/x86/jaketown/uncore-io.json | 324 +
> .../arch/x86/jaketown/uncore-other.json | 1393 -
> .../{uncore-other.json => uncore-cache.json} | 260 -
> .../arch/x86/knightslanding/uncore-io.json | 194 +
> .../x86/knightslanding/uncore-memory.json | 68 +
> tools/perf/pmu-events/arch/x86/mapfile.csv | 4 +-
> .../arch/x86/sandybridge/uncore-cache.json | 50 +-
> ...re-other.json => uncore-interconnect.json} | 0
> .../arch/x86/sapphirerapids/other.json | 3 +-
> .../arch/x86/sapphirerapids/pipeline.json | 4 +-
> .../arch/x86/sapphirerapids/uncore-cache.json | 5644 +++
> .../arch/x86/sapphirerapids/uncore-cxl.json | 450 +
> .../sapphirerapids/uncore-interconnect.json | 6199 +++
> .../arch/x86/sapphirerapids/uncore-io.json | 3651 ++
> .../x86/sapphirerapids/uncore-memory.json | 3283 +-
> .../arch/x86/sapphirerapids/uncore-other.json | 4525 ---
> .../arch/x86/sapphirerapids/uncore-power.json | 107 +
> .../arch/x86/sierraforest/cache.json | 155 +
> .../arch/x86/sierraforest/frontend.json | 16 +
> .../arch/x86/sierraforest/memory.json | 20 +
> .../arch/x86/sierraforest/other.json | 20 +
> .../arch/x86/sierraforest/pipeline.json | 96 +
> .../arch/x86/sierraforest/virtual-memory.json | 24 +
> .../arch/x86/skylake/uncore-cache.json | 28 +-
> .../arch/x86/skylake/uncore-interconnect.json | 67 +
> .../arch/x86/skylake/uncore-other.json | 65 -
> .../arch/x86/skylakex/uncore-cache.json | 10649 +++++
> .../x86/skylakex/uncore-interconnect.json | 11248 ++++++
> .../arch/x86/skylakex/uncore-io.json | 4250 ++
> .../arch/x86/skylakex/uncore-memory.json | 2 +-
> .../arch/x86/skylakex/uncore-other.json | 26143 ------------
> .../arch/x86/snowridgex/uncore-cache.json | 7100 ++++
> .../x86/snowridgex/uncore-interconnect.json | 6016 +++
> .../arch/x86/snowridgex/uncore-io.json | 8944 ++++
> .../arch/x86/snowridgex/uncore-other.json | 22056 ----------
> .../x86/tigerlake/uncore-interconnect.json | 90 +
> .../arch/x86/tigerlake/uncore-other.json | 88 -
> 83 files changed, 142122 insertions(+), 127048 deletions(-)
> create mode 100644 tools/perf/pmu-events/arch/x86/alderlake/uncore-interconnect.json
> create mode 100644 tools/perf/pmu-events/arch/x86/alderlaken/uncore-interconnect.json
> create mode 100644 tools/perf/pmu-events/arch/x86/broadwell/uncore-interconnect.json
> create mode 100644 tools/perf/pmu-events/arch/x86/broadwellde/uncore-interconnect.json
> rename tools/perf/pmu-events/arch/x86/broadwellde/{uncore-other.json => uncore-io.json} (53%)
> create mode 100644 tools/perf/pmu-events/arch/x86/broadwellx/uncore-io.json
> delete mode 100644 tools/perf/pmu-events/arch/x86/broadwellx/uncore-other.json
> create mode 100644 tools/perf/pmu-events/arch/x86/cascadelakex/uncore-cache.json
> create mode 100644 tools/perf/pmu-events/arch/x86/cascadelakex/uncore-interconnect.json
> create mode 100644 tools/perf/pmu-events/arch/x86/cascadelakex/uncore-io.json
> delete mode 100644 tools/perf/pmu-events/arch/x86/cascadelakex/uncore-other.json
> create mode 100644 tools/perf/pmu-events/arch/x86/grandridge/cache.json
> create mode 100644 tools/perf/pmu-events/arch/x86/grandridge/frontend.json
> create mode 100644 tools/perf/pmu-events/arch/x86/grandridge/memory.json
> create mode 100644 tools/perf/pmu-events/arch/x86/grandridge/other.json
> create mode 100644 tools/perf/pmu-events/arch/x86/grandridge/pipeline.json
> create mode 100644 tools/perf/pmu-events/arch/x86/grandridge/virtual-memory.json
> create mode 100644 tools/perf/pmu-events/arch/x86/haswell/uncore-interconnect.json
> create mode 100644 tools/perf/pmu-events/arch/x86/haswellx/uncore-io.json
> delete mode 100644 tools/perf/pmu-events/arch/x86/haswellx/uncore-other.json
> create mode 100644 tools/perf/pmu-events/arch/x86/icelake/uncore-interconnect.json
> create mode 100644 tools/perf/pmu-events/arch/x86/icelakex/uncore-cache.json
> create mode 100644 tools/perf/pmu-events/arch/x86/icelakex/uncore-interconnect.json
> create mode 100644 tools/perf/pmu-events/arch/x86/icelakex/uncore-io.json
> delete mode 100644 tools/perf/pmu-events/arch/x86/icelakex/uncore-other.json
> rename tools/perf/pmu-events/arch/x86/ivybridge/{uncore-other.json => uncore-interconnect.json} (100%)
> create mode 100644 tools/perf/pmu-events/arch/x86/ivytown/uncore-io.json
> delete mode 100644 tools/perf/pmu-events/arch/x86/ivytown/uncore-other.json
> create mode 100644 tools/perf/pmu-events/arch/x86/jaketown/uncore-io.json
> delete mode 100644 tools/perf/pmu-events/arch/x86/jaketown/uncore-other.json
> rename tools/perf/pmu-events/arch/x86/knightslanding/{uncore-other.json => uncore-cache.json} (91%)
> create mode 100644 tools/perf/pmu-events/arch/x86/knightslanding/uncore-io.json
> rename tools/perf/pmu-events/arch/x86/sandybridge/{uncore-other.json => uncore-interconnect.json} (100%)
> create mode 100644 tools/perf/pmu-events/arch/x86/sapphirerapids/uncore-cache.json
> create mode 100644 tools/perf/pmu-events/arch/x86/sapphirerapids/uncore-cxl.json
> create mode 100644 tools/perf/pmu-events/arch/x86/sapphirerapids/uncore-interconnect.json
> create mode 100644 tools/perf/pmu-events/arch/x86/sapphirerapids/uncore-io.json
> delete mode 100644 tools/perf/pmu-events/arch/x86/sapphirerapids/uncore-other.json
> create mode 100644 tools/perf/pmu-events/arch/x86/sierraforest/cache.json
> create mode 100644 tools/perf/pmu-events/arch/x86/sierraforest/frontend.json
> create mode 100644 tools/perf/pmu-events/arch/x86/sierraforest/memory.json
> create mode 100644 tools/perf/pmu-events/arch/x86/sierraforest/other.json
> create mode 100644 tools/perf/pmu-events/arch/x86/sierraforest/pipeline.json
> create mode 100644 tools/perf/pmu-events/arch/x86/sierraforest/virtual-memory.json
> create mode 100644 tools/perf/pmu-events/arch/x86/skylake/uncore-interconnect.json
> create mode 100644 tools/perf/pmu-events/arch/x86/skylakex/uncore-cache.json
> create mode 100644 tools/perf/pmu-events/arch/x86/skylakex/uncore-interconnect.json
> create mode 100644 tools/perf/pmu-events/arch/x86/skylakex/uncore-io.json
> delete mode 100644 tools/perf/pmu-events/arch/x86/skylakex/uncore-other.json
> create mode 100644 tools/perf/pmu-events/arch/x86/snowridgex/uncore-cache.json
> create mode 100644 tools/perf/pmu-events/arch/x86/snowridgex/uncore-interconnect.json
> create mode 100644 tools/perf/pmu-events/arch/x86/snowridgex/uncore-io.json
> delete mode 100644 tools/perf/pmu-events/arch/x86/snowridgex/uncore-other.json
> create mode 100644 tools/perf/pmu-events/arch/x86/tigerlake/uncore-interconnect.json
>
> --
> 2.40.0.577.gac1e443424-goog
>
--
- Arnaldo
^ permalink raw reply [flat|nested] 18+ messages in thread