From: Yu-Chien Peter Lin <peterlin@andestech.com>
To: "Clément Léger" <cleger@rivosinc.com>
Cc: <linux-riscv@lists.infradead.org>,
<linux-arm-kernel@lists.infradead.org>,
<linux-kernel@vger.kernel.org>,
<linux-perf-users@vger.kernel.org>, <paul.walmsley@sifive.com>,
<palmer@dabbelt.com>, <aou@eecs.berkeley.edu>,
<conor.dooley@microchip.com>, <atishp@atishpatra.org>,
<anup@brainfault.org>, <prabhakar.mahadev-lad.rj@bp.renesas.com>,
<ajones@ventanamicro.com>, <heiko@sntech.de>,
<samuel@sholland.org>, <geert+renesas@glider.be>,
<n.shubin@yadro.com>, <dminus@andestech.com>,
<ycliang@andestech.com>, <tim609@andestech.com>,
<locus84@andestech.com>, <dylan@andestech.com>
Subject: Re: [RFC PATCH 2/4] irqchip/riscv-intc: Support large non-standard hwirq number
Date: Mon, 11 Sep 2023 16:04:59 +0800 [thread overview]
Message-ID: <ZP7KKyjj6QObXAyb@APC323> (raw)
In-Reply-To: <ff6302ae-a114-4ef0-be87-a5fa34c3aab5@rivosinc.com>
On Thu, Sep 07, 2023 at 12:22:55PM +0200, Clément Léger wrote:
>
>
> On 07/09/2023 04:16, Yu Chien Peter Lin wrote:
> > Currently, the implementation of the RISC-V INTC driver uses the
> > interrupt cause as hwirq and has a limitation of supporting a
> > maximum of 64 hwirqs. However, according to the privileged spec,
> > interrupt cause >= 16 are defined for platform use.
> >
> > This limitation prevents us from fully utilizing the available
> > local interrupt sources. Additionally, the hwirqs used on RISC-V
> > are sparse, with only interrupt numbers 1, 5 and 9 (plus Sscofpmf
> > or T-Head's PMU irq) being currently used for supervisor mode.
> >
> > The patch switches to using irq_domain_create_tree() which
> > creates the radix tree map, allowing us to handle a larger
> > number of hwirqs.
> >
> > Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com>
> > Reviewed-by: Charles Ci-Jyun Wu <dminus@andestech.com>
> > Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
> >
> > ---
> > There are 3 hwirqs of local interrupt source exceed 64 defined in
> > AX45MP datasheet [1] Table 56: AX45MP-1C scause Value After Trap:
> > - 256+16 Slave port ECC error interrupt (S-mode)
> > - 256+17 Bus write transaction error interrupt (S-mode)
> > - 256+18 Performance monitor overflow interrupt(S-mode)
> >
> > [1] http://www.andestech.com/wp-content/uploads/AX45MP-1C-Rev.-5.0.0-Datasheet.pdf
> > ---
> > drivers/irqchip/irq-riscv-intc.c | 10 ++++------
> > 1 file changed, 4 insertions(+), 6 deletions(-)
> >
> > diff --git a/drivers/irqchip/irq-riscv-intc.c b/drivers/irqchip/irq-riscv-intc.c
> > index 4adeee1bc391..76e1229c45de 100644
> > --- a/drivers/irqchip/irq-riscv-intc.c
> > +++ b/drivers/irqchip/irq-riscv-intc.c
> > @@ -24,8 +24,8 @@ static asmlinkage void riscv_intc_irq(struct pt_regs *regs)
> > {
> > unsigned long cause = regs->cause & ~CAUSE_IRQ_FLAG;
> >
> > - if (unlikely(cause >= BITS_PER_LONG))
> > - panic("unexpected interrupt cause");
> > + if (!irq_find_mapping(intc_domain, cause))
> > + panic("unexpected interrupt cause: %ld", cause);
>
> Hi Yu,
>
> It seems like generic_handle_domain_irq() returns -EINVAL if provided
> with NULL (which will happen if the interrupt does not have a mapping
> due to __irq_resolve_mapping returning NULL) so maybe it is possible to
> remove this check (since __irq_resolve_mapping() is also called by
> generic_handle_domain_irq()) and panic if generic_handle_domain_irq()
> returns -EINVAL ? That would avoid calling __irq_resolve_mapping() twice
> for really rare cases.
>
> Clément
Hi Clément,
Thanks for catching this, will fix it in the patch v2.
Best regards,
Peter Lin
next prev parent reply other threads:[~2023-09-11 8:06 UTC|newest]
Thread overview: 15+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-09-07 2:16 [PATCH 0/4] Support Andes PMU extension Yu Chien Peter Lin
2023-09-07 2:16 ` [PATCH 1/4] riscv: errata: Rename defines for Andes Yu Chien Peter Lin
2023-09-07 2:16 ` [RFC PATCH 2/4] irqchip/riscv-intc: Support large non-standard hwirq number Yu Chien Peter Lin
2023-09-07 10:22 ` Clément Léger
2023-09-11 8:04 ` Yu-Chien Peter Lin [this message]
2023-09-07 13:06 ` Anup Patel
2023-09-11 8:12 ` Yu-Chien Peter Lin
2023-09-07 2:16 ` [PATCH 3/4] riscv: errata: Add Andes PMU errata Yu Chien Peter Lin
2023-09-07 2:48 ` Samuel Holland
2023-09-11 2:38 ` Yu-Chien Peter Lin
2023-09-07 9:27 ` Conor Dooley
2023-09-07 11:02 ` Conor Dooley
2023-09-11 2:48 ` Yu-Chien Peter Lin
2023-09-11 12:35 ` Conor Dooley
2023-09-07 2:16 ` [PATCH 4/4] riscv: andes: Support symbolic FW and HW raw events Yu Chien Peter Lin
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