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[31.46.241.231]) by smtp.gmail.com with ESMTPSA id b7-20020a1709062b4700b009ade1a4f795sm7687839ejg.168.2023.10.24.01.02.15 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 24 Oct 2023 01:02:16 -0700 (PDT) Sender: Ingo Molnar Date: Tue, 24 Oct 2023 10:02:13 +0200 From: Ingo Molnar To: Mario Limonciello Cc: Peter Zijlstra , Borislav Petkov , Thomas Gleixner , Dave Hansen , Sandipan Das , "H . Peter Anvin" , linux-kernel@vger.kernel.org, x86@kernel.org, linux-pm@vger.kernel.org, rafael@kernel.org, pavel@ucw.cz, linux-perf-users@vger.kernel.org, Ingo Molnar , Arnaldo Carvalho de Melo , Mark Rutland , Alexander Shishkin , Jiri Olsa , Namhyung Kim , Ian Rogers , Adrian Hunter Subject: Re: [PATCH 2/2] perf/x86/amd: Don't allow pre-emption in amd_pmu_lbr_reset() Message-ID: References: <20231023160018.164054-1-mario.limonciello@amd.com> <20231023160018.164054-3-mario.limonciello@amd.com> Precedence: bulk X-Mailing-List: linux-perf-users@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20231023160018.164054-3-mario.limonciello@amd.com> * Mario Limonciello wrote: > Fixes a BUG reported during suspend to ram testing. > > ``` > [ 478.274752] BUG: using smp_processor_id() in preemptible [00000000] code: rtcwake/2948 > [ 478.274754] caller is amd_pmu_lbr_reset+0x19/0xc0 > ``` > > Cc: stable@vger.kernel.org # 6.1+ > Fixes: ca5b7c0d9621 ("perf/x86/amd/lbr: Add LbrExtV2 branch record support") > Signed-off-by: Mario Limonciello > --- > arch/x86/events/amd/lbr.c | 3 ++- > 1 file changed, 2 insertions(+), 1 deletion(-) > > diff --git a/arch/x86/events/amd/lbr.c b/arch/x86/events/amd/lbr.c > index eb31f850841a..5b98e8c7d8b7 100644 > --- a/arch/x86/events/amd/lbr.c > +++ b/arch/x86/events/amd/lbr.c > @@ -321,7 +321,7 @@ int amd_pmu_lbr_hw_config(struct perf_event *event) > > void amd_pmu_lbr_reset(void) > { > - struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); > + struct cpu_hw_events *cpuc = get_cpu_ptr(&cpu_hw_events); > int i; > > if (!x86_pmu.lbr_nr) > @@ -335,6 +335,7 @@ void amd_pmu_lbr_reset(void) > > cpuc->last_task_ctx = NULL; > cpuc->last_log_id = 0; > + put_cpu_ptr(&cpu_hw_events); > wrmsrl(MSR_AMD64_LBR_SELECT, 0); > } Weird, amd_pmu_lbr_reset() is called from these places: - amd_pmu_lbr_sched_task(): during task sched-in during context-switching, this should already have preemption disabled. - amd_pmu_lbr_add(): this gets indirectly called by amd_pmu::add (amd_pmu_add_event()), called by event_sched_in(), which too should have preemption disabled. I clearly must have missed some additional place it gets called in. Could you please cite the full log of the amd_pmu_lbr_reset() call that caused the critical section warning? Thanks, Ingo