From mboxrd@z Thu Jan 1 00:00:00 1970 Authentication-Results: smtp.subspace.kernel.org; dkim=none Received: from Atcsqr.andestech.com (60-248-80-70.hinet-ip.hinet.net [60.248.80.70]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id EE35E10C2; Thu, 30 Nov 2023 01:23:40 -0800 (PST) Received: from mail.andestech.com (ATCPCS16.andestech.com [10.0.1.222]) by Atcsqr.andestech.com with ESMTP id 3AU9L7OD077461; Thu, 30 Nov 2023 17:21:07 +0800 (+08) (envelope-from peterlin@andestech.com) Received: from APC323 (10.0.12.98) by ATCPCS16.andestech.com (10.0.1.222) with Microsoft SMTP Server id 14.3.498.0; Thu, 30 Nov 2023 17:21:04 +0800 Date: Thu, 30 Nov 2023 17:21:01 +0800 From: Yu-Chien Peter Lin To: Inochi Amaoto CC: Guo Ren , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , Subject: Re: [PATCH v4 09/13] dt-bindings: riscv: Add T-Head PMU extension description Message-ID: References: Precedence: bulk X-Mailing-List: linux-perf-users@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: User-Agent: Mutt/2.2.10 (2023-03-25) X-DNSRBL: X-SPAM-SOURCE-CHECK: pass X-MAIL:Atcsqr.andestech.com 3AU9L7OD077461 Hi Inochi, On Thu, Nov 30, 2023 at 04:29:22PM +0800, Inochi Amaoto wrote: > > > >Hi Guo Ren, > > > >On Thu, Nov 23, 2023 at 05:14:30AM +0800, Guo Ren wrote: > >> On Wed, Nov 22, 2023 at 8:17 PM Yu Chien Peter Lin > >> wrote: > >>> > >>> Document the ISA string for T-Head performance monitor extension > >>> which provides counter overflow interrupt mechanism. > >>> > >>> Signed-off-by: Yu Chien Peter Lin > >>> --- > >>> Changes v2 -> v3: > >>> - New patch > >>> Changes v3 -> v4: > >>> - No change > >>> --- > >>> Documentation/devicetree/bindings/riscv/extensions.yaml | 6 ++++++ > >>> 1 file changed, 6 insertions(+) > >>> > >>> diff --git a/Documentation/devicetree/bindings/riscv/extensions.yaml b/Documentation/devicetree/bindings/riscv/extensions.yaml > >>> index c91ab0e46648..694efaea8fce 100644 > >>> --- a/Documentation/devicetree/bindings/riscv/extensions.yaml > >>> +++ b/Documentation/devicetree/bindings/riscv/extensions.yaml > >>> @@ -258,5 +258,11 @@ properties: > >>> in commit 2e5236 ("Ztso is now ratified.") of the > >>> riscv-isa-manual. > >>> > >>> + - const: xtheadpmu > >>> + description: > >>> + The T-Head performance monitor extension for counter overflow. For more > >>> + details, see the chapter 12 in the Xuantie C906 user manual. > >>> + https://github.com/T-head-Semi/openc906/tree/main/doc > >>> + > >>> additionalProperties: true > >>> ... > >>> -- > >>> 2.34.1 > >>> > >> Reviewed-by: Guo Ren > > > >Thanks for the review. > >Would you share document about T-Head PMU? > > > > Hi, Peter Lin: > > You can use the following two document to get all events: > https://github.com/T-head-Semi/openc906/tree/main/doc > https://github.com/T-head-Semi/openc910/tree/main/doc > > There are also some RTL code can describe these events: > https://github.com/T-head-Semi/openc910/blob/e0c4ad8ec7f8c70f649d826ebd6c949086453272/C910_RTL_FACTORY/gen_rtl/pmu/rtl/ct_hpcp_top.v#L1123 > https://github.com/T-head-Semi/openc906/blob/af5614d72de7e5a4b8609c427d2e20af1deb21c4/C906_RTL_FACTORY/gen_rtl/pmu/rtl/aq_hpcp_top.v#L543 > > The perf events json can also be used as document, this is already > applied (with more detailed explanation): > https://lore.kernel.org/all/IA1PR20MB495325FCF603BAA841E29281BBBAA@IA1PR20MB4953.namprd20.prod.outlook.com/ Thanks for reaching out! The updated description will be: - const: xtheadpmu description: The T-Head performance monitor extension for counter overflow, as ratified in commit bd9206 ("Initial commit") of Xuantie C906 user manual. https://github.com/T-head-Semi/openc906/tree/main/doc Is it OK with you? Best regards, Peter Lin > Best regards, > Inochi