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AJvYcCXbbw2Jn45z4J4p6Td//7G8XaxWcdkDYKrcNvnsThyHMYeQrqs0ZG39Bsl01Jn2iyJvVCvddOU/W/S8z4Dl2CPka/dQsr9L1swhHYCAuHtwUA== X-Gm-Message-State: AOJu0YyChArqgGFQJZPuocqC8OFuyuD6yjNspFHpdmSBq+xqxSGjkDvw cD6yV5owC0SW0wRUAm4lxg3F03ruiJYbFKbfJZ9e8vFcn38/dOcT/PsZWWOpZUEzqQPSAPkBTup DoQ== X-Google-Smtp-Source: AGHT+IGLnJWSe1pvT4fYPO2ARANLiP/Na43gje8HhGRqItkZXxuLiueYxnrbicDCpCBuUCuFLqQcY6Xcom8= X-Received: from zagreus.c.googlers.com ([fda3:e722:ac3:cc00:7f:e700:c0a8:5c37]) (user=seanjc job=sendgmr) by 2002:a17:90a:e213:b0:2a5:c05e:6e3d with SMTP id a19-20020a17090ae21300b002a5c05e6e3dmr2191pjz.0.1712870603948; Thu, 11 Apr 2024 14:23:23 -0700 (PDT) Date: Thu, 11 Apr 2024 14:23:22 -0700 In-Reply-To: <20240126085444.324918-19-xiong.y.zhang@linux.intel.com> Precedence: bulk X-Mailing-List: linux-perf-users@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Mime-Version: 1.0 References: <20240126085444.324918-1-xiong.y.zhang@linux.intel.com> <20240126085444.324918-19-xiong.y.zhang@linux.intel.com> Message-ID: Subject: Re: [RFC PATCH 18/41] KVM: x86/pmu: Intercept full-width GP counter MSRs by checking with perf capabilities From: Sean Christopherson To: Xiong Zhang Cc: pbonzini@redhat.com, peterz@infradead.org, mizhang@google.com, kan.liang@intel.com, zhenyuw@linux.intel.com, dapeng1.mi@linux.intel.com, jmattson@google.com, kvm@vger.kernel.org, linux-perf-users@vger.kernel.org, linux-kernel@vger.kernel.org, zhiyuan.lv@intel.com, eranian@google.com, irogers@google.com, samantha.alt@intel.com, like.xu.linux@gmail.com, chao.gao@intel.com, Xiong Zhang Content-Type: text/plain; charset="us-ascii" On Fri, Jan 26, 2024, Xiong Zhang wrote: > From: Mingwei Zhang > > Intercept full-width GP counter MSRs in passthrough PMU if guest does not > have the capability to write in full-width. In addition, opportunistically > add a warning if non-full-width counter MSRs are also intercepted, in which > case it is a clear mistake. > > Co-developed-by: Xiong Zhang > Signed-off-by: Xiong Zhang > Signed-off-by: Mingwei Zhang > --- > arch/x86/kvm/vmx/pmu_intel.c | 10 +++++++++- > 1 file changed, 9 insertions(+), 1 deletion(-) > > diff --git a/arch/x86/kvm/vmx/pmu_intel.c b/arch/x86/kvm/vmx/pmu_intel.c > index 7f6cabb2c378..49df154fbb5b 100644 > --- a/arch/x86/kvm/vmx/pmu_intel.c > +++ b/arch/x86/kvm/vmx/pmu_intel.c > @@ -429,6 +429,13 @@ static int intel_pmu_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info) > default: > if ((pmc = get_gp_pmc(pmu, msr, MSR_IA32_PERFCTR0)) || > (pmc = get_gp_pmc(pmu, msr, MSR_IA32_PMC0))) { > + if (is_passthrough_pmu_enabled(vcpu) && > + !(msr & MSR_PMC_FULL_WIDTH_BIT) && > + !msr_info->host_initiated) { > + pr_warn_once("passthrough PMU never intercepts non-full-width PMU counters\n"); > + return 1; This is broken, KVM must be prepared to handle WRMSR (and RDMSR and RDPMC) that come in through the emulator.