* [PATCH 0/7] perf vendor events riscv: Update SiFive CPU PMU events
@ 2024-05-09 2:14 Samuel Holland
2024-05-09 2:14 ` [PATCH 1/7] perf vendor events riscv: Rename U74 to Bullet Samuel Holland
` (7 more replies)
0 siblings, 8 replies; 9+ messages in thread
From: Samuel Holland @ 2024-05-09 2:14 UTC (permalink / raw)
To: Arnaldo Carvalho de Melo, Palmer Dabbelt, linux-perf-users,
linux-riscv
Cc: Mark Rutland, Adrian Hunter, Alexander Shishkin, Jiri Olsa,
Peter Zijlstra, Ingo Molnar, Ian Rogers, Namhyung Kim,
Arnaldo Carvalho de Melo, Samuel Holland
This series updates the PMU event JSON files to add support for newer
SiFive CPUs, including those used in the upcoming HiFive Premier P550
board. Since most changes are incremental, symbolic links are used when
a set of events is unchanged from the previous CPU series.
Eric Lin (5):
perf vendor events riscv: Update SiFive Bullet events
perf vendor events riscv: Add SiFive Bullet version 0x07 events
perf vendor events riscv: Add SiFive Bullet version 0x0d events
perf vendor events riscv: Add SiFive P550 events
perf vendor events riscv: Add SiFive P650 events
Samuel Holland (2):
perf vendor events riscv: Rename U74 to Bullet
perf vendor events riscv: Remove leading zeroes
tools/perf/pmu-events/arch/riscv/mapfile.csv | 6 +-
.../cycle-and-instruction-count.json | 12 +++
.../arch/riscv/sifive/bullet-07/firmware.json | 1 +
.../riscv/sifive/bullet-07/instruction.json | 1 +
.../arch/riscv/sifive/bullet-07/memory.json | 1 +
.../riscv/sifive/bullet-07/microarch.json | 62 +++++++++++++
.../riscv/sifive/bullet-07/watchpoint.json | 42 +++++++++
.../cycle-and-instruction-count.json | 1 +
.../arch/riscv/sifive/bullet-0d/firmware.json | 1 +
.../riscv/sifive/bullet-0d/instruction.json | 1 +
.../arch/riscv/sifive/bullet-0d/memory.json | 1 +
.../riscv/sifive/bullet-0d/microarch.json | 72 +++++++++++++++
.../riscv/sifive/bullet-0d/watchpoint.json | 1 +
.../sifive/{u74 => bullet}/firmware.json | 0
.../arch/riscv/sifive/bullet/instruction.json | 92 +++++++++++++++++++
.../arch/riscv/sifive/bullet/memory.json | 32 +++++++
.../arch/riscv/sifive/bullet/microarch.json | 57 ++++++++++++
.../arch/riscv/sifive/p550/firmware.json | 1 +
.../arch/riscv/sifive/p550/instruction.json | 1 +
.../arch/riscv/sifive/p550/memory.json | 47 ++++++++++
.../arch/riscv/sifive/p550/microarch.json | 1 +
.../p650/cycle-and-instruction-count.json | 1 +
.../arch/riscv/sifive/p650/firmware.json | 1 +
.../arch/riscv/sifive/p650/instruction.json | 1 +
.../arch/riscv/sifive/p650/memory.json | 57 ++++++++++++
.../arch/riscv/sifive/p650/microarch.json | 62 +++++++++++++
.../arch/riscv/sifive/p650/watchpoint.json | 1 +
.../arch/riscv/sifive/u74/instructions.json | 92 -------------------
.../arch/riscv/sifive/u74/memory.json | 32 -------
.../arch/riscv/sifive/u74/microarch.json | 57 ------------
30 files changed, 555 insertions(+), 182 deletions(-)
create mode 100644 tools/perf/pmu-events/arch/riscv/sifive/bullet-07/cycle-and-instruction-count.json
create mode 120000 tools/perf/pmu-events/arch/riscv/sifive/bullet-07/firmware.json
create mode 120000 tools/perf/pmu-events/arch/riscv/sifive/bullet-07/instruction.json
create mode 120000 tools/perf/pmu-events/arch/riscv/sifive/bullet-07/memory.json
create mode 100644 tools/perf/pmu-events/arch/riscv/sifive/bullet-07/microarch.json
create mode 100644 tools/perf/pmu-events/arch/riscv/sifive/bullet-07/watchpoint.json
create mode 120000 tools/perf/pmu-events/arch/riscv/sifive/bullet-0d/cycle-and-instruction-count.json
create mode 120000 tools/perf/pmu-events/arch/riscv/sifive/bullet-0d/firmware.json
create mode 120000 tools/perf/pmu-events/arch/riscv/sifive/bullet-0d/instruction.json
create mode 120000 tools/perf/pmu-events/arch/riscv/sifive/bullet-0d/memory.json
create mode 100644 tools/perf/pmu-events/arch/riscv/sifive/bullet-0d/microarch.json
create mode 120000 tools/perf/pmu-events/arch/riscv/sifive/bullet-0d/watchpoint.json
rename tools/perf/pmu-events/arch/riscv/sifive/{u74 => bullet}/firmware.json (100%)
create mode 100644 tools/perf/pmu-events/arch/riscv/sifive/bullet/instruction.json
create mode 100644 tools/perf/pmu-events/arch/riscv/sifive/bullet/memory.json
create mode 100644 tools/perf/pmu-events/arch/riscv/sifive/bullet/microarch.json
create mode 120000 tools/perf/pmu-events/arch/riscv/sifive/p550/firmware.json
create mode 120000 tools/perf/pmu-events/arch/riscv/sifive/p550/instruction.json
create mode 100644 tools/perf/pmu-events/arch/riscv/sifive/p550/memory.json
create mode 120000 tools/perf/pmu-events/arch/riscv/sifive/p550/microarch.json
create mode 120000 tools/perf/pmu-events/arch/riscv/sifive/p650/cycle-and-instruction-count.json
create mode 120000 tools/perf/pmu-events/arch/riscv/sifive/p650/firmware.json
create mode 120000 tools/perf/pmu-events/arch/riscv/sifive/p650/instruction.json
create mode 100644 tools/perf/pmu-events/arch/riscv/sifive/p650/memory.json
create mode 100644 tools/perf/pmu-events/arch/riscv/sifive/p650/microarch.json
create mode 120000 tools/perf/pmu-events/arch/riscv/sifive/p650/watchpoint.json
delete mode 100644 tools/perf/pmu-events/arch/riscv/sifive/u74/instructions.json
delete mode 100644 tools/perf/pmu-events/arch/riscv/sifive/u74/memory.json
delete mode 100644 tools/perf/pmu-events/arch/riscv/sifive/u74/microarch.json
--
2.44.0
^ permalink raw reply [flat|nested] 9+ messages in thread
* [PATCH 1/7] perf vendor events riscv: Rename U74 to Bullet
2024-05-09 2:14 [PATCH 0/7] perf vendor events riscv: Update SiFive CPU PMU events Samuel Holland
@ 2024-05-09 2:14 ` Samuel Holland
2024-05-09 2:14 ` [PATCH 2/7] perf vendor events riscv: Remove leading zeroes Samuel Holland
` (6 subsequent siblings)
7 siblings, 0 replies; 9+ messages in thread
From: Samuel Holland @ 2024-05-09 2:14 UTC (permalink / raw)
To: Arnaldo Carvalho de Melo, Palmer Dabbelt, linux-perf-users,
linux-riscv
Cc: Mark Rutland, Adrian Hunter, Alexander Shishkin, Jiri Olsa,
Peter Zijlstra, Ingo Molnar, Ian Rogers, Namhyung Kim,
Arnaldo Carvalho de Melo, Samuel Holland
This set of PMU event descriptions applies not only to the SiFive U74
core configuration, but also to other SiFive cores that implement the
Bullet microarchitecture (such as U64, P270, and X280). Rename the
directory to be more generic.
Signed-off-by: Samuel Holland <samuel.holland@sifive.com>
---
tools/perf/pmu-events/arch/riscv/mapfile.csv | 2 +-
.../pmu-events/arch/riscv/sifive/{u74 => bullet}/firmware.json | 0
.../sifive/{u74/instructions.json => bullet/instruction.json} | 0
.../pmu-events/arch/riscv/sifive/{u74 => bullet}/memory.json | 0
.../pmu-events/arch/riscv/sifive/{u74 => bullet}/microarch.json | 0
5 files changed, 1 insertion(+), 1 deletion(-)
rename tools/perf/pmu-events/arch/riscv/sifive/{u74 => bullet}/firmware.json (100%)
rename tools/perf/pmu-events/arch/riscv/sifive/{u74/instructions.json => bullet/instruction.json} (100%)
rename tools/perf/pmu-events/arch/riscv/sifive/{u74 => bullet}/memory.json (100%)
rename tools/perf/pmu-events/arch/riscv/sifive/{u74 => bullet}/microarch.json (100%)
diff --git a/tools/perf/pmu-events/arch/riscv/mapfile.csv b/tools/perf/pmu-events/arch/riscv/mapfile.csv
index 3d3a809a5446..521f416b0006 100644
--- a/tools/perf/pmu-events/arch/riscv/mapfile.csv
+++ b/tools/perf/pmu-events/arch/riscv/mapfile.csv
@@ -14,7 +14,7 @@
#
#
#MVENDORID-MARCHID-MIMPID,Version,Filename,EventType
-0x489-0x8000000000000007-0x[[:xdigit:]]+,v1,sifive/u74,core
+0x489-0x8000000000000007-0x[[:xdigit:]]+,v1,sifive/bullet,core
0x5b7-0x0-0x0,v1,thead/c900-legacy,core
0x67e-0x80000000db0000[89]0-0x[[:xdigit:]]+,v1,starfive/dubhe-80,core
0x31e-0x8000000000008a45-0x[[:xdigit:]]+,v1,andes/ax45,core
diff --git a/tools/perf/pmu-events/arch/riscv/sifive/u74/firmware.json b/tools/perf/pmu-events/arch/riscv/sifive/bullet/firmware.json
similarity index 100%
rename from tools/perf/pmu-events/arch/riscv/sifive/u74/firmware.json
rename to tools/perf/pmu-events/arch/riscv/sifive/bullet/firmware.json
diff --git a/tools/perf/pmu-events/arch/riscv/sifive/u74/instructions.json b/tools/perf/pmu-events/arch/riscv/sifive/bullet/instruction.json
similarity index 100%
rename from tools/perf/pmu-events/arch/riscv/sifive/u74/instructions.json
rename to tools/perf/pmu-events/arch/riscv/sifive/bullet/instruction.json
diff --git a/tools/perf/pmu-events/arch/riscv/sifive/u74/memory.json b/tools/perf/pmu-events/arch/riscv/sifive/bullet/memory.json
similarity index 100%
rename from tools/perf/pmu-events/arch/riscv/sifive/u74/memory.json
rename to tools/perf/pmu-events/arch/riscv/sifive/bullet/memory.json
diff --git a/tools/perf/pmu-events/arch/riscv/sifive/u74/microarch.json b/tools/perf/pmu-events/arch/riscv/sifive/bullet/microarch.json
similarity index 100%
rename from tools/perf/pmu-events/arch/riscv/sifive/u74/microarch.json
rename to tools/perf/pmu-events/arch/riscv/sifive/bullet/microarch.json
--
2.44.0
^ permalink raw reply related [flat|nested] 9+ messages in thread
* [PATCH 2/7] perf vendor events riscv: Remove leading zeroes
2024-05-09 2:14 [PATCH 0/7] perf vendor events riscv: Update SiFive CPU PMU events Samuel Holland
2024-05-09 2:14 ` [PATCH 1/7] perf vendor events riscv: Rename U74 to Bullet Samuel Holland
@ 2024-05-09 2:14 ` Samuel Holland
2024-05-09 2:14 ` [PATCH 3/7] perf vendor events riscv: Update SiFive Bullet events Samuel Holland
` (5 subsequent siblings)
7 siblings, 0 replies; 9+ messages in thread
From: Samuel Holland @ 2024-05-09 2:14 UTC (permalink / raw)
To: Arnaldo Carvalho de Melo, Palmer Dabbelt, linux-perf-users,
linux-riscv
Cc: Mark Rutland, Adrian Hunter, Alexander Shishkin, Jiri Olsa,
Peter Zijlstra, Ingo Molnar, Ian Rogers, Namhyung Kim,
Arnaldo Carvalho de Melo, Samuel Holland
The EventCode field (as stored in the mhpmeventN CSRs) is actually 56
bits wide, but there is no need to keep leading zeroes in the JSON
files. Remove them to simplify review of the following change, which
regenerates the files in a way that does not include leading zeroes.
This change was performed automatically with `sed -i "s/0x0*/0x/"`.
Signed-off-by: Samuel Holland <samuel.holland@sifive.com>
---
.../arch/riscv/sifive/bullet/instruction.json | 32 +++++++++----------
.../arch/riscv/sifive/bullet/memory.json | 12 +++----
.../arch/riscv/sifive/bullet/microarch.json | 22 ++++++-------
3 files changed, 33 insertions(+), 33 deletions(-)
diff --git a/tools/perf/pmu-events/arch/riscv/sifive/bullet/instruction.json b/tools/perf/pmu-events/arch/riscv/sifive/bullet/instruction.json
index 5eab718c9256..d5c370f70819 100644
--- a/tools/perf/pmu-events/arch/riscv/sifive/bullet/instruction.json
+++ b/tools/perf/pmu-events/arch/riscv/sifive/bullet/instruction.json
@@ -1,82 +1,82 @@
[
{
"EventName": "EXCEPTION_TAKEN",
- "EventCode": "0x0000100",
+ "EventCode": "0x100",
"BriefDescription": "Exception taken"
},
{
"EventName": "INTEGER_LOAD_RETIRED",
- "EventCode": "0x0000200",
+ "EventCode": "0x200",
"BriefDescription": "Integer load instruction retired"
},
{
"EventName": "INTEGER_STORE_RETIRED",
- "EventCode": "0x0000400",
+ "EventCode": "0x400",
"BriefDescription": "Integer store instruction retired"
},
{
"EventName": "ATOMIC_MEMORY_RETIRED",
- "EventCode": "0x0000800",
+ "EventCode": "0x800",
"BriefDescription": "Atomic memory operation retired"
},
{
"EventName": "SYSTEM_INSTRUCTION_RETIRED",
- "EventCode": "0x0001000",
+ "EventCode": "0x1000",
"BriefDescription": "System instruction retired"
},
{
"EventName": "INTEGER_ARITHMETIC_RETIRED",
- "EventCode": "0x0002000",
+ "EventCode": "0x2000",
"BriefDescription": "Integer arithmetic instruction retired"
},
{
"EventName": "CONDITIONAL_BRANCH_RETIRED",
- "EventCode": "0x0004000",
+ "EventCode": "0x4000",
"BriefDescription": "Conditional branch retired"
},
{
"EventName": "JAL_INSTRUCTION_RETIRED",
- "EventCode": "0x0008000",
+ "EventCode": "0x8000",
"BriefDescription": "JAL instruction retired"
},
{
"EventName": "JALR_INSTRUCTION_RETIRED",
- "EventCode": "0x0010000",
+ "EventCode": "0x10000",
"BriefDescription": "JALR instruction retired"
},
{
"EventName": "INTEGER_MULTIPLICATION_RETIRED",
- "EventCode": "0x0020000",
+ "EventCode": "0x20000",
"BriefDescription": "Integer multiplication instruction retired"
},
{
"EventName": "INTEGER_DIVISION_RETIRED",
- "EventCode": "0x0040000",
+ "EventCode": "0x40000",
"BriefDescription": "Integer division instruction retired"
},
{
"EventName": "FP_LOAD_RETIRED",
- "EventCode": "0x0080000",
+ "EventCode": "0x80000",
"BriefDescription": "Floating-point load instruction retired"
},
{
"EventName": "FP_STORE_RETIRED",
- "EventCode": "0x0100000",
+ "EventCode": "0x100000",
"BriefDescription": "Floating-point store instruction retired"
},
{
"EventName": "FP_ADDITION_RETIRED",
- "EventCode": "0x0200000",
+ "EventCode": "0x200000",
"BriefDescription": "Floating-point addition retired"
},
{
"EventName": "FP_MULTIPLICATION_RETIRED",
- "EventCode": "0x0400000",
+ "EventCode": "0x400000",
"BriefDescription": "Floating-point multiplication retired"
},
{
"EventName": "FP_FUSEDMADD_RETIRED",
- "EventCode": "0x0800000",
+ "EventCode": "0x800000",
"BriefDescription": "Floating-point fused multiply-add retired"
},
{
diff --git a/tools/perf/pmu-events/arch/riscv/sifive/bullet/memory.json b/tools/perf/pmu-events/arch/riscv/sifive/bullet/memory.json
index be1a46312ac3..ba3168f8a4cd 100644
--- a/tools/perf/pmu-events/arch/riscv/sifive/bullet/memory.json
+++ b/tools/perf/pmu-events/arch/riscv/sifive/bullet/memory.json
@@ -1,32 +1,32 @@
[
{
"EventName": "ICACHE_RETIRED",
- "EventCode": "0x0000102",
+ "EventCode": "0x102",
"BriefDescription": "Instruction cache miss"
},
{
"EventName": "DCACHE_MISS_MMIO_ACCESSES",
- "EventCode": "0x0000202",
+ "EventCode": "0x202",
"BriefDescription": "Data cache miss or memory-mapped I/O access"
},
{
"EventName": "DCACHE_WRITEBACK",
- "EventCode": "0x0000402",
+ "EventCode": "0x402",
"BriefDescription": "Data cache write-back"
},
{
"EventName": "INST_TLB_MISS",
- "EventCode": "0x0000802",
+ "EventCode": "0x802",
"BriefDescription": "Instruction TLB miss"
},
{
"EventName": "DATA_TLB_MISS",
- "EventCode": "0x0001002",
+ "EventCode": "0x1002",
"BriefDescription": "Data TLB miss"
},
{
"EventName": "UTLB_MISS",
- "EventCode": "0x0002002",
+ "EventCode": "0x2002",
"BriefDescription": "UTLB miss"
}
]
\ No newline at end of file
diff --git a/tools/perf/pmu-events/arch/riscv/sifive/bullet/microarch.json b/tools/perf/pmu-events/arch/riscv/sifive/bullet/microarch.json
index 50ffa55418cb..8036e72fb0d4 100644
--- a/tools/perf/pmu-events/arch/riscv/sifive/bullet/microarch.json
+++ b/tools/perf/pmu-events/arch/riscv/sifive/bullet/microarch.json
@@ -1,57 +1,57 @@
[
{
"EventName": "ADDRESSGEN_INTERLOCK",
- "EventCode": "0x0000101",
+ "EventCode": "0x101",
"BriefDescription": "Address-generation interlock"
},
{
"EventName": "LONGLAT_INTERLOCK",
- "EventCode": "0x0000201",
+ "EventCode": "0x201",
"BriefDescription": "Long-latency interlock"
},
{
"EventName": "CSR_READ_INTERLOCK",
- "EventCode": "0x0000401",
+ "EventCode": "0x401",
"BriefDescription": "CSR read interlock"
},
{
"EventName": "ICACHE_ITIM_BUSY",
- "EventCode": "0x0000801",
+ "EventCode": "0x801",
"BriefDescription": "Instruction cache/ITIM busy"
},
{
"EventName": "DCACHE_DTIM_BUSY",
- "EventCode": "0x0001001",
+ "EventCode": "0x1001",
"BriefDescription": "Data cache/DTIM busy"
},
{
"EventName": "BRANCH_DIRECTION_MISPREDICTION",
- "EventCode": "0x0002001",
+ "EventCode": "0x2001",
"BriefDescription": "Branch direction misprediction"
},
{
"EventName": "BRANCH_TARGET_MISPREDICTION",
- "EventCode": "0x0004001",
+ "EventCode": "0x4001",
"BriefDescription": "Branch/jump target misprediction"
},
{
"EventName": "PIPE_FLUSH_CSR_WRITE",
- "EventCode": "0x0008001",
+ "EventCode": "0x8001",
"BriefDescription": "Pipeline flush from CSR write"
},
{
"EventName": "PIPE_FLUSH_OTHER_EVENT",
- "EventCode": "0x0010001",
+ "EventCode": "0x10001",
"BriefDescription": "Pipeline flush from other event"
},
{
"EventName": "INTEGER_MULTIPLICATION_INTERLOCK",
- "EventCode": "0x0020001",
+ "EventCode": "0x20001",
"BriefDescription": "Integer multiplication interlock"
},
{
"EventName": "FP_INTERLOCK",
- "EventCode": "0x0040001",
+ "EventCode": "0x40001",
"BriefDescription": "Floating-point interlock"
}
]
\ No newline at end of file
--
2.44.0
^ permalink raw reply related [flat|nested] 9+ messages in thread
* [PATCH 3/7] perf vendor events riscv: Update SiFive Bullet events
2024-05-09 2:14 [PATCH 0/7] perf vendor events riscv: Update SiFive CPU PMU events Samuel Holland
2024-05-09 2:14 ` [PATCH 1/7] perf vendor events riscv: Rename U74 to Bullet Samuel Holland
2024-05-09 2:14 ` [PATCH 2/7] perf vendor events riscv: Remove leading zeroes Samuel Holland
@ 2024-05-09 2:14 ` Samuel Holland
2024-05-09 2:14 ` [PATCH 4/7] perf vendor events riscv: Add SiFive Bullet version 0x07 events Samuel Holland
` (4 subsequent siblings)
7 siblings, 0 replies; 9+ messages in thread
From: Samuel Holland @ 2024-05-09 2:14 UTC (permalink / raw)
To: Arnaldo Carvalho de Melo, Palmer Dabbelt, linux-perf-users,
linux-riscv
Cc: Mark Rutland, Adrian Hunter, Alexander Shishkin, Jiri Olsa,
Peter Zijlstra, Ingo Molnar, Ian Rogers, Namhyung Kim,
Arnaldo Carvalho de Melo, Eric Lin, Samuel Holland
From: Eric Lin <eric.lin@sifive.com>
Regenerate the event lists from the original hardware description. This
makes them consistent with the event lists for newer versions of the
hardware, allowing most files to be reused across hardware versions.
Signed-off-by: Eric Lin <eric.lin@sifive.com>
Co-developed-by: Samuel Holland <samuel.holland@sifive.com>
Signed-off-by: Samuel Holland <samuel.holland@sifive.com>
---
.../arch/riscv/sifive/bullet/instruction.json | 44 +++++++++----------
.../arch/riscv/sifive/bullet/memory.json | 24 +++++-----
.../arch/riscv/sifive/bullet/microarch.json | 38 ++++++++--------
3 files changed, 53 insertions(+), 53 deletions(-)
diff --git a/tools/perf/pmu-events/arch/riscv/sifive/bullet/instruction.json b/tools/perf/pmu-events/arch/riscv/sifive/bullet/instruction.json
index d5c370f70819..284e4c1566e0 100644
--- a/tools/perf/pmu-events/arch/riscv/sifive/bullet/instruction.json
+++ b/tools/perf/pmu-events/arch/riscv/sifive/bullet/instruction.json
@@ -2,91 +2,91 @@
{
"EventName": "EXCEPTION_TAKEN",
"EventCode": "0x100",
- "BriefDescription": "Exception taken"
+ "BriefDescription": "Counts exceptions taken"
},
{
"EventName": "INTEGER_LOAD_RETIRED",
"EventCode": "0x200",
- "BriefDescription": "Integer load instruction retired"
+ "BriefDescription": "Counts integer load instructions retired"
},
{
"EventName": "INTEGER_STORE_RETIRED",
"EventCode": "0x400",
- "BriefDescription": "Integer store instruction retired"
+ "BriefDescription": "Counts integer store instructions retired"
},
{
"EventName": "ATOMIC_MEMORY_RETIRED",
"EventCode": "0x800",
- "BriefDescription": "Atomic memory operation retired"
+ "BriefDescription": "Counts atomic memory instructions retired"
},
{
"EventName": "SYSTEM_INSTRUCTION_RETIRED",
"EventCode": "0x1000",
- "BriefDescription": "System instruction retired"
+ "BriefDescription": "Counts system instructions retired (CSR, WFI, MRET, etc.)"
},
{
"EventName": "INTEGER_ARITHMETIC_RETIRED",
"EventCode": "0x2000",
- "BriefDescription": "Integer arithmetic instruction retired"
+ "BriefDescription": "Counts integer arithmetic instructions retired"
},
{
"EventName": "CONDITIONAL_BRANCH_RETIRED",
"EventCode": "0x4000",
- "BriefDescription": "Conditional branch retired"
+ "BriefDescription": "Counts conditional branch instructions retired"
},
{
"EventName": "JAL_INSTRUCTION_RETIRED",
"EventCode": "0x8000",
- "BriefDescription": "JAL instruction retired"
+ "BriefDescription": "Counts jump-and-link instructions retired"
},
{
"EventName": "JALR_INSTRUCTION_RETIRED",
"EventCode": "0x10000",
- "BriefDescription": "JALR instruction retired"
+ "BriefDescription": "Counts indirect jump instructions (JALR) retired"
},
{
"EventName": "INTEGER_MULTIPLICATION_RETIRED",
"EventCode": "0x20000",
- "BriefDescription": "Integer multiplication instruction retired"
+ "BriefDescription": "Counts integer multiplication instructions retired"
},
{
"EventName": "INTEGER_DIVISION_RETIRED",
"EventCode": "0x40000",
- "BriefDescription": "Integer division instruction retired"
+ "BriefDescription": "Counts integer division instructions retired"
},
{
"EventName": "FP_LOAD_RETIRED",
"EventCode": "0x80000",
- "BriefDescription": "Floating-point load instruction retired"
+ "BriefDescription": "Counts floating-point load instructions retired"
},
{
"EventName": "FP_STORE_RETIRED",
"EventCode": "0x100000",
- "BriefDescription": "Floating-point store instruction retired"
+ "BriefDescription": "Counts floating-point store instructions retired"
},
{
- "EventName": "FP_ADDITION_RETIRED",
+ "EventName": "FP_ADD_RETIRED",
"EventCode": "0x200000",
- "BriefDescription": "Floating-point addition retired"
+ "BriefDescription": "Counts floating-point add instructions retired"
},
{
- "EventName": "FP_MULTIPLICATION_RETIRED",
+ "EventName": "FP_MUL_RETIRED",
"EventCode": "0x400000",
- "BriefDescription": "Floating-point multiplication retired"
+ "BriefDescription": "Counts floating-point multiply instructions retired"
},
{
- "EventName": "FP_FUSEDMADD_RETIRED",
+ "EventName": "FP_MULADD_RETIRED",
"EventCode": "0x800000",
- "BriefDescription": "Floating-point fused multiply-add retired"
+ "BriefDescription": "Counts floating-point fused multiply-add instructions retired"
},
{
"EventName": "FP_DIV_SQRT_RETIRED",
"EventCode": "0x1000000",
- "BriefDescription": "Floating-point division or square-root retired"
+ "BriefDescription": "Counts floating point divide or square root instructions retired"
},
{
"EventName": "OTHER_FP_RETIRED",
"EventCode": "0x2000000",
- "BriefDescription": "Other floating-point instruction retired"
+ "BriefDescription": "Counts other floating-point instructions retired"
}
-]
\ No newline at end of file
+]
diff --git a/tools/perf/pmu-events/arch/riscv/sifive/bullet/memory.json b/tools/perf/pmu-events/arch/riscv/sifive/bullet/memory.json
index ba3168f8a4cd..70441a55dd66 100644
--- a/tools/perf/pmu-events/arch/riscv/sifive/bullet/memory.json
+++ b/tools/perf/pmu-events/arch/riscv/sifive/bullet/memory.json
@@ -1,32 +1,32 @@
[
{
- "EventName": "ICACHE_RETIRED",
+ "EventName": "ICACHE_MISS",
"EventCode": "0x102",
- "BriefDescription": "Instruction cache miss"
+ "BriefDescription": "Counts instruction cache misses"
},
{
- "EventName": "DCACHE_MISS_MMIO_ACCESSES",
+ "EventName": "DCACHE_MISS",
"EventCode": "0x202",
- "BriefDescription": "Data cache miss or memory-mapped I/O access"
+ "BriefDescription": "Counts data cache misses"
},
{
- "EventName": "DCACHE_WRITEBACK",
+ "EventName": "DCACHE_RELEASE",
"EventCode": "0x402",
- "BriefDescription": "Data cache write-back"
+ "BriefDescription": "Counts writeback requests from the data cache"
},
{
- "EventName": "INST_TLB_MISS",
+ "EventName": "ITLB_MISS",
"EventCode": "0x802",
- "BriefDescription": "Instruction TLB miss"
+ "BriefDescription": "Counts Instruction TLB misses caused by instruction address translation requests"
},
{
- "EventName": "DATA_TLB_MISS",
+ "EventName": "DTLB_MISS",
"EventCode": "0x1002",
- "BriefDescription": "Data TLB miss"
+ "BriefDescription": "Counts Data TLB misses caused by data address translation requests"
},
{
"EventName": "UTLB_MISS",
"EventCode": "0x2002",
- "BriefDescription": "UTLB miss"
+ "BriefDescription": "Counts Unified TLB misses caused by address translation requests"
}
-]
\ No newline at end of file
+]
diff --git a/tools/perf/pmu-events/arch/riscv/sifive/bullet/microarch.json b/tools/perf/pmu-events/arch/riscv/sifive/bullet/microarch.json
index 8036e72fb0d4..d9cdb7d747ee 100644
--- a/tools/perf/pmu-events/arch/riscv/sifive/bullet/microarch.json
+++ b/tools/perf/pmu-events/arch/riscv/sifive/bullet/microarch.json
@@ -2,56 +2,56 @@
{
"EventName": "ADDRESSGEN_INTERLOCK",
"EventCode": "0x101",
- "BriefDescription": "Address-generation interlock"
+ "BriefDescription": "Counts cycles with an address-generation interlock"
},
{
- "EventName": "LONGLAT_INTERLOCK",
+ "EventName": "LONGLATENCY_INTERLOCK",
"EventCode": "0x201",
- "BriefDescription": "Long-latency interlock"
+ "BriefDescription": "Counts cycles with a long-latency interlock"
},
{
- "EventName": "CSR_READ_INTERLOCK",
+ "EventName": "CSR_INTERLOCK",
"EventCode": "0x401",
- "BriefDescription": "CSR read interlock"
+ "BriefDescription": "Counts cycles with a CSR interlock"
},
{
- "EventName": "ICACHE_ITIM_BUSY",
+ "EventName": "ICACHE_BLOCKED",
"EventCode": "0x801",
- "BriefDescription": "Instruction cache/ITIM busy"
+ "BriefDescription": "Counts cycles in which the instruction cache was not able to provide an instruction"
},
{
- "EventName": "DCACHE_DTIM_BUSY",
+ "EventName": "DCACHE_BLOCKED",
"EventCode": "0x1001",
- "BriefDescription": "Data cache/DTIM busy"
+ "BriefDescription": "Counts cycles in which the data cache blocked an instruction"
},
{
"EventName": "BRANCH_DIRECTION_MISPREDICTION",
"EventCode": "0x2001",
- "BriefDescription": "Branch direction misprediction"
+ "BriefDescription": "Counts mispredictions of conditional branch direction (taken/not taken)"
},
{
"EventName": "BRANCH_TARGET_MISPREDICTION",
"EventCode": "0x4001",
- "BriefDescription": "Branch/jump target misprediction"
+ "BriefDescription": "Counts mispredictions of the target PC of control-flow instructions"
},
{
- "EventName": "PIPE_FLUSH_CSR_WRITE",
+ "EventName": "PIPELINE_FLUSH",
"EventCode": "0x8001",
- "BriefDescription": "Pipeline flush from CSR write"
+ "BriefDescription": "Counts flushes of the core pipeline. Common causes include fence.i and CSR accesses"
},
{
- "EventName": "PIPE_FLUSH_OTHER_EVENT",
+ "EventName": "REPLAY",
"EventCode": "0x10001",
- "BriefDescription": "Pipeline flush from other event"
+ "BriefDescription": "Counts instruction replays"
},
{
- "EventName": "INTEGER_MULTIPLICATION_INTERLOCK",
+ "EventName": "INTEGER_MUL_DIV_INTERLOCK",
"EventCode": "0x20001",
- "BriefDescription": "Integer multiplication interlock"
+ "BriefDescription": "Counts cycles with a multiply or divide interlock"
},
{
"EventName": "FP_INTERLOCK",
"EventCode": "0x40001",
- "BriefDescription": "Floating-point interlock"
+ "BriefDescription": "Counts cycles with a floating-point interlock"
}
-]
\ No newline at end of file
+]
--
2.44.0
^ permalink raw reply related [flat|nested] 9+ messages in thread
* [PATCH 4/7] perf vendor events riscv: Add SiFive Bullet version 0x07 events
2024-05-09 2:14 [PATCH 0/7] perf vendor events riscv: Update SiFive CPU PMU events Samuel Holland
` (2 preceding siblings ...)
2024-05-09 2:14 ` [PATCH 3/7] perf vendor events riscv: Update SiFive Bullet events Samuel Holland
@ 2024-05-09 2:14 ` Samuel Holland
2024-05-09 2:14 ` [PATCH 5/7] perf vendor events riscv: Add SiFive Bullet version 0x0d events Samuel Holland
` (3 subsequent siblings)
7 siblings, 0 replies; 9+ messages in thread
From: Samuel Holland @ 2024-05-09 2:14 UTC (permalink / raw)
To: Arnaldo Carvalho de Melo, Palmer Dabbelt, linux-perf-users,
linux-riscv
Cc: Mark Rutland, Adrian Hunter, Alexander Shishkin, Jiri Olsa,
Peter Zijlstra, Ingo Molnar, Ian Rogers, Namhyung Kim,
Arnaldo Carvalho de Melo, Eric Lin, Samuel Holland
From: Eric Lin <eric.lin@sifive.com>
SiFive Bullet microarchitecture cores with mimpid values starting with
0x07 or greater add new PMU events to support debug, trace, and counter
sampling and filtering (Sscofpmf).
All other PMU events are unchanged from earlier Bullet cores.
Signed-off-by: Eric Lin <eric.lin@sifive.com>
Co-developed-by: Samuel Holland <samuel.holland@sifive.com>
Signed-off-by: Samuel Holland <samuel.holland@sifive.com>
---
tools/perf/pmu-events/arch/riscv/mapfile.csv | 1 +
.../cycle-and-instruction-count.json | 12 ++++
.../arch/riscv/sifive/bullet-07/firmware.json | 1 +
.../riscv/sifive/bullet-07/instruction.json | 1 +
.../arch/riscv/sifive/bullet-07/memory.json | 1 +
.../riscv/sifive/bullet-07/microarch.json | 62 +++++++++++++++++++
.../riscv/sifive/bullet-07/watchpoint.json | 42 +++++++++++++
7 files changed, 120 insertions(+)
create mode 100644 tools/perf/pmu-events/arch/riscv/sifive/bullet-07/cycle-and-instruction-count.json
create mode 120000 tools/perf/pmu-events/arch/riscv/sifive/bullet-07/firmware.json
create mode 120000 tools/perf/pmu-events/arch/riscv/sifive/bullet-07/instruction.json
create mode 120000 tools/perf/pmu-events/arch/riscv/sifive/bullet-07/memory.json
create mode 100644 tools/perf/pmu-events/arch/riscv/sifive/bullet-07/microarch.json
create mode 100644 tools/perf/pmu-events/arch/riscv/sifive/bullet-07/watchpoint.json
diff --git a/tools/perf/pmu-events/arch/riscv/mapfile.csv b/tools/perf/pmu-events/arch/riscv/mapfile.csv
index 521f416b0006..8706d289215e 100644
--- a/tools/perf/pmu-events/arch/riscv/mapfile.csv
+++ b/tools/perf/pmu-events/arch/riscv/mapfile.csv
@@ -15,6 +15,7 @@
#
#MVENDORID-MARCHID-MIMPID,Version,Filename,EventType
0x489-0x8000000000000007-0x[[:xdigit:]]+,v1,sifive/bullet,core
+0x489-0x8000000000000[1-9a-e]07-0x[78ac][[:xdigit:]]+,v1,sifive/bullet-07,core
0x5b7-0x0-0x0,v1,thead/c900-legacy,core
0x67e-0x80000000db0000[89]0-0x[[:xdigit:]]+,v1,starfive/dubhe-80,core
0x31e-0x8000000000008a45-0x[[:xdigit:]]+,v1,andes/ax45,core
diff --git a/tools/perf/pmu-events/arch/riscv/sifive/bullet-07/cycle-and-instruction-count.json b/tools/perf/pmu-events/arch/riscv/sifive/bullet-07/cycle-and-instruction-count.json
new file mode 100644
index 000000000000..5c8124cfe926
--- /dev/null
+++ b/tools/perf/pmu-events/arch/riscv/sifive/bullet-07/cycle-and-instruction-count.json
@@ -0,0 +1,12 @@
+[
+ {
+ "EventName": "CORE_CLOCK_CYCLES",
+ "EventCode": "0x165",
+ "BriefDescription": "Counts core clock cycles"
+ },
+ {
+ "EventName": "INSTRUCTIONS_RETIRED",
+ "EventCode": "0x265",
+ "BriefDescription": "Counts instructions retired"
+ }
+]
diff --git a/tools/perf/pmu-events/arch/riscv/sifive/bullet-07/firmware.json b/tools/perf/pmu-events/arch/riscv/sifive/bullet-07/firmware.json
new file mode 120000
index 000000000000..34e5c2870eee
--- /dev/null
+++ b/tools/perf/pmu-events/arch/riscv/sifive/bullet-07/firmware.json
@@ -0,0 +1 @@
+../bullet/firmware.json
\ No newline at end of file
diff --git a/tools/perf/pmu-events/arch/riscv/sifive/bullet-07/instruction.json b/tools/perf/pmu-events/arch/riscv/sifive/bullet-07/instruction.json
new file mode 120000
index 000000000000..62eacc2d7497
--- /dev/null
+++ b/tools/perf/pmu-events/arch/riscv/sifive/bullet-07/instruction.json
@@ -0,0 +1 @@
+../bullet/instruction.json
\ No newline at end of file
diff --git a/tools/perf/pmu-events/arch/riscv/sifive/bullet-07/memory.json b/tools/perf/pmu-events/arch/riscv/sifive/bullet-07/memory.json
new file mode 120000
index 000000000000..df50fc47a5fe
--- /dev/null
+++ b/tools/perf/pmu-events/arch/riscv/sifive/bullet-07/memory.json
@@ -0,0 +1 @@
+../bullet/memory.json
\ No newline at end of file
diff --git a/tools/perf/pmu-events/arch/riscv/sifive/bullet-07/microarch.json b/tools/perf/pmu-events/arch/riscv/sifive/bullet-07/microarch.json
new file mode 100644
index 000000000000..de8efd7b8b34
--- /dev/null
+++ b/tools/perf/pmu-events/arch/riscv/sifive/bullet-07/microarch.json
@@ -0,0 +1,62 @@
+[
+ {
+ "EventName": "ADDRESSGEN_INTERLOCK",
+ "EventCode": "0x101",
+ "BriefDescription": "Counts cycles with an address-generation interlock"
+ },
+ {
+ "EventName": "LONGLATENCY_INTERLOCK",
+ "EventCode": "0x201",
+ "BriefDescription": "Counts cycles with a long-latency interlock"
+ },
+ {
+ "EventName": "CSR_INTERLOCK",
+ "EventCode": "0x401",
+ "BriefDescription": "Counts cycles with a CSR interlock"
+ },
+ {
+ "EventName": "ICACHE_BLOCKED",
+ "EventCode": "0x801",
+ "BriefDescription": "Counts cycles in which the instruction cache was not able to provide an instruction"
+ },
+ {
+ "EventName": "DCACHE_BLOCKED",
+ "EventCode": "0x1001",
+ "BriefDescription": "Counts cycles in which the data cache blocked an instruction"
+ },
+ {
+ "EventName": "BRANCH_DIRECTION_MISPREDICTION",
+ "EventCode": "0x2001",
+ "BriefDescription": "Counts mispredictions of conditional branch direction (taken/not taken)"
+ },
+ {
+ "EventName": "BRANCH_TARGET_MISPREDICTION",
+ "EventCode": "0x4001",
+ "BriefDescription": "Counts mispredictions of the target PC of control-flow instructions"
+ },
+ {
+ "EventName": "PIPELINE_FLUSH",
+ "EventCode": "0x8001",
+ "BriefDescription": "Counts flushes of the core pipeline. Common causes include fence.i and CSR accesses"
+ },
+ {
+ "EventName": "REPLAY",
+ "EventCode": "0x10001",
+ "BriefDescription": "Counts instruction replays"
+ },
+ {
+ "EventName": "INTEGER_MUL_DIV_INTERLOCK",
+ "EventCode": "0x20001",
+ "BriefDescription": "Counts cycles with a multiply or divide interlock"
+ },
+ {
+ "EventName": "FP_INTERLOCK",
+ "EventCode": "0x40001",
+ "BriefDescription": "Counts cycles with a floating-point interlock"
+ },
+ {
+ "EventName": "TRACE_STALL",
+ "EventCode": "0x80001",
+ "BriefDescription": "Counts cycles in which the core pipeline is stalled due to backpressure from the Trace Encoder"
+ }
+]
diff --git a/tools/perf/pmu-events/arch/riscv/sifive/bullet-07/watchpoint.json b/tools/perf/pmu-events/arch/riscv/sifive/bullet-07/watchpoint.json
new file mode 100644
index 000000000000..aa7a12818521
--- /dev/null
+++ b/tools/perf/pmu-events/arch/riscv/sifive/bullet-07/watchpoint.json
@@ -0,0 +1,42 @@
+[
+ {
+ "EventName": "WATCHPOINT_0",
+ "EventCode": "0x164",
+ "BriefDescription": "Counts occurrences of watchpoint 0 with action=8"
+ },
+ {
+ "EventName": "WATCHPOINT_1",
+ "EventCode": "0x264",
+ "BriefDescription": "Counts occurrences of watchpoint 1 with action=8"
+ },
+ {
+ "EventName": "WATCHPOINT_2",
+ "EventCode": "0x464",
+ "BriefDescription": "Counts occurrences of watchpoint 2 with action=8"
+ },
+ {
+ "EventName": "WATCHPOINT_3",
+ "EventCode": "0x864",
+ "BriefDescription": "Counts occurrences of watchpoint 3 with action=8"
+ },
+ {
+ "EventName": "WATCHPOINT_4",
+ "EventCode": "0x1064",
+ "BriefDescription": "Counts occurrences of watchpoint 4 with action=8"
+ },
+ {
+ "EventName": "WATCHPOINT_5",
+ "EventCode": "0x2064",
+ "BriefDescription": "Counts occurrences of watchpoint 5 with action=8"
+ },
+ {
+ "EventName": "WATCHPOINT_6",
+ "EventCode": "0x4064",
+ "BriefDescription": "Counts occurrences of watchpoint 6 with action=8"
+ },
+ {
+ "EventName": "WATCHPOINT_7",
+ "EventCode": "0x8064",
+ "BriefDescription": "Counts occurrences of watchpoint 7 with action=8"
+ }
+]
--
2.44.0
^ permalink raw reply related [flat|nested] 9+ messages in thread
* [PATCH 5/7] perf vendor events riscv: Add SiFive Bullet version 0x0d events
2024-05-09 2:14 [PATCH 0/7] perf vendor events riscv: Update SiFive CPU PMU events Samuel Holland
` (3 preceding siblings ...)
2024-05-09 2:14 ` [PATCH 4/7] perf vendor events riscv: Add SiFive Bullet version 0x07 events Samuel Holland
@ 2024-05-09 2:14 ` Samuel Holland
2024-05-09 2:14 ` [PATCH 6/7] perf vendor events riscv: Add SiFive P550 events Samuel Holland
` (2 subsequent siblings)
7 siblings, 0 replies; 9+ messages in thread
From: Samuel Holland @ 2024-05-09 2:14 UTC (permalink / raw)
To: Arnaldo Carvalho de Melo, Palmer Dabbelt, linux-perf-users,
linux-riscv
Cc: Mark Rutland, Adrian Hunter, Alexander Shishkin, Jiri Olsa,
Peter Zijlstra, Ingo Molnar, Ian Rogers, Namhyung Kim,
Arnaldo Carvalho de Melo, Eric Lin, Samuel Holland
From: Eric Lin <eric.lin@sifive.com>
SiFive Bullet microarchitecture cores with mimpid values starting with
0x0d or greater add new PMU events to count TLB miss stall cycles.
All other PMU events are unchanged from earlier Bullet cores.
Signed-off-by: Eric Lin <eric.lin@sifive.com>
Signed-off-by: Samuel Holland <samuel.holland@sifive.com>
---
tools/perf/pmu-events/arch/riscv/mapfile.csv | 1 +
.../cycle-and-instruction-count.json | 1 +
.../arch/riscv/sifive/bullet-0d/firmware.json | 1 +
.../riscv/sifive/bullet-0d/instruction.json | 1 +
.../arch/riscv/sifive/bullet-0d/memory.json | 1 +
.../riscv/sifive/bullet-0d/microarch.json | 72 +++++++++++++++++++
.../riscv/sifive/bullet-0d/watchpoint.json | 1 +
7 files changed, 78 insertions(+)
create mode 120000 tools/perf/pmu-events/arch/riscv/sifive/bullet-0d/cycle-and-instruction-count.json
create mode 120000 tools/perf/pmu-events/arch/riscv/sifive/bullet-0d/firmware.json
create mode 120000 tools/perf/pmu-events/arch/riscv/sifive/bullet-0d/instruction.json
create mode 120000 tools/perf/pmu-events/arch/riscv/sifive/bullet-0d/memory.json
create mode 100644 tools/perf/pmu-events/arch/riscv/sifive/bullet-0d/microarch.json
create mode 120000 tools/perf/pmu-events/arch/riscv/sifive/bullet-0d/watchpoint.json
diff --git a/tools/perf/pmu-events/arch/riscv/mapfile.csv b/tools/perf/pmu-events/arch/riscv/mapfile.csv
index 8706d289215e..9e9bd7ac0ebe 100644
--- a/tools/perf/pmu-events/arch/riscv/mapfile.csv
+++ b/tools/perf/pmu-events/arch/riscv/mapfile.csv
@@ -16,6 +16,7 @@
#MVENDORID-MARCHID-MIMPID,Version,Filename,EventType
0x489-0x8000000000000007-0x[[:xdigit:]]+,v1,sifive/bullet,core
0x489-0x8000000000000[1-9a-e]07-0x[78ac][[:xdigit:]]+,v1,sifive/bullet-07,core
+0x489-0x8000000000000[1-9a-e]07-0xd[[:xdigit:]]+,v1,sifive/bullet-0d,core
0x5b7-0x0-0x0,v1,thead/c900-legacy,core
0x67e-0x80000000db0000[89]0-0x[[:xdigit:]]+,v1,starfive/dubhe-80,core
0x31e-0x8000000000008a45-0x[[:xdigit:]]+,v1,andes/ax45,core
diff --git a/tools/perf/pmu-events/arch/riscv/sifive/bullet-0d/cycle-and-instruction-count.json b/tools/perf/pmu-events/arch/riscv/sifive/bullet-0d/cycle-and-instruction-count.json
new file mode 120000
index 000000000000..ccd29278f61b
--- /dev/null
+++ b/tools/perf/pmu-events/arch/riscv/sifive/bullet-0d/cycle-and-instruction-count.json
@@ -0,0 +1 @@
+../bullet-07/cycle-and-instruction-count.json
\ No newline at end of file
diff --git a/tools/perf/pmu-events/arch/riscv/sifive/bullet-0d/firmware.json b/tools/perf/pmu-events/arch/riscv/sifive/bullet-0d/firmware.json
new file mode 120000
index 000000000000..34e5c2870eee
--- /dev/null
+++ b/tools/perf/pmu-events/arch/riscv/sifive/bullet-0d/firmware.json
@@ -0,0 +1 @@
+../bullet/firmware.json
\ No newline at end of file
diff --git a/tools/perf/pmu-events/arch/riscv/sifive/bullet-0d/instruction.json b/tools/perf/pmu-events/arch/riscv/sifive/bullet-0d/instruction.json
new file mode 120000
index 000000000000..62eacc2d7497
--- /dev/null
+++ b/tools/perf/pmu-events/arch/riscv/sifive/bullet-0d/instruction.json
@@ -0,0 +1 @@
+../bullet/instruction.json
\ No newline at end of file
diff --git a/tools/perf/pmu-events/arch/riscv/sifive/bullet-0d/memory.json b/tools/perf/pmu-events/arch/riscv/sifive/bullet-0d/memory.json
new file mode 120000
index 000000000000..df50fc47a5fe
--- /dev/null
+++ b/tools/perf/pmu-events/arch/riscv/sifive/bullet-0d/memory.json
@@ -0,0 +1 @@
+../bullet/memory.json
\ No newline at end of file
diff --git a/tools/perf/pmu-events/arch/riscv/sifive/bullet-0d/microarch.json b/tools/perf/pmu-events/arch/riscv/sifive/bullet-0d/microarch.json
new file mode 100644
index 000000000000..6573b24788eb
--- /dev/null
+++ b/tools/perf/pmu-events/arch/riscv/sifive/bullet-0d/microarch.json
@@ -0,0 +1,72 @@
+[
+ {
+ "EventName": "ADDRESSGEN_INTERLOCK",
+ "EventCode": "0x101",
+ "BriefDescription": "Counts cycles with an address-generation interlock"
+ },
+ {
+ "EventName": "LONGLATENCY_INTERLOCK",
+ "EventCode": "0x201",
+ "BriefDescription": "Counts cycles with a long-latency interlock"
+ },
+ {
+ "EventName": "CSR_INTERLOCK",
+ "EventCode": "0x401",
+ "BriefDescription": "Counts cycles with a CSR interlock"
+ },
+ {
+ "EventName": "ICACHE_BLOCKED",
+ "EventCode": "0x801",
+ "BriefDescription": "Counts cycles in which the instruction cache was not able to provide an instruction"
+ },
+ {
+ "EventName": "DCACHE_BLOCKED",
+ "EventCode": "0x1001",
+ "BriefDescription": "Counts cycles in which the data cache blocked an instruction"
+ },
+ {
+ "EventName": "BRANCH_DIRECTION_MISPREDICTION",
+ "EventCode": "0x2001",
+ "BriefDescription": "Counts mispredictions of conditional branch direction (taken/not taken)"
+ },
+ {
+ "EventName": "BRANCH_TARGET_MISPREDICTION",
+ "EventCode": "0x4001",
+ "BriefDescription": "Counts mispredictions of the target PC of control-flow instructions"
+ },
+ {
+ "EventName": "PIPELINE_FLUSH",
+ "EventCode": "0x8001",
+ "BriefDescription": "Counts flushes of the core pipeline. Common causes include fence.i and CSR accesses"
+ },
+ {
+ "EventName": "REPLAY",
+ "EventCode": "0x10001",
+ "BriefDescription": "Counts instruction replays"
+ },
+ {
+ "EventName": "INTEGER_MUL_DIV_INTERLOCK",
+ "EventCode": "0x20001",
+ "BriefDescription": "Counts cycles with a multiply or divide interlock"
+ },
+ {
+ "EventName": "FP_INTERLOCK",
+ "EventCode": "0x40001",
+ "BriefDescription": "Counts cycles with a floating-point interlock"
+ },
+ {
+ "EventName": "TRACE_STALL",
+ "EventCode": "0x80001",
+ "BriefDescription": "Counts cycles in which the core pipeline is stalled due to backpressure from the Trace Encoder"
+ },
+ {
+ "EventName": "ITLB_MISS_STALL",
+ "EventCode": "0x100001",
+ "BriefDescription": "Counts cycles in which the core pipeline is stalled due to ITLB Miss"
+ },
+ {
+ "EventName": "DTLB_MISS_STALL",
+ "EventCode": "0x200001",
+ "BriefDescription": "Counts cycles in which the core pipeline is stalled due to DTLB Miss"
+ }
+]
diff --git a/tools/perf/pmu-events/arch/riscv/sifive/bullet-0d/watchpoint.json b/tools/perf/pmu-events/arch/riscv/sifive/bullet-0d/watchpoint.json
new file mode 120000
index 000000000000..e88b98bfc5c8
--- /dev/null
+++ b/tools/perf/pmu-events/arch/riscv/sifive/bullet-0d/watchpoint.json
@@ -0,0 +1 @@
+../bullet-07/watchpoint.json
\ No newline at end of file
--
2.44.0
^ permalink raw reply related [flat|nested] 9+ messages in thread
* [PATCH 6/7] perf vendor events riscv: Add SiFive P550 events
2024-05-09 2:14 [PATCH 0/7] perf vendor events riscv: Update SiFive CPU PMU events Samuel Holland
` (4 preceding siblings ...)
2024-05-09 2:14 ` [PATCH 5/7] perf vendor events riscv: Add SiFive Bullet version 0x0d events Samuel Holland
@ 2024-05-09 2:14 ` Samuel Holland
2024-05-09 2:15 ` [PATCH 7/7] perf vendor events riscv: Add SiFive P650 events Samuel Holland
2024-05-11 15:53 ` [PATCH 0/7] perf vendor events riscv: Update SiFive CPU PMU events Arnaldo Carvalho de Melo
7 siblings, 0 replies; 9+ messages in thread
From: Samuel Holland @ 2024-05-09 2:14 UTC (permalink / raw)
To: Arnaldo Carvalho de Melo, Palmer Dabbelt, linux-perf-users,
linux-riscv
Cc: Mark Rutland, Adrian Hunter, Alexander Shishkin, Jiri Olsa,
Peter Zijlstra, Ingo Molnar, Ian Rogers, Namhyung Kim,
Arnaldo Carvalho de Melo, Eric Lin, Samuel Holland
From: Eric Lin <eric.lin@sifive.com>
The SiFive Performance P550 core features an out-of-order
microarchitecture which exposes the same PMU events as Bullet,
plus events for UTLB hits and PTE cache misses/hits.
Add support for specifying these events using symbolic names.
Signed-off-by: Eric Lin <eric.lin@sifive.com>
Co-developed-by: Samuel Holland <samuel.holland@sifive.com>
Signed-off-by: Samuel Holland <samuel.holland@sifive.com>
---
tools/perf/pmu-events/arch/riscv/mapfile.csv | 1 +
.../arch/riscv/sifive/p550/firmware.json | 1 +
.../arch/riscv/sifive/p550/instruction.json | 1 +
.../arch/riscv/sifive/p550/memory.json | 47 +++++++++++++++++++
.../arch/riscv/sifive/p550/microarch.json | 1 +
5 files changed, 51 insertions(+)
create mode 120000 tools/perf/pmu-events/arch/riscv/sifive/p550/firmware.json
create mode 120000 tools/perf/pmu-events/arch/riscv/sifive/p550/instruction.json
create mode 100644 tools/perf/pmu-events/arch/riscv/sifive/p550/memory.json
create mode 120000 tools/perf/pmu-events/arch/riscv/sifive/p550/microarch.json
diff --git a/tools/perf/pmu-events/arch/riscv/mapfile.csv b/tools/perf/pmu-events/arch/riscv/mapfile.csv
index 9e9bd7ac0ebe..a301e9dbfd5a 100644
--- a/tools/perf/pmu-events/arch/riscv/mapfile.csv
+++ b/tools/perf/pmu-events/arch/riscv/mapfile.csv
@@ -17,6 +17,7 @@
0x489-0x8000000000000007-0x[[:xdigit:]]+,v1,sifive/bullet,core
0x489-0x8000000000000[1-9a-e]07-0x[78ac][[:xdigit:]]+,v1,sifive/bullet-07,core
0x489-0x8000000000000[1-9a-e]07-0xd[[:xdigit:]]+,v1,sifive/bullet-0d,core
+0x489-0x8000000000000008-0x[[:xdigit:]]+,v1,sifive/p550,core
0x5b7-0x0-0x0,v1,thead/c900-legacy,core
0x67e-0x80000000db0000[89]0-0x[[:xdigit:]]+,v1,starfive/dubhe-80,core
0x31e-0x8000000000008a45-0x[[:xdigit:]]+,v1,andes/ax45,core
diff --git a/tools/perf/pmu-events/arch/riscv/sifive/p550/firmware.json b/tools/perf/pmu-events/arch/riscv/sifive/p550/firmware.json
new file mode 120000
index 000000000000..34e5c2870eee
--- /dev/null
+++ b/tools/perf/pmu-events/arch/riscv/sifive/p550/firmware.json
@@ -0,0 +1 @@
+../bullet/firmware.json
\ No newline at end of file
diff --git a/tools/perf/pmu-events/arch/riscv/sifive/p550/instruction.json b/tools/perf/pmu-events/arch/riscv/sifive/p550/instruction.json
new file mode 120000
index 000000000000..62eacc2d7497
--- /dev/null
+++ b/tools/perf/pmu-events/arch/riscv/sifive/p550/instruction.json
@@ -0,0 +1 @@
+../bullet/instruction.json
\ No newline at end of file
diff --git a/tools/perf/pmu-events/arch/riscv/sifive/p550/memory.json b/tools/perf/pmu-events/arch/riscv/sifive/p550/memory.json
new file mode 100644
index 000000000000..8393f81b2cf0
--- /dev/null
+++ b/tools/perf/pmu-events/arch/riscv/sifive/p550/memory.json
@@ -0,0 +1,47 @@
+[
+ {
+ "EventName": "ICACHE_MISS",
+ "EventCode": "0x102",
+ "BriefDescription": "Counts instruction cache misses"
+ },
+ {
+ "EventName": "DCACHE_MISS",
+ "EventCode": "0x202",
+ "BriefDescription": "Counts data cache misses"
+ },
+ {
+ "EventName": "DCACHE_RELEASE",
+ "EventCode": "0x402",
+ "BriefDescription": "Counts writeback requests from the data cache"
+ },
+ {
+ "EventName": "ITLB_MISS",
+ "EventCode": "0x802",
+ "BriefDescription": "Counts Instruction TLB misses caused by instruction address translation requests"
+ },
+ {
+ "EventName": "DTLB_MISS",
+ "EventCode": "0x1002",
+ "BriefDescription": "Counts Data TLB misses caused by data address translation requests"
+ },
+ {
+ "EventName": "UTLB_MISS",
+ "EventCode": "0x2002",
+ "BriefDescription": "Counts Unified TLB misses caused by address translation requests"
+ },
+ {
+ "EventName": "UTLB_HIT",
+ "EventCode": "0x4002",
+ "BriefDescription": "Counts Unified TLB hits for address translation requests"
+ },
+ {
+ "EventName": "PTE_CACHE_MISS",
+ "EventCode": "0x8002",
+ "BriefDescription": "Counts Page Table Entry cache misses"
+ },
+ {
+ "EventName": "PTE_CACHE_HIT",
+ "EventCode": "0x10002",
+ "BriefDescription": "Counts Page Table Entry cache hits"
+ }
+]
diff --git a/tools/perf/pmu-events/arch/riscv/sifive/p550/microarch.json b/tools/perf/pmu-events/arch/riscv/sifive/p550/microarch.json
new file mode 120000
index 000000000000..ba5dd2960e9f
--- /dev/null
+++ b/tools/perf/pmu-events/arch/riscv/sifive/p550/microarch.json
@@ -0,0 +1 @@
+../bullet/microarch.json
\ No newline at end of file
--
2.44.0
^ permalink raw reply related [flat|nested] 9+ messages in thread
* [PATCH 7/7] perf vendor events riscv: Add SiFive P650 events
2024-05-09 2:14 [PATCH 0/7] perf vendor events riscv: Update SiFive CPU PMU events Samuel Holland
` (5 preceding siblings ...)
2024-05-09 2:14 ` [PATCH 6/7] perf vendor events riscv: Add SiFive P550 events Samuel Holland
@ 2024-05-09 2:15 ` Samuel Holland
2024-05-11 15:53 ` [PATCH 0/7] perf vendor events riscv: Update SiFive CPU PMU events Arnaldo Carvalho de Melo
7 siblings, 0 replies; 9+ messages in thread
From: Samuel Holland @ 2024-05-09 2:15 UTC (permalink / raw)
To: Arnaldo Carvalho de Melo, Palmer Dabbelt, linux-perf-users,
linux-riscv
Cc: Mark Rutland, Adrian Hunter, Alexander Shishkin, Jiri Olsa,
Peter Zijlstra, Ingo Molnar, Ian Rogers, Namhyung Kim,
Arnaldo Carvalho de Melo, Eric Lin, Samuel Holland
From: Eric Lin <eric.lin@sifive.com>
The SiFive Performance P650 core (including the vector-enabled P670 and
area-optimized P450/P470 variants) updates the P550 microarchitecture.
It brings in the debug, trace, and counter events from newer Bullet
cores, and adds new events for iTLB and dTLB multi-hits.
All other PMU events are unchanged from the P550 core.
Signed-off-by: Eric Lin <eric.lin@sifive.com>
Co-developed-by: Samuel Holland <samuel.holland@sifive.com>
Signed-off-by: Samuel Holland <samuel.holland@sifive.com>
---
tools/perf/pmu-events/arch/riscv/mapfile.csv | 1 +
.../p650/cycle-and-instruction-count.json | 1 +
.../arch/riscv/sifive/p650/firmware.json | 1 +
.../arch/riscv/sifive/p650/instruction.json | 1 +
.../arch/riscv/sifive/p650/memory.json | 57 +++++++++++++++++
.../arch/riscv/sifive/p650/microarch.json | 62 +++++++++++++++++++
.../arch/riscv/sifive/p650/watchpoint.json | 1 +
7 files changed, 124 insertions(+)
create mode 120000 tools/perf/pmu-events/arch/riscv/sifive/p650/cycle-and-instruction-count.json
create mode 120000 tools/perf/pmu-events/arch/riscv/sifive/p650/firmware.json
create mode 120000 tools/perf/pmu-events/arch/riscv/sifive/p650/instruction.json
create mode 100644 tools/perf/pmu-events/arch/riscv/sifive/p650/memory.json
create mode 100644 tools/perf/pmu-events/arch/riscv/sifive/p650/microarch.json
create mode 120000 tools/perf/pmu-events/arch/riscv/sifive/p650/watchpoint.json
diff --git a/tools/perf/pmu-events/arch/riscv/mapfile.csv b/tools/perf/pmu-events/arch/riscv/mapfile.csv
index a301e9dbfd5a..0a7e7dcc81be 100644
--- a/tools/perf/pmu-events/arch/riscv/mapfile.csv
+++ b/tools/perf/pmu-events/arch/riscv/mapfile.csv
@@ -18,6 +18,7 @@
0x489-0x8000000000000[1-9a-e]07-0x[78ac][[:xdigit:]]+,v1,sifive/bullet-07,core
0x489-0x8000000000000[1-9a-e]07-0xd[[:xdigit:]]+,v1,sifive/bullet-0d,core
0x489-0x8000000000000008-0x[[:xdigit:]]+,v1,sifive/p550,core
+0x489-0x8000000000000[1-6]08-0x[9b][[:xdigit:]]+,v1,sifive/p650,core
0x5b7-0x0-0x0,v1,thead/c900-legacy,core
0x67e-0x80000000db0000[89]0-0x[[:xdigit:]]+,v1,starfive/dubhe-80,core
0x31e-0x8000000000008a45-0x[[:xdigit:]]+,v1,andes/ax45,core
diff --git a/tools/perf/pmu-events/arch/riscv/sifive/p650/cycle-and-instruction-count.json b/tools/perf/pmu-events/arch/riscv/sifive/p650/cycle-and-instruction-count.json
new file mode 120000
index 000000000000..ccd29278f61b
--- /dev/null
+++ b/tools/perf/pmu-events/arch/riscv/sifive/p650/cycle-and-instruction-count.json
@@ -0,0 +1 @@
+../bullet-07/cycle-and-instruction-count.json
\ No newline at end of file
diff --git a/tools/perf/pmu-events/arch/riscv/sifive/p650/firmware.json b/tools/perf/pmu-events/arch/riscv/sifive/p650/firmware.json
new file mode 120000
index 000000000000..34e5c2870eee
--- /dev/null
+++ b/tools/perf/pmu-events/arch/riscv/sifive/p650/firmware.json
@@ -0,0 +1 @@
+../bullet/firmware.json
\ No newline at end of file
diff --git a/tools/perf/pmu-events/arch/riscv/sifive/p650/instruction.json b/tools/perf/pmu-events/arch/riscv/sifive/p650/instruction.json
new file mode 120000
index 000000000000..62eacc2d7497
--- /dev/null
+++ b/tools/perf/pmu-events/arch/riscv/sifive/p650/instruction.json
@@ -0,0 +1 @@
+../bullet/instruction.json
\ No newline at end of file
diff --git a/tools/perf/pmu-events/arch/riscv/sifive/p650/memory.json b/tools/perf/pmu-events/arch/riscv/sifive/p650/memory.json
new file mode 100644
index 000000000000..f1431b339c7f
--- /dev/null
+++ b/tools/perf/pmu-events/arch/riscv/sifive/p650/memory.json
@@ -0,0 +1,57 @@
+[
+ {
+ "EventName": "ICACHE_MISS",
+ "EventCode": "0x102",
+ "BriefDescription": "Counts instruction cache misses"
+ },
+ {
+ "EventName": "DCACHE_MISS",
+ "EventCode": "0x202",
+ "BriefDescription": "Counts data cache misses"
+ },
+ {
+ "EventName": "DCACHE_RELEASE",
+ "EventCode": "0x402",
+ "BriefDescription": "Counts writeback requests from the data cache"
+ },
+ {
+ "EventName": "ITLB_MISS",
+ "EventCode": "0x802",
+ "BriefDescription": "Counts Instruction TLB misses caused by instruction address translation requests"
+ },
+ {
+ "EventName": "DTLB_MISS",
+ "EventCode": "0x1002",
+ "BriefDescription": "Counts Data TLB misses caused by data address translation requests"
+ },
+ {
+ "EventName": "UTLB_MISS",
+ "EventCode": "0x2002",
+ "BriefDescription": "Counts Unified TLB misses caused by address translation requests"
+ },
+ {
+ "EventName": "UTLB_HIT",
+ "EventCode": "0x4002",
+ "BriefDescription": "Counts Unified TLB hits for address translation requests"
+ },
+ {
+ "EventName": "PTE_CACHE_MISS",
+ "EventCode": "0x8002",
+ "BriefDescription": "Counts Page Table Entry cache misses"
+ },
+ {
+ "EventName": "PTE_CACHE_HIT",
+ "EventCode": "0x10002",
+ "BriefDescription": "Counts Page Table Entry cache hits"
+ },
+ {
+ "EventName": "ITLB_MULTI_HIT",
+ "EventCode": "0x20002",
+ "BriefDescription": "Counts Instruction TLB multi-hits"
+ },
+ {
+ "EventName": "DTLB_MULTI_HIT",
+ "EventCode": "0x40002",
+ "BriefDescription": "Counts Data TLB multi-hits"
+ }
+]
diff --git a/tools/perf/pmu-events/arch/riscv/sifive/p650/microarch.json b/tools/perf/pmu-events/arch/riscv/sifive/p650/microarch.json
new file mode 100644
index 000000000000..de8efd7b8b34
--- /dev/null
+++ b/tools/perf/pmu-events/arch/riscv/sifive/p650/microarch.json
@@ -0,0 +1,62 @@
+[
+ {
+ "EventName": "ADDRESSGEN_INTERLOCK",
+ "EventCode": "0x101",
+ "BriefDescription": "Counts cycles with an address-generation interlock"
+ },
+ {
+ "EventName": "LONGLATENCY_INTERLOCK",
+ "EventCode": "0x201",
+ "BriefDescription": "Counts cycles with a long-latency interlock"
+ },
+ {
+ "EventName": "CSR_INTERLOCK",
+ "EventCode": "0x401",
+ "BriefDescription": "Counts cycles with a CSR interlock"
+ },
+ {
+ "EventName": "ICACHE_BLOCKED",
+ "EventCode": "0x801",
+ "BriefDescription": "Counts cycles in which the instruction cache was not able to provide an instruction"
+ },
+ {
+ "EventName": "DCACHE_BLOCKED",
+ "EventCode": "0x1001",
+ "BriefDescription": "Counts cycles in which the data cache blocked an instruction"
+ },
+ {
+ "EventName": "BRANCH_DIRECTION_MISPREDICTION",
+ "EventCode": "0x2001",
+ "BriefDescription": "Counts mispredictions of conditional branch direction (taken/not taken)"
+ },
+ {
+ "EventName": "BRANCH_TARGET_MISPREDICTION",
+ "EventCode": "0x4001",
+ "BriefDescription": "Counts mispredictions of the target PC of control-flow instructions"
+ },
+ {
+ "EventName": "PIPELINE_FLUSH",
+ "EventCode": "0x8001",
+ "BriefDescription": "Counts flushes of the core pipeline. Common causes include fence.i and CSR accesses"
+ },
+ {
+ "EventName": "REPLAY",
+ "EventCode": "0x10001",
+ "BriefDescription": "Counts instruction replays"
+ },
+ {
+ "EventName": "INTEGER_MUL_DIV_INTERLOCK",
+ "EventCode": "0x20001",
+ "BriefDescription": "Counts cycles with a multiply or divide interlock"
+ },
+ {
+ "EventName": "FP_INTERLOCK",
+ "EventCode": "0x40001",
+ "BriefDescription": "Counts cycles with a floating-point interlock"
+ },
+ {
+ "EventName": "TRACE_STALL",
+ "EventCode": "0x80001",
+ "BriefDescription": "Counts cycles in which the core pipeline is stalled due to backpressure from the Trace Encoder"
+ }
+]
diff --git a/tools/perf/pmu-events/arch/riscv/sifive/p650/watchpoint.json b/tools/perf/pmu-events/arch/riscv/sifive/p650/watchpoint.json
new file mode 120000
index 000000000000..e88b98bfc5c8
--- /dev/null
+++ b/tools/perf/pmu-events/arch/riscv/sifive/p650/watchpoint.json
@@ -0,0 +1 @@
+../bullet-07/watchpoint.json
\ No newline at end of file
--
2.44.0
^ permalink raw reply related [flat|nested] 9+ messages in thread
* Re: [PATCH 0/7] perf vendor events riscv: Update SiFive CPU PMU events
2024-05-09 2:14 [PATCH 0/7] perf vendor events riscv: Update SiFive CPU PMU events Samuel Holland
` (6 preceding siblings ...)
2024-05-09 2:15 ` [PATCH 7/7] perf vendor events riscv: Add SiFive P650 events Samuel Holland
@ 2024-05-11 15:53 ` Arnaldo Carvalho de Melo
7 siblings, 0 replies; 9+ messages in thread
From: Arnaldo Carvalho de Melo @ 2024-05-11 15:53 UTC (permalink / raw)
To: Ian Rogers, Samuel Holland
Cc: Arnaldo Carvalho de Melo, Palmer Dabbelt, linux-perf-users,
linux-riscv, Mark Rutland, Adrian Hunter, Alexander Shishkin,
Jiri Olsa, Peter Zijlstra, Ingo Molnar, Namhyung Kim
On Wed, May 08, 2024 at 07:14:53PM -0700, Samuel Holland wrote:
> This series updates the PMU event JSON files to add support for newer
> SiFive CPUs, including those used in the upcoming HiFive Premier P550
> board. Since most changes are incremental, symbolic links are used when
> a set of events is unchanged from the previous CPU series.
Ian, are you ok with this? Someone with such systems can provide some
Tested-by?
- Arnaldo
>
> Eric Lin (5):
> perf vendor events riscv: Update SiFive Bullet events
> perf vendor events riscv: Add SiFive Bullet version 0x07 events
> perf vendor events riscv: Add SiFive Bullet version 0x0d events
> perf vendor events riscv: Add SiFive P550 events
> perf vendor events riscv: Add SiFive P650 events
>
> Samuel Holland (2):
> perf vendor events riscv: Rename U74 to Bullet
> perf vendor events riscv: Remove leading zeroes
>
> tools/perf/pmu-events/arch/riscv/mapfile.csv | 6 +-
> .../cycle-and-instruction-count.json | 12 +++
> .../arch/riscv/sifive/bullet-07/firmware.json | 1 +
> .../riscv/sifive/bullet-07/instruction.json | 1 +
> .../arch/riscv/sifive/bullet-07/memory.json | 1 +
> .../riscv/sifive/bullet-07/microarch.json | 62 +++++++++++++
> .../riscv/sifive/bullet-07/watchpoint.json | 42 +++++++++
> .../cycle-and-instruction-count.json | 1 +
> .../arch/riscv/sifive/bullet-0d/firmware.json | 1 +
> .../riscv/sifive/bullet-0d/instruction.json | 1 +
> .../arch/riscv/sifive/bullet-0d/memory.json | 1 +
> .../riscv/sifive/bullet-0d/microarch.json | 72 +++++++++++++++
> .../riscv/sifive/bullet-0d/watchpoint.json | 1 +
> .../sifive/{u74 => bullet}/firmware.json | 0
> .../arch/riscv/sifive/bullet/instruction.json | 92 +++++++++++++++++++
> .../arch/riscv/sifive/bullet/memory.json | 32 +++++++
> .../arch/riscv/sifive/bullet/microarch.json | 57 ++++++++++++
> .../arch/riscv/sifive/p550/firmware.json | 1 +
> .../arch/riscv/sifive/p550/instruction.json | 1 +
> .../arch/riscv/sifive/p550/memory.json | 47 ++++++++++
> .../arch/riscv/sifive/p550/microarch.json | 1 +
> .../p650/cycle-and-instruction-count.json | 1 +
> .../arch/riscv/sifive/p650/firmware.json | 1 +
> .../arch/riscv/sifive/p650/instruction.json | 1 +
> .../arch/riscv/sifive/p650/memory.json | 57 ++++++++++++
> .../arch/riscv/sifive/p650/microarch.json | 62 +++++++++++++
> .../arch/riscv/sifive/p650/watchpoint.json | 1 +
> .../arch/riscv/sifive/u74/instructions.json | 92 -------------------
> .../arch/riscv/sifive/u74/memory.json | 32 -------
> .../arch/riscv/sifive/u74/microarch.json | 57 ------------
> 30 files changed, 555 insertions(+), 182 deletions(-)
> create mode 100644 tools/perf/pmu-events/arch/riscv/sifive/bullet-07/cycle-and-instruction-count.json
> create mode 120000 tools/perf/pmu-events/arch/riscv/sifive/bullet-07/firmware.json
> create mode 120000 tools/perf/pmu-events/arch/riscv/sifive/bullet-07/instruction.json
> create mode 120000 tools/perf/pmu-events/arch/riscv/sifive/bullet-07/memory.json
> create mode 100644 tools/perf/pmu-events/arch/riscv/sifive/bullet-07/microarch.json
> create mode 100644 tools/perf/pmu-events/arch/riscv/sifive/bullet-07/watchpoint.json
> create mode 120000 tools/perf/pmu-events/arch/riscv/sifive/bullet-0d/cycle-and-instruction-count.json
> create mode 120000 tools/perf/pmu-events/arch/riscv/sifive/bullet-0d/firmware.json
> create mode 120000 tools/perf/pmu-events/arch/riscv/sifive/bullet-0d/instruction.json
> create mode 120000 tools/perf/pmu-events/arch/riscv/sifive/bullet-0d/memory.json
> create mode 100644 tools/perf/pmu-events/arch/riscv/sifive/bullet-0d/microarch.json
> create mode 120000 tools/perf/pmu-events/arch/riscv/sifive/bullet-0d/watchpoint.json
> rename tools/perf/pmu-events/arch/riscv/sifive/{u74 => bullet}/firmware.json (100%)
> create mode 100644 tools/perf/pmu-events/arch/riscv/sifive/bullet/instruction.json
> create mode 100644 tools/perf/pmu-events/arch/riscv/sifive/bullet/memory.json
> create mode 100644 tools/perf/pmu-events/arch/riscv/sifive/bullet/microarch.json
> create mode 120000 tools/perf/pmu-events/arch/riscv/sifive/p550/firmware.json
> create mode 120000 tools/perf/pmu-events/arch/riscv/sifive/p550/instruction.json
> create mode 100644 tools/perf/pmu-events/arch/riscv/sifive/p550/memory.json
> create mode 120000 tools/perf/pmu-events/arch/riscv/sifive/p550/microarch.json
> create mode 120000 tools/perf/pmu-events/arch/riscv/sifive/p650/cycle-and-instruction-count.json
> create mode 120000 tools/perf/pmu-events/arch/riscv/sifive/p650/firmware.json
> create mode 120000 tools/perf/pmu-events/arch/riscv/sifive/p650/instruction.json
> create mode 100644 tools/perf/pmu-events/arch/riscv/sifive/p650/memory.json
> create mode 100644 tools/perf/pmu-events/arch/riscv/sifive/p650/microarch.json
> create mode 120000 tools/perf/pmu-events/arch/riscv/sifive/p650/watchpoint.json
> delete mode 100644 tools/perf/pmu-events/arch/riscv/sifive/u74/instructions.json
> delete mode 100644 tools/perf/pmu-events/arch/riscv/sifive/u74/memory.json
> delete mode 100644 tools/perf/pmu-events/arch/riscv/sifive/u74/microarch.json
>
> --
> 2.44.0
>
^ permalink raw reply [flat|nested] 9+ messages in thread
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2024-05-09 2:14 [PATCH 0/7] perf vendor events riscv: Update SiFive CPU PMU events Samuel Holland
2024-05-09 2:14 ` [PATCH 1/7] perf vendor events riscv: Rename U74 to Bullet Samuel Holland
2024-05-09 2:14 ` [PATCH 2/7] perf vendor events riscv: Remove leading zeroes Samuel Holland
2024-05-09 2:14 ` [PATCH 3/7] perf vendor events riscv: Update SiFive Bullet events Samuel Holland
2024-05-09 2:14 ` [PATCH 4/7] perf vendor events riscv: Add SiFive Bullet version 0x07 events Samuel Holland
2024-05-09 2:14 ` [PATCH 5/7] perf vendor events riscv: Add SiFive Bullet version 0x0d events Samuel Holland
2024-05-09 2:14 ` [PATCH 6/7] perf vendor events riscv: Add SiFive P550 events Samuel Holland
2024-05-09 2:15 ` [PATCH 7/7] perf vendor events riscv: Add SiFive P650 events Samuel Holland
2024-05-11 15:53 ` [PATCH 0/7] perf vendor events riscv: Update SiFive CPU PMU events Arnaldo Carvalho de Melo
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