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[34.105.13.176]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-1f60a5aa7ecsm11991535ad.213.2024.05.29.21.35.00 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 29 May 2024 21:35:01 -0700 (PDT) Date: Thu, 30 May 2024 04:34:57 +0000 From: Mingwei Zhang To: Peter Zijlstra Cc: Sean Christopherson , Paolo Bonzini , Xiong Zhang , Dapeng Mi , Kan Liang , Zhenyu Wang , Manali Shukla , Sandipan Das , Jim Mattson , Stephane Eranian , Ian Rogers , Namhyung Kim , gce-passthrou-pmu-dev@google.com, Samantha Alt , Zhiyuan Lv , Yanfei Xu , maobibo , Like Xu , kvm@vger.kernel.org, linux-perf-users@vger.kernel.org Subject: Re: [PATCH v2 38/54] KVM: x86/pmu: Call perf_guest_enter() at PMU context switch Message-ID: References: <20240506053020.3911940-1-mizhang@google.com> <20240506053020.3911940-39-mizhang@google.com> <20240507093923.GX40213@noisy.programming.kicks-ass.net> Precedence: bulk X-Mailing-List: linux-perf-users@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20240507093923.GX40213@noisy.programming.kicks-ass.net> On Tue, May 07, 2024, Peter Zijlstra wrote: > On Mon, May 06, 2024 at 05:30:03AM +0000, Mingwei Zhang wrote: > > From: Xiong Zhang > > > > perf subsystem should stop and restart all the perf events at the host > > level when entering and leaving passthrough PMU respectively. So invoke > > the perf API at PMU context switch functions. > > > > Signed-off-by: Xiong Zhang > > Signed-off-by: Dapeng Mi > > --- > > arch/x86/events/core.c | 4 ++++ > > 1 file changed, 4 insertions(+) > > > > diff --git a/arch/x86/events/core.c b/arch/x86/events/core.c > > index f5a043410614..6fe467bca809 100644 > > --- a/arch/x86/events/core.c > > +++ b/arch/x86/events/core.c > > @@ -705,6 +705,8 @@ void x86_perf_guest_enter(u32 guest_lvtpc) > > { > > lockdep_assert_irqs_disabled(); > > > > + perf_guest_enter(); > > + > > apic_write(APIC_LVTPC, APIC_DM_FIXED | KVM_GUEST_PMI_VECTOR | > > (guest_lvtpc & APIC_LVT_MASKED)); > > } > > @@ -715,6 +717,8 @@ void x86_perf_guest_exit(void) > > lockdep_assert_irqs_disabled(); > > > > apic_write(APIC_LVTPC, APIC_DM_NMI); > > + > > + perf_guest_exit(); > > } > > EXPORT_SYMBOL_GPL(x86_perf_guest_exit); > > *sigh*.. why does this patch exist? Please merge with the one that > introduces these functions. > > This is making review really hard. Ah, right. This function should be added immediately after commit "perf: x86: Add x86 function to switch PMI handler". It was just mind set of development: "how can we call perf_guest_{enter,exit}() if KVM has not implemented anything?" So we defer the invocation until this moment :) Will fix that in next version. Thanks. -Mingwei