From: "Mi, Dapeng" <dapeng1.mi@linux.intel.com>
To: Dave Hansen <dave.hansen@intel.com>,
"Chang S. Bae" <chang.seok.bae@intel.com>,
Peter Zijlstra <peterz@infradead.org>,
Ingo Molnar <mingo@redhat.com>,
Arnaldo Carvalho de Melo <acme@kernel.org>,
Namhyung Kim <namhyung@kernel.org>,
Thomas Gleixner <tglx@linutronix.de>,
Dave Hansen <dave.hansen@linux.intel.com>,
Ian Rogers <irogers@google.com>,
Adrian Hunter <adrian.hunter@intel.com>,
Jiri Olsa <jolsa@kernel.org>,
Alexander Shishkin <alexander.shishkin@linux.intel.com>,
Andi Kleen <ak@linux.intel.com>,
Eranian Stephane <eranian@google.com>
Cc: Mark Rutland <mark.rutland@arm.com>,
broonie@kernel.org, Ravi Bangoria <ravi.bangoria@amd.com>,
linux-kernel@vger.kernel.org, linux-perf-users@vger.kernel.org,
Zide Chen <zide.chen@intel.com>,
Falcon Thomas <thomas.falcon@intel.com>,
Dapeng Mi <dapeng1.mi@intel.com>,
Xudong Hao <xudong.hao@intel.com>
Subject: Re: [Patch v6 08/22] x86/fpu: Ensure TIF_NEED_FPU_LOAD is set after saving FPU state
Date: Tue, 24 Feb 2026 14:50:33 +0800 [thread overview]
Message-ID: <a0bc418d-c167-4ccf-8f50-eba9396d2112@linux.intel.com> (raw)
In-Reply-To: <960918ce-f42f-464f-a887-c36d8d9e2937@intel.com>
On 2/12/2026 3:55 AM, Dave Hansen wrote:
> On 2/11/26 11:39, Chang S. Bae wrote:
>> But the changelog doesn't look clear enough to explain the reason to me.
> Yeah, the changelog could use some improvement.
>
> This also leaves the code rather fragile. Right now, all of the:
>
> save_fpregs_to_fpstate(fpu);
> set_thread_flag(TIF_NEED_FPU_LOAD);
>
> pairs are open-coded. There's precisely nothing stopping someone from
> coming in tomorrow and reversing the order at these or other call sites.
> There's also zero comments left in the code to tell folks not to do this.
>
> Are there enough of these to have a helper that does:
>
> save_fpregs_to_fpstate_before_invalidation(fpu);
>
> which could do the save and set TIF_NEED_FPU_LOAD? (that name is awful
> btw, please don't use it).
Sure. Would introduce an inline function and add comments. Thanks.
>
> This:
>
>> /* Swap fpstate */
>> if (enter_guest) {
>> - fpu->__task_fpstate = cur_fps;
>> + WRITE_ONCE(fpu->__task_fpstate, cur_fps);
>> + barrier();
>> fpu->fpstate = guest_fps;
>> guest_fps->in_use = true;
>> } else {
>> guest_fps->in_use = false;
>> fpu->fpstate = fpu->__task_fpstate;
>> - fpu->__task_fpstate = NULL;
>> + barrier();
>> + WRITE_ONCE(fpu->__task_fpstate, NULL);
>> }
> also urgently needs comments.
>
> I also can't help but think that there might be a nicer way to do that
> without the barrier(). I _think_ two correctly-ordered WRITE_ONCE()'s
> would make the compiler do the same thing as the barrier().
>
> But I'm not fully understanding what the barrier() is doing anyway, so
> take that with a grain of salt.
IMO, barrier() seems a safer way for this situation. I'm not quite sure if
two WRITE_ONCE()'s would block the reordering from compiler, so I asked
Gemini, and here is its answer.
"
WRITE_ONCE() provides a certain level of protection, but it isn't a full
barrier.
WRITE_ONCE(): Prevents the compiler from optimizing the store away or
splitting it into multiple instructions.
Two WRITE_ONCE() calls: The compiler is generally discouraged from
reordering two volatile-style accesses (which WRITE_ONCE uses), but the C
standard doesn't strictly guarantee it in all cases.
"
Thanks.
next prev parent reply other threads:[~2026-02-24 6:50 UTC|newest]
Thread overview: 45+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-02-09 7:20 [Patch v6 00/22] Support SIMD/eGPRs/SSP registers sampling for perf Dapeng Mi
2026-02-09 7:20 ` [Patch v6 01/22] perf/x86/intel: Restrict PEBS_ENABLE writes to PEBS-capable counters Dapeng Mi
2026-02-10 15:36 ` Peter Zijlstra
2026-02-11 5:47 ` Mi, Dapeng
2026-02-09 7:20 ` [Patch v6 02/22] perf/x86/intel: Enable large PEBS sampling for XMMs Dapeng Mi
2026-02-09 7:20 ` [Patch v6 03/22] perf/x86/intel: Convert x86_perf_regs to per-cpu variables Dapeng Mi
2026-02-09 7:20 ` [Patch v6 04/22] perf: Eliminate duplicate arch-specific functions definations Dapeng Mi
2026-02-09 7:20 ` [Patch v6 05/22] perf/x86: Use x86_perf_regs in the x86 nmi handler Dapeng Mi
2026-02-10 18:40 ` Peter Zijlstra
2026-02-11 6:26 ` Mi, Dapeng
2026-02-09 7:20 ` [Patch v6 06/22] perf/x86: Introduce x86-specific x86_pmu_setup_regs_data() Dapeng Mi
2026-02-09 7:20 ` [Patch v6 07/22] x86/fpu/xstate: Add xsaves_nmi() helper Dapeng Mi
2026-02-09 7:20 ` [Patch v6 08/22] x86/fpu: Ensure TIF_NEED_FPU_LOAD is set after saving FPU state Dapeng Mi
2026-02-11 19:39 ` Chang S. Bae
2026-02-11 19:55 ` Dave Hansen
2026-02-24 6:50 ` Mi, Dapeng [this message]
2026-02-25 13:02 ` Peter Zijlstra
2026-02-24 5:35 ` Mi, Dapeng
2026-02-24 19:13 ` Chang S. Bae
2026-02-25 0:35 ` Mi, Dapeng
2026-02-09 7:20 ` [Patch v6 09/22] perf: Move and rename has_extended_regs() for ARCH-specific use Dapeng Mi
2026-02-09 7:20 ` [Patch v6 10/22] perf/x86: Enable XMM Register Sampling for Non-PEBS Events Dapeng Mi
2026-02-15 23:58 ` Chang S. Bae
2026-02-24 7:11 ` Mi, Dapeng
2026-02-24 19:13 ` Chang S. Bae
2026-02-25 0:55 ` Mi, Dapeng
2026-02-25 1:11 ` Chang S. Bae
2026-02-25 1:36 ` Mi, Dapeng
2026-02-25 3:14 ` Chang S. Bae
2026-02-25 6:13 ` Mi, Dapeng
2026-02-09 7:20 ` [Patch v6 11/22] perf/x86: Enable XMM register sampling for REGS_USER case Dapeng Mi
2026-02-09 7:20 ` [Patch v6 12/22] perf: Add sampling support for SIMD registers Dapeng Mi
2026-02-10 20:04 ` Peter Zijlstra
2026-02-11 6:56 ` Mi, Dapeng
2026-02-09 7:20 ` [Patch v6 13/22] perf/x86: Enable XMM sampling using sample_simd_vec_reg_* fields Dapeng Mi
2026-02-09 7:20 ` [Patch v6 14/22] perf/x86: Enable YMM " Dapeng Mi
2026-02-09 7:20 ` [Patch v6 15/22] perf/x86: Enable ZMM " Dapeng Mi
2026-02-09 7:20 ` [Patch v6 16/22] perf/x86: Enable OPMASK sampling using sample_simd_pred_reg_* fields Dapeng Mi
2026-02-09 7:20 ` [Patch v6 17/22] perf: Enhance perf_reg_validate() with simd_enabled argument Dapeng Mi
2026-02-09 7:20 ` [Patch v6 18/22] perf/x86: Enable eGPRs sampling using sample_regs_* fields Dapeng Mi
2026-02-09 7:20 ` [Patch v6 19/22] perf/x86: Enable SSP " Dapeng Mi
2026-02-09 7:20 ` [Patch v6 20/22] perf/x86/intel: Enable PERF_PMU_CAP_SIMD_REGS capability Dapeng Mi
2026-02-09 7:20 ` [Patch v6 21/22] perf/x86/intel: Enable arch-PEBS based SIMD/eGPRs/SSP sampling Dapeng Mi
2026-02-09 7:20 ` [Patch v6 22/22] perf/x86: Activate back-to-back NMI detection for arch-PEBS induced NMIs Dapeng Mi
2026-02-09 8:48 ` [Patch v6 00/22] Support SIMD/eGPRs/SSP registers sampling for perf Mi, Dapeng
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