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Peter Anvin" , Andy Lutomirski , Peter Zijlstra , Ingo Molnar , Arnaldo Carvalho de Melo , Namhyung Kim , Paolo Bonzini , linux-arm-kernel@lists.infradead.org, kvmarm@lists.linux.dev, kvm@vger.kernel.org, loongarch@lists.linux.dev, kvm-riscv@lists.infradead.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, linux-perf-users@vger.kernel.org, Mingwei Zhang , Xudong Hao , Sandipan Das , Xiong Zhang , Manali Shukla , Jim Mattson Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable On Mon, Dec 08, 2025, Dapeng Mi wrote: >=20 > On 12/6/2025 8:17 AM, Sean Christopherson wrote: > > Add a helper to remove an MSR from an auto-{load,store} list to dedup t= he > > msr_autoload code, and in anticipation of adding similar functionality = for > > msr_autostore. > > > > No functional change intended. > > > > Signed-off-by: Sean Christopherson > > --- > > arch/x86/kvm/vmx/vmx.c | 31 ++++++++++++++++--------------- > > 1 file changed, 16 insertions(+), 15 deletions(-) > > > > diff --git a/arch/x86/kvm/vmx/vmx.c b/arch/x86/kvm/vmx/vmx.c > > index 52bcb817cc15..a51f66d1b201 100644 > > --- a/arch/x86/kvm/vmx/vmx.c > > +++ b/arch/x86/kvm/vmx/vmx.c > > @@ -1040,9 +1040,22 @@ static int vmx_find_loadstore_msr_slot(struct vm= x_msrs *m, u32 msr) > > return -ENOENT; > > } > > =20 > > +static void vmx_remove_auto_msr(struct vmx_msrs *m, u32 msr, > > + unsigned long vmcs_count_field) > > +{ > > + int i; > > + > > + i =3D vmx_find_loadstore_msr_slot(m, msr); > > + if (i < 0) > > + return; > > + > > + --m->nr; > > + m->val[i] =3D m->val[m->nr]; >=20 > Sometimes the order of MSR writing does matter, e.g., PERF_GLOBAL_CTRL MS= R > should be written at last after all PMU MSR writing. Hmm, no. _If_ KVM were writing event selectors using the auto-load lists, = then KVM would need to bookend the event selector MSRs with PERF_GLOBAL_CTRL=3D0= and PERF_GLOBAL_CTRL=3D. E.g. so that guest PMC = counts aren't polluted with host events, and vice versa. As things stand today, the only other MSRs are PEBS and the DS area configu= ration stuff, and kinda to my earlier point, KVM pre-zeroes MSR_IA32_PEBS_ENABLE a= s part of add_atomic_switch_msr() to ensure a quiescent period before VM-Enter. Heh, and writing PERF_GLOBAL_CTRL last for that sequence might actually be problematic. E.g. load host PEBS with guest PERF_GLOBAL_CTRL active. Anyways, I agree that this might be brittle, but this is all pre-existing b= ehavior so I don't want to tackle that here unless it's absolutely necessary. Or wait, by "writing" do you mean "writing MSRs to memory", as opposed to "= writing values to MSRs"? Regardless, I think my answer is the same: this isn't a p= roblem today, so I'd prefer to not shuffle the ordering unless it's absolutely nec= essary. > So directly moving the last MSR entry into cleared one could break the MS= R > writing sequence and may cause issue in theory. >=20 > I know this won't really cause issue since currently vPMU won't use the M= SR > auto-load feature to save any PMU MSR, but it's still unsafe for future u= ses.=C2=A0 >=20 > I'm not sure if it's worthy to do the strict MSR entry shift right now. > > Perhaps we could add a message to warn users at least. Hmm, yeah, but I'm not entirely sure where/how best to document this. Beca= use it's not just that vmx_remove_auto_msr() arbitrarily maniuplates the order,= e.g. multiple calls to vmx_add_auto_msr() aren't guaranteed to provide ordering = because one or more MSRs may already be in the list. And the "special" MSRs that c= an be switched via dedicated VMCS fields further muddy the waters. So I'm tempted to not add a comment to the helpers, or even the struct fiel= ds, because unfortunately it's largely a "Here be dragons!" type warning. :-/