From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id AF3AC309EFB; Tue, 9 Dec 2025 23:01:02 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1765321262; cv=none; b=SDkssKiPqoHVidRY69G3QI2R/Lgn5rt/zbh2fDHzm4FCTBHnbVgTDfUzpdX4MI+ZuunuHYzCM/ZRa8OdMwRoCdqVpDV0tdQ1eUeMdotrmB6LfM/l5RRZDRtqlK3RHbh46hUlk02G61KwfPr6cQXsQ8WrQN3y4zvLvvvFqk3+9A4= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1765321262; c=relaxed/simple; bh=/ah7Zqz2nEXNAxPK4fIH6Lzc/09WmhDQtHjd6n9mOeg=; h=Date:From:To:Cc:Subject:Message-ID:References:MIME-Version: Content-Type:Content-Disposition:In-Reply-To; b=UB+PRSXq6143uOWLzdsoL7LgghzoOkAbxWRK7ZhOlkBaMzzzcGG0Z7KwEdQP01fqd5/niFHK5UduPLxnYGPLTcW0SMB+kItbXrNFcp59EnGh3RXFjdJ2uR2gHdM/+4sTWA1GEqA9yg3fRT5LOAzhTUVN0+GNpoigatxceen6K9c= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=e1Z2s9JW; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="e1Z2s9JW" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 360C2C4CEF5; Tue, 9 Dec 2025 23:01:01 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1765321261; bh=/ah7Zqz2nEXNAxPK4fIH6Lzc/09WmhDQtHjd6n9mOeg=; h=Date:From:To:Cc:Subject:References:In-Reply-To:From; b=e1Z2s9JWfojscSVTnJwydD7UV4xdGcvwgbFKC8mdeuCUIQGwCGyf+uTghHKUBkIbu ZPRz8fO0uNalxMF/ozlxNYLd+Apyru/mijc2WT70RTagFeAOyjPcLQAU4zLBxFcMCl PcjmeDS2LWJ2KAibw5ZtxQdXj/FP62jnY69/yJ8KzjFOsqNxk3bj/WbI9aAMzQrnwo p3B3CkuN3cfv46RHfhNytOPrt5Qn9eFQrZr+py3CzHyMWVIX/dQb3/n5njtU3b0Ip0 udpcHzXK1FdWrvrirQyGdPNfrzcAy3d5nEfHa6ssb2rKx+7J54erVlG5dJEepmb+EN HPka7oYuHd9og== Date: Tue, 9 Dec 2025 15:00:59 -0800 From: Oliver Upton To: Colton Lewis Cc: kvm@vger.kernel.org, Paolo Bonzini , Jonathan Corbet , Russell King , Catalin Marinas , Will Deacon , Marc Zyngier , Oliver Upton , Mingwei Zhang , Joey Gouly , Suzuki K Poulose , Zenghui Yu , Mark Rutland , Shuah Khan , Ganapatrao Kulkarni , linux-doc@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, kvmarm@lists.linux.dev, linux-perf-users@vger.kernel.org, linux-kselftest@vger.kernel.org Subject: Re: [PATCH v5 00/24] ARM64 PMU Partitioning Message-ID: References: <20251209205121.1871534-1-coltonlewis@google.com> Precedence: bulk X-Mailing-List: linux-perf-users@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20251209205121.1871534-1-coltonlewis@google.com> On Tue, Dec 09, 2025 at 08:50:57PM +0000, Colton Lewis wrote: > This series creates a new PMU scheme on ARM, a partitioned PMU that > allows reserving a subset of counters for more direct guest access, > significantly reducing overhead. More details, including performance > benchmarks, can be read in the v1 cover letter linked below. > > An overview of what this series accomplishes was presented at KVM > Forum 2025. Slides [1] and video [2] are linked below. > > The long duration between v4 and v5 is due to time spent on this > project being monopolized preparing this feature for internal > production. As a result, there are too many improvements to fully list > here, but I will cover the notable ones. Thanks for reposting. I think there's still quite a bit of ground to cover on the KVM side of this, but I would definitely appreciate it if someone with more context on the perf side of things could chime in. Will, IIRC you had some thoughts around counter allocation, right? Best, Oliver