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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: =?us-ascii?Q?/Pft1uz+V18nSpfOb7hCuQPYFJ8CK6j3+0dJUpHi/o2IY5yiMdlaNopo1MWK?= =?us-ascii?Q?KLAHIg4CO04BPe/j7ZrpdWXhPQ4OMSHC1o8vqWewRQm5efMx+dJPPjDhE4Gb?= =?us-ascii?Q?2R0hmziO7+iw2EGOXLVeb7KhI7hE3i3GribkGv7JmeKLHhFxHgHOjbs3bQP2?= =?us-ascii?Q?1ZZIzEw0lbSM2EDujkpS92qAQXxYMN5g1Ab0gA764pZZOOk3rLNF7HCFH/Cj?= =?us-ascii?Q?zd00tnpxRaQg+Ifc7LOhv9ZAKED4HPLkBRB2LWnnjbw0QqbH/OhaIE3DsocO?= =?us-ascii?Q?d07grmKKwNVu+HOJDPkFWFFVmuLZHncAcUc0MyCQ6u+IWa8nIEJYvm00HW0s?= =?us-ascii?Q?coIKE/bUTk1PNz5gbvBrdD5ZciyR29e2xxaHYHKkd6hVzKaZD2FQAgmQgRcq?= =?us-ascii?Q?b2yv8sVzRks6JNE9gaX76/6WfvOCNCluPTypgXFDuZ0OgdG8NllBc6GqdJc2?= =?us-ascii?Q?ic5kN3u4BnNY6aYsn3096SLEYcKjbnATIJe2YCRtvDqeGv+IyCCihG/Mp+RO?= =?us-ascii?Q?R1N/06C9KSpu6I8eK8fS+23ZDYo060GDbPHGc+jglE/1RUCEjpWsGI9j6cs1?= =?us-ascii?Q?apvWz8UDnaC0z182OOJc6uNf4TZhndN4id9dz3jXwaQoWHMGkdPReGYwBUej?= =?us-ascii?Q?yxpYa8i1UmSmy+kZr5hcpPATEZb0xWEJ6tWkmxjTi+wUTfo+QeNBVDNeTTXY?= =?us-ascii?Q?zjxaJXKF9lw8DlI+RuKr8wGWabBgk/txkD7VkGARb7AKC2rzwbRg+Jq4p1jH?= =?us-ascii?Q?6Iimo19aYB37pqywC+KVXSjy7gfYjL6f7EEQ6iH3mL45002yUKqoH+SM2Wun?= =?us-ascii?Q?3tLPsDCncj9Ri+vMeFV4T7wuUAnMVqQoG8LmUjiWoDCHUC2SKu3/+0ebiNwW?= =?us-ascii?Q?ke6+D2mAcjwi4iogQNv4iDKDknpxPsJtpEcpeDsLzm/2WYnNApIQblGNd04W?= =?us-ascii?Q?UTXpXIpzTgy/DTgwnQkNIuPIUUVZvSWATf0sIBZ+VQjmMifeEK6cuOJUHVP7?= =?us-ascii?Q?VemYypnCDM6tb+bLU5kQ0AaeCz72XbweTmptXsmfA1uafSfuxrz3cG05BYnt?= =?us-ascii?Q?QRRt6m4fhsXM8f2GY4ECvgT/hMa8NuxylMpJ1nklfjkfJmbvPF+bAEykjgm1?= =?us-ascii?Q?MPsbGVdeOxehhByRxK1QzwN95l6RG4n/9YNPEuq+2raUNRY7rXy2dPsHAfq5?= =?us-ascii?Q?bcsVtylkcrX1cUfaT8yschMeMi0dEzXk4NbTi11/FWj5A1Eolu7xFpS9dnH4?= =?us-ascii?Q?3NRnAhUzI6BBncXX6Po8H9NyOJoUOIzZVaAQLoWe7nBcXI5ripbC0wXfiYbv?= =?us-ascii?Q?k9Ag37L3vbeGyDCWo1UC+ZbCoCzXXeR/6pImJoWheifJdHQZ/venWdPy3PHm?= =?us-ascii?Q?VvSaBFeEIskU1yjHF0uFdXZ3vkqyEem5m5j2tm5r8H+mauumFeExWf3Z0oUx?= =?us-ascii?Q?9cuTcjW7jLzUG3NMQiaxC0gFRV55dHBNacc+K7zsv27hK5dAzYMpa4uHz7Bm?= =?us-ascii?Q?/DaI/ukv/1xIDIDAl5/nJSo/2p+DOEzhEP3RNXONoXWWp68TSKOWe7/u+NsN?= =?us-ascii?Q?utMal0TG1RyEZN0cc+7i5xja2qBYHU5WyzSETbmm1ZnipOHhf8ty7T+WQLoe?= =?us-ascii?Q?W+1UY8vuJsyBAS1Hp2Qa9m47TGUeUQAGBMb0twVBmrD/4MDXtNK7o/KAILIZ?= =?us-ascii?Q?a2DT/usqunezypWlz8ueLYFiu6jm3iiIBMnjU/TfbYHEAlJ3OMro29Xxkfqo?= =?us-ascii?Q?0qzxPzzeuA=3D=3D?= X-OriginatorOrg: oss.nxp.com X-MS-Exchange-CrossTenant-Network-Message-Id: 8566f197-44c7-4a6f-5513-08de957508d4 X-MS-Exchange-CrossTenant-AuthSource: PAXPR04MB8459.eurprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 08 Apr 2026 13:45:02.9063 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 686ea1d3-bc2b-4c6f-a92c-d99c5c301635 X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: AIOevKqM3/tKj8A2lRBlxAM7aXCyf5GYhzu8Fhcuh/YytjG+ejP84Awvkg1f5aKZ4GGrj0JiN+juH8skIIcsDA== X-MS-Exchange-Transport-CrossTenantHeadersStamped: AM9PR04MB8570 On Wed, Apr 08, 2026 at 12:15:31PM +0100, Robin Murphy wrote: >On 2026-04-08 8:51 am, Peng Fan (OSS) wrote: >> This patch series adds proper support for describing and probing the >> Arm SMMU v3 PMCG (Performance Monitor Control Group) as a child node of >> the SMMU in Devicetree, and updates the relevant drivers accordingly. >> >> The SMMU v3 architecture allows an optional PMCG block, typically >> associated with TCUs, to be implemented within the SMMU register >> address space. For example, mmu700 PMCG is at the offset 0x2000 of the >> TCU page 0. > >But what's wrong with the existing binding? Especially given that it even has >an upstream user already: > >https://git.kernel.org/torvalds/c/aef9703dcbf8 > >> Patch 1 updates the SMMU v3 Devicetree binding to allow PMCG child nodes, >> referencing the existing arm,smmu-v3-pmcg binding. >> >> Patch 2 updates the arm-smmu-v3 driver to populate platform devices for >> child nodes described in DT once the SMMU probe succeeds. >> >> Patch 3 updates the SMMUv3 PMU driver to correctly handle MMIO mapping when >> PMCG is described as a child node. The PMCG registers occupy a sub-region >> of the parent SMMU MMIO window, which is already requested by the SMMU > >That has not been the case since 52f3fab0067d ("iommu/arm-smmu-v3: Don't >reserve implementation defined register space") nearly 6 years ago, where the >whole purpose was to support Arm's PMCG implementation properly. What kernel >is this based on? Seems I am wrong. I thought PMCG is in page 0, so there were resource conflicts. I just retest without this patchset, all goes well. But from dt perspective, should the TCU PMCG node be child node of SMMU node? Thanks, Peng > >Thanks, >Robin. > >> Signed-off-by: Peng Fan >> --- >> Peng Fan (3): >> dt-bindings: iommu: arm-smmu-v3: Allow PMU child nodes >> iommu/arm-smmu-v3: Populate PMU child devices from Devicetree >> perf/arm-smmuv3: Avoid double-requesting shared SMMU MMIO for PMCG >> >> .../devicetree/bindings/iommu/arm,smmu-v3.yaml | 10 ++++++++++ >> drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c | 3 +++ >> drivers/perf/arm_smmuv3_pmu.c | 19 ++++++++++++++++--- >> 3 files changed, 29 insertions(+), 3 deletions(-) >> --- >> base-commit: f3e6330d7fe42b204af05a2dbc68b379e0ad179e >> change-id: 20260408-smmu-perf-754367fe66c8 >> >> Best regards, > >