Re: [PATCH v2] x86/events/intel/ds: Enable large PEBS for PERF_SAMPLE_WEIGHT_TYPE

["Liang, Kan" <kan.liang@linux.intel.com>]

On 5/19/2022 11:19 AM, Like Xu wrote:
> From: Like Xu <likexu@tencent.com>
> 
> All the information required by the PERF_SAMPLE_WEIGHT is
> available in the pebs record. Thus large PEBS could be enabled
> for PERF_SAMPLE_WEIGHT sample type to save PMIs overhead until
> other non-compatible flags such as PERF_SAMPLE_DATA_PAGE_SIZE
> (due to lack of munmap tracking) stop it.
> 
> To cover new weight extension, add PERF_SAMPLE_WEIGHT_TYPE
> to the guardian LARGE_PEBS_FLAGS.
> 
> Tested it with:
> 
> $ perf mem record -c 1000 workload
> Before: Captured and wrote 0.126 MB perf.data (958 samples) [958 PMIs]
> After: Captured and wrote 0.313 MB perf.data (4859 samples) [3 PMIs]
> 
> Cc: Kan Liang <kan.liang@linux.intel.com>
> Cc: Stephane Eranian <eranian@google.com>
> Cc: Jiri Olsa <jolsa@kernel.org>
> Reported-by: Yongchao Duan <yongduan@tencent.com>
> Signed-off-by: Like Xu <likexu@tencent.com>


Reviewed-by: Kan Liang <kan.liang@linux.intel.com>

Thanks,
Kan
> ---
> v1: https://lore.kernel.org/lkml/20220519104509.51847-1-likexu@tencent.com/
> v1 -> v2 Changelog:
> - Use the PERF_SAMPLE_WEIGHT_TYPE instead (Kan);
> 
>   arch/x86/events/perf_event.h | 3 ++-
>   1 file changed, 2 insertions(+), 1 deletion(-)
> 
> diff --git a/arch/x86/events/perf_event.h b/arch/x86/events/perf_event.h
> index 21a5482bcf84..1ca6200ca135 100644
> --- a/arch/x86/events/perf_event.h
> +++ b/arch/x86/events/perf_event.h
> @@ -136,7 +136,8 @@ struct amd_nb {
>   	PERF_SAMPLE_DATA_SRC | PERF_SAMPLE_IDENTIFIER | \
>   	PERF_SAMPLE_TRANSACTION | PERF_SAMPLE_PHYS_ADDR | \
>   	PERF_SAMPLE_REGS_INTR | PERF_SAMPLE_REGS_USER | \
> -	PERF_SAMPLE_PERIOD | PERF_SAMPLE_CODE_PAGE_SIZE)
> +	PERF_SAMPLE_PERIOD | PERF_SAMPLE_CODE_PAGE_SIZE | \
> +	PERF_SAMPLE_WEIGHT_TYPE)
>   
>   #define PEBS_GP_REGS			\
>   	((1ULL << PERF_REG_X86_AX)    | \