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AFNElJ/k+Rd+4uyhI+dMxT22M0xK8JdGArO8YD98ETt6cHy16qQrNuYHZS9o7Hst/OLjjfbI1Us+Gs6fH642RFf/Mwce@vger.kernel.org X-Gm-Message-State: AOJu0YyENO5akO6wgyMPrAqVGxo+XF8b/FWayMRYwzFxhZFdB6sPuV/W HK4kLCRmD72Mz0PFBH/wjgI+NQZ+N6Lzq3USdMd6a1vYUTzR36AWMn+F8FOWLbowkWXrnZqfmxj hkhYlYg== X-Received: from pffy27.prod.google.com ([2002:aa7:93db:0:b0:835:37a2:5ea7]) (user=seanjc job=prod-delivery.src-stubby-dispatcher) by 2002:a05:6a00:b91:b0:834:efcb:12b4 with SMTP id d2e1a72fcca58-8352d1fcf27mr10371914b3a.28.1777915177342; Mon, 04 May 2026 10:19:37 -0700 (PDT) Date: Mon, 4 May 2026 10:19:35 -0700 In-Reply-To: Precedence: bulk X-Mailing-List: linux-perf-users@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Mime-Version: 1.0 References: <20260423150340.463896-1-seanjc@google.com> <20260423150340.463896-5-seanjc@google.com> Message-ID: Subject: Re: [PATCH v2 4/4] perf/x86: KVM: Have perf define a dedicated struct for getting guest PEBS data From: Sean Christopherson To: Jim Mattson Cc: Peter Zijlstra , Ingo Molnar , Arnaldo Carvalho de Melo , Namhyung Kim , Thomas Gleixner , Borislav Petkov , Dave Hansen , x86@kernel.org, Paolo Bonzini , linux-perf-users@vger.kernel.org, linux-kernel@vger.kernel.org, kvm@vger.kernel.org, Mingwei Zhang , Stephane Eranian , Dapeng Mi Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable On Fri, May 01, 2026, Jim Mattson wrote: > On Thu, Apr 23, 2026 at 8:03=E2=80=AFAM Sean Christopherson wrote: > > diff --git a/arch/x86/events/intel/core.c b/arch/x86/events/intel/core.= c > > index 7403ca721b6a..04d9c51335d7 100644 > > --- a/arch/x86/events/intel/core.c > > +++ b/arch/x86/events/intel/core.c > > @@ -14,7 +14,6 @@ > > #include > > #include > > #include > > -#include > > > > #include > > #include > > @@ -4992,11 +4991,11 @@ static int intel_pmu_hw_config(struct perf_even= t *event) > > * when it uses {RD,WR}MSR, which should be handled by the KVM context= , > > * specifically in the intel_pmu_{get,set}_msr(). > > */ > > -static struct perf_guest_switch_msr *intel_guest_get_msrs(int *nr, voi= d *data) > > +static struct perf_guest_switch_msr *intel_guest_get_msrs(int *nr, > > + struct x86_gu= est_pebs *guest_pebs) > > { > > struct cpu_hw_events *cpuc =3D this_cpu_ptr(&cpu_hw_events); > > struct perf_guest_switch_msr *arr =3D cpuc->guest_switch_msrs; > > - struct kvm_pmu *kvm_pmu =3D (struct kvm_pmu *)data; > > u64 intel_ctrl =3D hybrid(cpuc->pmu, intel_ctrl); > > u64 pebs_mask =3D cpuc->pebs_enabled & x86_pmu.pebs_capable; > > u64 guest_pebs_mask =3D pebs_mask & ~cpuc->intel_ctrl_host_mask= ; > > @@ -5052,7 +5051,7 @@ static struct perf_guest_switch_msr *intel_guest_= get_msrs(int *nr, void *data) > > * wrong counter(s). Similarly, disallow PEBS in the guest if = the host > > * is using PEBS, to avoid bleeding host state into PEBS record= s. > > */ > > - guest_pebs_mask &=3D kvm_pmu->pebs_enable & ~kvm_pmu->host_cros= s_mapped_mask; > > + guest_pebs_mask &=3D guest_pebs->enable & ~guest_pebs->cross_ma= pped_mask; >=20 > It would be helpful to save this mask somewhere, so that it can be > used when calculating guest_pebs_idxs in x86_pmu_handle_guest_pebs(). > I think that code needs a fix similar to the one in commit > 58f6217e5d01 ("perf/x86/intel: KVM: Mask PEBS_ENABLE loaded for guest > with vCPU's value."). Blech. This all feels like a losing game of whack-a-mole. Proxying the PM= U through perf is a mediocre approximation for non-PEBS events, and it seems = like it's downright awful for PEBS. Ideally, we'd just rip out all of the perf-= based PEBS virtualization support, and only support PEBS through the mediated PMU= . :-/ Absent drastic measures though, saving the effective guest_pebs_enable in t= he per-CPU tracking does seem like the least awful approach. Though I don't q= uite understand why we can't use GLOBAL_STATUS for x86_pmu_handle_guest_pebs(). = I.e. what happens if x86_pmu_handle_guest_pebs() only processes counters that ac= tually got marked as overflowing? Regardless, I'm not going to try and address that mess in this series. AFA= ICT, it's not urgent, and I don't want to snowball into a broader cleanup.