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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: =?us-ascii?Q?Oi9n+iS1o+sMFscfTP/KIaB6s9YSyecXDschBtjTqz4vkvagsc3r5xIbpDpG?= =?us-ascii?Q?sNySJPZokYBIim++r3jfb4CXmy68gedIvOcvH3JQDgiSJG9FZ5I3R8VqXm/P?= =?us-ascii?Q?nWHQhND5liIaONWN/7NMAeiN/0AlU/aflZv1AArTAd1OwpNENHXvctj7xcY0?= =?us-ascii?Q?MyNkj82fBp23Ijch1A8gjxdMPmkTMvJ/6ArlPHfigPHfxdgjVXWL44jq3zzL?= =?us-ascii?Q?DLs+JwJ6t71YNvKiCgBao5bQXHtdTfCy83fjB3+KCJP0MKqCeb8eHhQQM36G?= =?us-ascii?Q?fqdcBMqz6f850tzkS/5RlhWAw+UKzUkpdI899iIy6Lm+64U1TrJbraCpA/cf?= =?us-ascii?Q?eLqN2pTk9jpwiRZNPO1slaC00QScong9YN8UFWIJRcKFtLBZg8gs1MFulgwx?= =?us-ascii?Q?x4Ly9RXX81O/SEK4QE/PHYzsh1gU4bOY0RupKivB+bY+9deJ3nlbimhMWnD1?= =?us-ascii?Q?vzJYyFrcDibByT1d7ryb1cBwVQ64QNHRMGFS99vbFglj0qa4tA8JxDespsCf?= =?us-ascii?Q?8D+/flK2WvOFhM7TYADsRMoxJiX4NuSGUMbM12QkYI643mP0RcfhrncySCMc?= =?us-ascii?Q?ZX+FCSDmF9kIhuZrD4BhLATNIYrWqXa2E+mObgeB4seiWcdjoMaGoV4tkreU?= =?us-ascii?Q?b1Y9m3NMKd3RbYjJq5UtDz5HC1NDgIBtCj8srVMcA/sSpnhynrRPZkz22Nuh?= =?us-ascii?Q?OIhskniAVPVrGm74rYSn0D0z16TQDPbpnJApkiDqdl7rs69Rk9pZF3s3PYrK?= =?us-ascii?Q?++nJ9AySBb6shYHKHiJTymjULfjKeTxP91JqN9h+0t7O2s329axBASH0le7e?= =?us-ascii?Q?mnRI6LXaiLT/km+BB7XmUWCsZUSGUPlYhSNsRLUmnoi0+F5BDI2ICo47ndE6?= =?us-ascii?Q?Z6j2qTB7Wctc1gEUwPUARQdaVv4W//ht+t1dqL+ayp5/sM8QkNEHS5oLdBhI?= =?us-ascii?Q?bbX4OiWbkRV2MLzfkCeuYlae6+RYsOsT9H5dXxrHQXG/NVi9QWFVcrdwiM2O?= =?us-ascii?Q?kAeUTLZqAsfaAdtJ/ftD0c9nto/fhD+yslwFSS3gJvHitskQf7vKwhsOK5dU?= =?us-ascii?Q?ggqScGCV2e3G1YacQLO8HZHH/9zuMtSaeYOfRHUZidapiH7s1iCQcdMfnitw?= =?us-ascii?Q?J3EyzGX1I/uXFfW48z9I92ri4GLcX0dGTYBN55YZuNvJlDHyc6aY7YeQbo2Z?= =?us-ascii?Q?y5kx9QZ4DtRAvB8eVrZmSat4uKdFRdRrLdrS8pCks3YwXTvtbXQtsJWGi/oA?= =?us-ascii?Q?yk9AKr/vbS0M+Ud79VyY6IUXSbGfib1gPJS2VmAXOUjjpcx8K9abz0Yn1D+9?= =?us-ascii?Q?4Btg5YqXuYMdO20jnMkwDTJahk2lFLcSLIxm0DsB9ZrhEgyC0kSr3QndYFxQ?= =?us-ascii?Q?kShnubcUto6fe/DPVMfQrHvgi8MsYBPaA5i1XulnNOBw+M22K0+TPprXxLtR?= =?us-ascii?Q?9tmyjcyB9KPeopj+fMcQjwu09S0zis+1JGT+JDQY2NeTYjrdBSJ2pLw+HtBK?= =?us-ascii?Q?Sb2DA4PU88i5LFCLGCmm+arTjmRcqOYlPvwtoP4+rtt3LQXsDTZFLZ1iMBis?= =?us-ascii?Q?ayt99RmHjncYIr8YnQkwpFx9KjOUSmsT0hD5pD9Upp+Tykhp+E0Ld/G0upti?= =?us-ascii?Q?r9dNKMQp+/pWw4JEk4CsEtHp80quTeBAz8i6uk+oKQkXOxrGvyLyPJEAgz/I?= =?us-ascii?Q?EY1E3M/rCNVCCkNVKA+XHrTWQOAPFRis3nRKfolriGzPJHck?= X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-Network-Message-Id: f97869e5-cc77-42c8-066a-08dee17223a7 X-MS-Exchange-CrossTenant-AuthSource: BL0PR12MB2370.namprd12.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 14 Jul 2026 06:35:47.7490 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: m2Hbg5a9KZ43mGWyBc3ava3QTwYOLOKGeX5hIpvcRkRHMkmheyRV8Dfx27S+EVH028+Z8i6kRTsMqX3f79S0fw== X-MS-Exchange-Transport-CrossTenantHeadersStamped: DS5PPFF2923D4C1 On Sun, Jul 12, 2026 at 11:11:12PM +0800, Davidlohr Bueso wrote: > From: Harshal Thakkar > > Implement CRB filtering per CXL 4.0 8.2.7.2.2, and extend the > current filtering support beyond HDM. CRB filtering is only > permitted for the DDR Interface, Queue Occupancy, Queue Residency > and Retry event groups (CXL 4.0 Table 13-5), and only when counting > a single event (a single mask bit). For example, to count DDR > activates on channel 2 only: > > perf stat -a -e cxl_pmu_mem0.0/ddr_act,crb_filter_en=1,crb=0x02FFFFFF/ > > Placing the 32-bit CRB value at config2:32-63 leaves the > existing HDM value at config2:0-15 untouched and avoids needing > a new config3. > > Signed-off-by: Harshal Thakkar > Signed-off-by: Davidlohr Bueso > --- > drivers/perf/cxl_pmu.c | 63 ++++++++++++++++++++++++++++++++++++++++-- > 1 file changed, 61 insertions(+), 2 deletions(-) > > diff --git a/drivers/perf/cxl_pmu.c b/drivers/perf/cxl_pmu.c > index 1fc83858f653..ca3361eb832d 100644 > --- a/drivers/perf/cxl_pmu.c > +++ b/drivers/perf/cxl_pmu.c > @@ -110,6 +110,7 @@ struct cxl_pmu_info { > int on_cpu; > struct hlist_node node; > bool filter_hdm; > + bool filter_crb; > int irq; > }; > > @@ -146,6 +147,8 @@ static int cxl_pmu_parse_caps(struct device *dev, struct cxl_pmu_info *info) > info->num_event_capabilities = FIELD_GET(CXL_PMU_CAP_NUM_EVN_CAP_REG_SUP_MSK, val) + 1; > > info->filter_hdm = FIELD_GET(CXL_PMU_CAP_FILTERS_SUP_MSK, val) & CXL_PMU_FILTER_HDM; > + info->filter_crb = FIELD_GET(CXL_PMU_CAP_FILTERS_SUP_MSK, val) & > + CXL_PMU_FILTER_CHAN_RANK_BANK; > if (FIELD_GET(CXL_PMU_CAP_INT, val)) > info->irq = FIELD_GET(CXL_PMU_CAP_MSI_N_MSK, val); > else > @@ -229,6 +232,8 @@ enum { > cxl_pmu_edge_attr, > cxl_pmu_hdm_filter_en_attr, > cxl_pmu_hdm_attr, > + cxl_pmu_crb_filter_en_attr, > + cxl_pmu_crb_attr, > }; > > static struct attribute *cxl_pmu_format_attr[] = { > @@ -240,6 +245,8 @@ static struct attribute *cxl_pmu_format_attr[] = { > [cxl_pmu_edge_attr] = CXL_PMU_FORMAT_ATTR(edge, "config1:17"), > [cxl_pmu_hdm_filter_en_attr] = CXL_PMU_FORMAT_ATTR(hdm_filter_en, "config1:18"), > [cxl_pmu_hdm_attr] = CXL_PMU_FORMAT_ATTR(hdm, "config2:0-15"), > + [cxl_pmu_crb_filter_en_attr] = CXL_PMU_FORMAT_ATTR(crb_filter_en, "config1:19"), > + [cxl_pmu_crb_attr] = CXL_PMU_FORMAT_ATTR(crb, "config2:32-63"), > NULL > }; > > @@ -250,7 +257,9 @@ static struct attribute *cxl_pmu_format_attr[] = { > #define CXL_PMU_ATTR_CONFIG1_INVERT_MSK BIT(16) > #define CXL_PMU_ATTR_CONFIG1_EDGE_MSK BIT(17) > #define CXL_PMU_ATTR_CONFIG1_FILTER_EN_MSK BIT(18) > +#define CXL_PMU_ATTR_CONFIG1_CRB_FILTER_EN_MSK BIT(19) > #define CXL_PMU_ATTR_CONFIG2_HDM_MSK GENMASK(15, 0) > +#define CXL_PMU_ATTR_CONFIG2_CRB_MSK GENMASK_ULL(63, 32) > > static umode_t cxl_pmu_format_is_visible(struct kobject *kobj, > struct attribute *attr, int a) > @@ -267,6 +276,11 @@ static umode_t cxl_pmu_format_is_visible(struct kobject *kobj, > attr == cxl_pmu_format_attr[cxl_pmu_hdm_attr])) > return 0; > > + if (!info->filter_crb && > + (attr == cxl_pmu_format_attr[cxl_pmu_crb_filter_en_attr] || > + attr == cxl_pmu_format_attr[cxl_pmu_crb_attr])) > + return 0; > + > return attr->mode; > } > > @@ -323,6 +337,17 @@ static u16 cxl_pmu_config2_get_hdm_decoder(struct perf_event *event) > return FIELD_GET(CXL_PMU_ATTR_CONFIG2_HDM_MSK, event->attr.config2); > } > > +static u16 cxl_pmu_config1_crb_filter_en(struct perf_event *event) > +{ > + return FIELD_GET(CXL_PMU_ATTR_CONFIG1_CRB_FILTER_EN_MSK, > + event->attr.config1); > +} > + > +static u32 cxl_pmu_config2_get_crb(struct perf_event *event) > +{ > + return FIELD_GET(CXL_PMU_ATTR_CONFIG2_CRB_MSK, event->attr.config2); > +} > + > static ssize_t cxl_pmu_event_sysfs_show(struct device *dev, > struct device_attribute *attr, char *buf) > { > @@ -621,6 +646,32 @@ static int cxl_pmu_event_init(struct perf_event *event) > return -EOPNOTSUPP; > /* TODO: Validation of any filter */ > > + if (cxl_pmu_config1_crb_filter_en(event)) { > + if (!info->filter_crb) > + return -EINVAL; > + /* > + * CRB filtering (Filter ID 1) is only valid for the DDR > + * Interface, Queue Occupancy, Queue Residency and Retry > + * event groups (CXL 4.0 Table 13-5). > + */ > + switch (cxl_pmu_config_get_gid(event)) { > + case CXL_PMU_GID_DDR: > + case CXL_PMU_GID_QUEUE_OCC: Should we also validate the Event Vendor ID? GID namespace is scoped by the Vendor ID, while the groups listed in CXL 4.0 Table 13-5 are under CXL vendor ID. A vendor-specific event could reuse one of these numeric GID and pass this switch even though the CXL CRB rules don't apply to it. I would suggest to reject non-CXL events before the switch """ if (cxl_pmu_config_get_vid(event) != PCI_VENDOR_ID_CXL) return -EINVAL; """ Do you think this make sense to you? Best regards, Richard Cheng. > + case CXL_PMU_GID_QUEUE_RESID: > + case CXL_PMU_GID_RETRY_EVENTS: > + break; > + default: > + return -EINVAL; > + } > + > + /* > + * Filtering while counting multiple events is > + * undefined behavior. > + */ > + if (hweight32(cxl_pmu_config_get_mask(event)) > 1) > + return -EINVAL; > + } > + > /* > * Verify that it is possible to count what was requested. Either must > * be a fixed counter that is a precise match or a configurable counter > @@ -677,8 +728,8 @@ static void cxl_pmu_event_start(struct perf_event *event, int flags) > hwc->state = 0; > > /* > - * Currently only hdm filter control is implemented, this code will > - * want generalizing when more filters are added. > + * Filter ID=0: HDM decoder filter > + * Filter ID=1: Channel/Rank/Bank (CRB) filter > */ > if (info->filter_hdm) { > if (cxl_pmu_config1_hdm_filter_en(event)) > @@ -688,6 +739,14 @@ static void cxl_pmu_event_start(struct perf_event *event, int flags) > writel(cfg, base + CXL_PMU_FILTER_CFG_REG(hwc->idx, 0)); > } > > + if (info->filter_crb) { > + if (cxl_pmu_config1_crb_filter_en(event)) > + cfg = cxl_pmu_config2_get_crb(event); > + else > + cfg = GENMASK(31, 0); /* no filtering if 0xFFFF_FFFF */ > + writel(cfg, base + CXL_PMU_FILTER_CFG_REG(hwc->idx, 1)); > + } > + > cfg = readq(base + CXL_PMU_COUNTER_CFG_REG(hwc->idx)); > cfg |= FIELD_PREP(CXL_PMU_COUNTER_CFG_INT_ON_OVRFLW, 1); > cfg |= FIELD_PREP(CXL_PMU_COUNTER_CFG_FREEZE_ON_OVRFLW, 1); > -- > 2.39.5 >