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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: =?us-ascii?Q?pZo/mjy9xgnSyOv9b5eJWpyda/lWzJLwGva18Zf/HNijKHhXctcvax3QVjnw?= =?us-ascii?Q?dgx4ID773yiiPhzr/2l9vWHJ+W3T0GFRg9BylR9uyPQWj/DgZWDoqnlZ6YKz?= =?us-ascii?Q?Ik/UUcgfV6LDEopJNM1riv9o6pKcsmHgr+zbl7ogUERmwfLcpZAy9DbrXa1Z?= =?us-ascii?Q?ZtywLRSsmXEHW8EhhvA/OLRGdgy5yDetHPgOV1s+BELFGJvfdoTYxmCTVSN+?= =?us-ascii?Q?/vDBz+WYNGcJ9OOv1jhxCnQvwZxVt/77a0pe5Viw+ullVdFoopssXp6m30ww?= =?us-ascii?Q?Rws0XobCvz2VA2NhMRqr/lMxWYBmhsecjWK9oVQKkoOSgbRQbchyG9q8vkQB?= =?us-ascii?Q?X+joKGKJbwudaMwu52SWFWzOsUsaGX8KOjDHNjFy64OkJq3nbDbxqwKOjrAY?= =?us-ascii?Q?ipkUtJ0oVYYksC8a/bakTtczzsGeca45Q9CUxRvauPcjmKtFluBXxTW4xGj9?= =?us-ascii?Q?JyoytOP1cB9fukSmQ+f0OGve8fR+1zQE4AW+8bYVDKmzghNbrygSPUb6im2/?= =?us-ascii?Q?/rtpHr6N3aPbzgEmKeolL98qpTjNFLzLgOldnhSzRvQ1AbTxaYIG8LPdmE1Q?= =?us-ascii?Q?yUIGZfdOcXQWmeh2Va/KAcPMt5z6Hd67GFPy8reYI4FuIJkRNupRBxHbbzOV?= =?us-ascii?Q?WoDKN++tjHgVwrMGctSZwQ+WvEVEf5nCkoWeTk69GUDGt9ETSM+2oV+dPbER?= =?us-ascii?Q?x77Wjbiz8IBh7lqNvdgP1TlmFSSGCd2ZdXwQB22v9M80/gbJR7T1ayBnHuFv?= =?us-ascii?Q?DMeIqhPhHPNrsFkmJQd2uB/oMr0GC33Vsx32zFwfZKNyp3Eq4UBlClvn/rYG?= =?us-ascii?Q?ENBoDm1+rAGrCG3PAsYkXbcAEzS/f/w/m3ulTag4U4JuufsYkdZ2oTuA/6J5?= =?us-ascii?Q?toXmx2Su/39L240rz1KS8xntCFgHfQcU872N6XDEbUskvle4xLIp5QsJotAL?= =?us-ascii?Q?2GLcQnMfHoWkDftFrdsWEYR+koCUyEu6D75cSTkIWiJne4MT8y6pNOxtu0J2?= =?us-ascii?Q?IPathiAxFlr/pcaAc64nFqZqsQ5nW7eka+R8OgH/8TREyulBT5deVSRWzao8?= =?us-ascii?Q?9ke8JjueKMz6p+wYj4EF6ROFgLAoAb6FuzuwLSaNZOeeKl+1SWfj3VESeWm1?= =?us-ascii?Q?DFzacNIF7TpYAr6YRTq0hw8/OnYdgEVY4nzWsm25248nBSpKlZ6E+ARXc/TJ?= =?us-ascii?Q?jTSEha9ERc+EfQUztRsW/uXHmTdfT6uX0MozOz0zxoOX/QDb9QRmTZaicgfl?= =?us-ascii?Q?qjUGziW3hO/B+OyLa/sFMVPGGFGDBAATQ1tN1ogpdr4w5TPkrXRE41ceeWyd?= =?us-ascii?Q?DHKY6lQyW5vYtTcXjRZblk+XZnqxl+yDbzkfHnK7z+N47X05hzvjM11mJFHI?= =?us-ascii?Q?6R8vQ2HWS719VuMtKGwD4AcIehlz49Z3A2SeaSpmkLqi1iob3s4/oNY72k6x?= =?us-ascii?Q?4zYpAJPaCnYW900Q4D1HwTRVbY+oHg1CwHeCpY2H2O7wVgH+61BOuSSrPCnc?= =?us-ascii?Q?9001+UFWWZhrsrT7GjdssjFTCg2W+Yyd3Ss70TXnY29jKDpBGkP7h//o9ixS?= =?us-ascii?Q?ooBVgpe5ZHUcuVlGbQhVixJ9dsfsuaGNOHUzp+jv6vmcHEQjfzSWHOclS/7P?= =?us-ascii?Q?Ft4b82r5LFdyqKSQSKxJpxUiTcx18pw95Mzo3pavHtv1/9lf5UQDXBlxEbr8?= =?us-ascii?Q?inSbL3926ChsciLTS7KxH6lxVKdy6JDIgeaMpFQoEaZstJIk?= X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-Network-Message-Id: 77e338d3-ecbb-4bf2-9c06-08def113bcfc X-MS-Exchange-CrossTenant-AuthSource: DM5PR12MB2376.namprd12.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 03 Aug 2026 04:00:21.5626 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: RV84YlFqWhl9I5OGkntN2qR58VvqDBUWieKmKzimqO+QSkJtmIz97jpJws7GorqYYcRwqGHv61pidjon9TKvsw== X-MS-Exchange-Transport-CrossTenantHeadersStamped: LV2PR12MB5871 On Fri, Jul 31, 2026 at 04:28:25PM +0800, Dave Jiang wrote: > The counters run with Freeze on Overflow set, so one overflow freezes every > counter in the block (CXL r4.0 8.2.7.2.1). cxl_pmu_irq() reads the > overflowed counters and clears the overflow status, but never unfreezes. > Everything stays frozen until the next pmu_enable(), and events in that > window are lost. > > Unfreeze after clearing the status, unless the PMU has been disabled in the > meantime. cxl_pmu_disable() freezes the block deliberately, and > cxl_pmu_offline_cpu() migrates the context before it moves the interrupt's > affinity, so an overflow can still land on the old CPU while the new one > reprograms. Track the enabled state and leave the block frozen in that > case. pmu_enable() unfreezes anyway. > > Fixes: 5d7107c72796 ("perf: CXL Performance Monitoring Unit driver") > Reported-by: sashiko-bot@kernel.org > Closes: https://sashiko.dev/#/patchset/20260715191454.459673-1-dave@stgolabs.net?part=1 > Assisted-by: Claude:claude-opus-4-8 > Signed-off-by: Dave Jiang > --- > v3: > - Don't unfreeze if the PMU has been disabled (Robin, Jonathan). Review tag > dropped as the patch grew a hunk. > - Robin also asked whether this can release a counter that overflowed after > the status read. It cannot. Global Freeze on Overflow stops every > non-free-running counter and they stay frozen until software unfreezes > them, so nothing the driver owns can advance, let alone newly overflow, > between the readq and here. Two counters overflowing together both show > up in the same pass. Only free-running counters move while frozen, and > the driver never programs those. > - The enabled check is not a full exclusion, since the flag is read outside > any lock. Say so in the comment rather than implying otherwise. A lock > would buy nothing: pmu_disable() normally runs on the pinned CPU with > interrupts off, and in the one window where it does not - the migration > in cxl_pmu_offline_cpu() - event_stop() has already cleared Counter > Enable, so a stray unfreeze resumes nothing (sashiko-bot). > --- > drivers/perf/cxl_pmu.c | 7 +++++++ > 1 file changed, 7 insertions(+) > > diff --git a/drivers/perf/cxl_pmu.c b/drivers/perf/cxl_pmu.c > index 6fdc66a01fb6..580a75bc9210 100644 > --- a/drivers/perf/cxl_pmu.c > +++ b/drivers/perf/cxl_pmu.c > @@ -108,6 +108,8 @@ struct cxl_pmu_info { > bool filter_hdm; > int msi_vec; > int irq; > + /* Set between pmu_enable() and pmu_disable(), read by the IRQ handler */ > + bool enabled; > }; > > #define pmu_to_cxl_pmu_info(_pmu) container_of(_pmu, struct cxl_pmu_info, pmu) > @@ -596,6 +598,7 @@ static void cxl_pmu_enable(struct pmu *pmu) > void __iomem *base = info->base; > > /* Can assume frozen at this stage */ > + WRITE_ONCE(info->enabled, true); > writeq(0, base + CXL_PMU_FREEZE_REG); > } > > @@ -604,6 +607,7 @@ static void cxl_pmu_disable(struct pmu *pmu) > struct cxl_pmu_info *info = pmu_to_cxl_pmu_info(pmu); > void __iomem *base = info->base; > > + WRITE_ONCE(info->enabled, false); > /* > * Whilst bits above number of counters are RsvdZ > * they are unlikely to be repurposed given > @@ -803,6 +807,9 @@ static irqreturn_t cxl_pmu_irq(int irq, void *data) > > writeq(overflowed, base + CXL_PMU_OVERFLOW_REG); > > + if (READ_ONCE(info->enabled)) > + writeq(0, base + CXL_PMU_FREEZE_REG); > + The unfreeze looks right to me. Maybe we should quote the corresponding part in spec as needed? CXL 4.0 8.2.7.1.3 "CPMU Freeze (Offset 18h)", Table 8-183 - "Counter Unit N remains frozen until explicitly unfrozen by software" . I guess Robin's hotplug rework is solving the issue of cross-CPU check-then-act ? --Richard > return IRQ_HANDLED; > } > > -- > 2.55.0 > >