Re: [Patch v2] perf/x86/msr: Make SMI and PPERF on by default

["Chen, Zide" <zide.chen@intel.com>]

On 3/26/2026 10:28 PM, Dapeng Mi wrote:
> From: Kan Liang <kan.liang@linux.intel.com>
> 
> The MSRs, SMI_COUNT and PPERF, are model-specific MSRs. A very long
> CPU ID list is maintained to indicate the supported platforms. With more
> and more platforms being introduced, new CPU IDs have to be kept adding.
> Also, the old kernel has to be updated to apply the new CPU ID.
> 
> The MSRs have been introduced for a long time. There is no plan to
> change them in the near future. Furthermore, the current code utilizes
> rdmsr_safe() to check the availability of MSRs before using it.
> 
> Make them on by default. It should be good enough to only rely on the
> rdmsr_safe() to check their availability for both existing and future
> platforms.
> 
> Signed-off-by: Kan Liang <kan.liang@linux.intel.com>
> Co-developed-by: Dapeng Mi <dapeng1.mi@linux.intel.com>
> Signed-off-by: Dapeng Mi <dapeng1.mi@linux.intel.com>
> ---

Reviewed-by: Zide Chen <zide.chen@intel.com>

> 
> V2: Removed stale #include <asm/cpu_device_id.h>.
> 
> V1: https://lore.kernel.org/lkml/20240910192626.768146-1-kan.liang@linux.intel.com/
> 
>  arch/x86/events/msr.c | 82 ++-----------------------------------------
>  1 file changed, 3 insertions(+), 79 deletions(-)
> 
> diff --git a/arch/x86/events/msr.c b/arch/x86/events/msr.c
> index 8052596b8503..76d6418c5055 100644
> --- a/arch/x86/events/msr.c
> +++ b/arch/x86/events/msr.c
> @@ -2,7 +2,6 @@
>  #include <linux/perf_event.h>
>  #include <linux/sysfs.h>
>  #include <linux/nospec.h>
> -#include <asm/cpu_device_id.h>
>  #include <asm/msr.h>
>  
>  #include "probe.h"
> @@ -41,86 +40,11 @@ static bool test_therm_status(int idx, void *data)
>  
>  static bool test_intel(int idx, void *data)
>  {
> -	if (boot_cpu_data.x86_vendor != X86_VENDOR_INTEL ||
> -	    boot_cpu_data.x86 != 6)
> +	if (boot_cpu_data.x86_vendor != X86_VENDOR_INTEL)
>  		return false;
>  
> -	switch (boot_cpu_data.x86_vfm) {
> -	case INTEL_NEHALEM:
> -	case INTEL_NEHALEM_G:
> -	case INTEL_NEHALEM_EP:
> -	case INTEL_NEHALEM_EX:
> -
> -	case INTEL_WESTMERE:
> -	case INTEL_WESTMERE_EP:
> -	case INTEL_WESTMERE_EX:
> -
> -	case INTEL_SANDYBRIDGE:
> -	case INTEL_SANDYBRIDGE_X:
> -
> -	case INTEL_IVYBRIDGE:
> -	case INTEL_IVYBRIDGE_X:
> -
> -	case INTEL_HASWELL:
> -	case INTEL_HASWELL_X:
> -	case INTEL_HASWELL_L:
> -	case INTEL_HASWELL_G:
> -
> -	case INTEL_BROADWELL:
> -	case INTEL_BROADWELL_D:
> -	case INTEL_BROADWELL_G:
> -	case INTEL_BROADWELL_X:
> -	case INTEL_SAPPHIRERAPIDS_X:
> -	case INTEL_EMERALDRAPIDS_X:
> -	case INTEL_GRANITERAPIDS_X:
> -	case INTEL_GRANITERAPIDS_D:
> -
> -	case INTEL_ATOM_SILVERMONT:
> -	case INTEL_ATOM_SILVERMONT_D:
> -	case INTEL_ATOM_AIRMONT:
> -	case INTEL_ATOM_AIRMONT_NP:
> -
> -	case INTEL_ATOM_GOLDMONT:
> -	case INTEL_ATOM_GOLDMONT_D:
> -	case INTEL_ATOM_GOLDMONT_PLUS:
> -	case INTEL_ATOM_TREMONT_D:
> -	case INTEL_ATOM_TREMONT:
> -	case INTEL_ATOM_TREMONT_L:
> -
> -	case INTEL_XEON_PHI_KNL:
> -	case INTEL_XEON_PHI_KNM:
> -		if (idx == PERF_MSR_SMI)
> -			return true;
> -		break;
> -
> -	case INTEL_SKYLAKE_L:
> -	case INTEL_SKYLAKE:
> -	case INTEL_SKYLAKE_X:
> -	case INTEL_KABYLAKE_L:
> -	case INTEL_KABYLAKE:
> -	case INTEL_COMETLAKE_L:
> -	case INTEL_COMETLAKE:
> -	case INTEL_ICELAKE_L:
> -	case INTEL_ICELAKE:
> -	case INTEL_ICELAKE_X:
> -	case INTEL_ICELAKE_D:
> -	case INTEL_TIGERLAKE_L:
> -	case INTEL_TIGERLAKE:
> -	case INTEL_ROCKETLAKE:
> -	case INTEL_ALDERLAKE:
> -	case INTEL_ALDERLAKE_L:
> -	case INTEL_ATOM_GRACEMONT:
> -	case INTEL_RAPTORLAKE:
> -	case INTEL_RAPTORLAKE_P:
> -	case INTEL_RAPTORLAKE_S:
> -	case INTEL_METEORLAKE:
> -	case INTEL_METEORLAKE_L:
> -		if (idx == PERF_MSR_SMI || idx == PERF_MSR_PPERF)
> -			return true;
> -		break;
> -	}
> -
> -	return false;
> +	/* Rely on perf_msr_probe() to check the availability */
> +	return true;
>  }
>  
>  PMU_EVENT_ATTR_STRING(tsc,				attr_tsc,		"event=0x00"	);
> 
> base-commit: 6ee26b7a224b27aa7e8e1ee8a845a31664d2e97c