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Thu, 15 Oct 2026 01:49:45 -0500 Message-ID: Date: Thu, 15 Oct 2026 12:19:39 +0530 Precedence: bulk X-Mailing-List: linux-perf-users@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 3/3] perf/amd/ibs: Simplify event state handling with IBS_CAPS_DIS To: CC: , Ravi Bangoria References: <20261015060430.5877-1-ravi.bangoria@amd.com> <20261015060430.5877-4-ravi.bangoria@amd.com> Content-Language: en-US From: Ravi Bangoria In-Reply-To: Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: 7bit X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: LV8PEPF00000066:EE_|CH3PR12MB8936:EE_ X-MS-Office365-Filtering-Correlation-Id: 924ba1a6-4c45-4cff-a2a5-08df2a8884af X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|23010399003|82310400026|36860700016|1800799024|376014|18002099003|22082099003|10067099003|4143699003|11063799006|56012099006; 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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: zsl+zBf7SIKTXZQ7qO9fxTwstRWWe+oDhbERKPEHBPMbfpAEJT49OwuxHhYb9heEtFrdxe3d2yi38sSZv8ckjBzbXQJme7PugwsjH8HM50z04tXkN2BqgXL7+MbgjhJmU6+otM0tVDhWlHRiUgm9sqnNDqiOrhSEOeVMxruPCiydVlZadzskVIRcBWw7VeD2LGauMFixVB3ECamAf/nA4tIIdub2kxSprWH44G5aSvvT/sRqNomZEmYkRc0wZ7XmrwroHxxiNrsUHtk6CTB1BicyGi2HodrpF5Vqot503N60rqrQQ1zLlFgjYqf904K7hJv54xmyknLN77jwuFvns1O1DTsc06yhTIEFs7lKMn3kPApkt6w5wPOA+el8mhJEkMv3yWttdyXjTBkBpZ8iI8ssKvHg7R4nvwkw37fpoOz3ySFQUmegdm+vlP+hSSyD X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 15 Oct 2026 06:49:53.9538 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 924ba1a6-4c45-4cff-a2a5-08df2a8884af X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[satlexmb07.amd.com] X-MS-Exchange-CrossTenant-AuthSource: LV8PEPF00000066.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CH3PR12MB8936 >> + if (ibs_caps & IBS_CAPS_DIS) { >> + /* >> + * IBS HW SW >> + * >> + * o Capture sample o ->stop() >> + * o Set VAL bit CTL2[Dis] = 1 >> + * o Raise NMI --. o ... >> + * \ o ->start() >> + * \ wrmsr(IBS_{FETCH|OP}_CTL, new value); >> + * \ (wrmsr clears the VAL bit) >> + * `--> o Receives delayed NMI >> + * (Unknown NMI since VAL bit is cleared) >> + * >> + * Handle this with induced delay. >> + */ >> + rdmsrq(hwc->config_base, ctl); >> + while ((ctl & perf_ibs->valid_mask) && delay--) { >> + udelay(1); >> + rdmsrq(hwc->config_base, ctl); >> + } > > [Severity: High] > What happens if the delayed NMI takes longer than 50us to arrive, for > example due to hypervisor scheduling, nested virtualization, or SMIs? > > If this delay loop expires, the code proceeds to call > perf_ibs_enable_event() which clears the VAL and CTL2[Dis] bits. When the > delayed NMI eventually arrives, it appears it will be treated as an > unhandled NMI. A delay exceeding 50us is highly unlikely in practice, and even if it occurs, the consequence is "Unknown NMI", which is not fatal. Thanks, Ravi