[PATCH v1 00/32] Refresh Intel vendor events

[PATCH v1 00/32] Refresh Intel vendor events

[Ian Rogers]

Use new repository [1] and converter script to regenerate Intel vendor
metrics. In particular this change removes unnecessary json fields and
correct uncore events that previously had a buggy converter.

[1] https://github.com/intel/perfmon/

Ian Rogers (32):
  perf test pmu-events: Fake PMU metric workaround
  perf vendor events intel: Refresh alderlake metrics
  perf vendor events intel: Refresh alderlake-n metrics
  perf vendor events intel: Refresh bonnell events
  perf vendor events intel: Refresh broadwell metrics and events
  perf vendor events intel: Refresh broadwellde metrics and events
  perf vendor events intel: Refresh broadwellx metrics and events
  perf vendor events intel: Refresh cascadelakex metrics and events
  perf vendor events intel: Refresh elkhartlake events
  perf vendor events intel: Refresh goldmont events
  perf vendor events intel: Refresh goldmontplus events
  perf vendor events intel: Refresh haswell metrics and events
  perf vendor events intel: Refresh haswellx metrics and events
  perf vendor events intel: Refresh icelake metrics and events
  perf vendor events intel: Refresh icelakex metrics and events
  perf vendor events intel: Refresh ivybridge metrics and events
  perf vendor events intel: Refresh ivytown metrics and events
  perf vendor events intel: Refresh jaketown metrics and events
  perf vendor events intel: Refresh knightslanding events
  perf vendor events intel: Refresh meteorlake events
  perf vendor events intel: Refresh nehalemep events
  perf vendor events intel: Refresh nehalemex events
  perf vendor events intel: Refresh sandybridge metrics and events
  perf vendor events intel: Refresh sapphirerapids metrics and events
  perf vendor events intel: Refresh silvermont events
  perf vendor events intel: Refresh skylake metrics and events
  perf vendor events intel: Refresh skylakex metrics and events
  perf vendor events intel: Refresh snowridgex events
  perf vendor events intel: Refresh tigerlake metrics and events
  perf vendor events intel: Refresh westmereep-dp events
  perf vendor events intel: Refresh westmereep-sp events
  perf vendor events intel: Refresh westmereex events

 .../arch/x86/alderlake/adl-metrics.json       |   116 +-
 .../arch/x86/alderlaken/adln-metrics.json     |    22 +-
 .../pmu-events/arch/x86/bonnell/cache.json    |    93 -
 .../arch/x86/bonnell/floating-point.json      |    47 +-
 .../pmu-events/arch/x86/bonnell/frontend.json |    11 -
 .../pmu-events/arch/x86/bonnell/memory.json   |    19 -
 .../pmu-events/arch/x86/bonnell/other.json    |    74 +-
 .../pmu-events/arch/x86/bonnell/pipeline.json |    65 +-
 .../arch/x86/bonnell/virtual-memory.json      |    15 -
 .../arch/x86/broadwell/bdw-metrics.json       |   137 +-
 .../pmu-events/arch/x86/broadwell/cache.json  |   957 -
 .../arch/x86/broadwell/floating-point.json    |    40 -
 .../arch/x86/broadwell/frontend.json          |    56 -
 .../pmu-events/arch/x86/broadwell/memory.json |   890 -
 .../pmu-events/arch/x86/broadwell/other.json  |     8 -
 .../arch/x86/broadwell/pipeline.json          |   272 -
 .../arch/x86/broadwell/uncore-cache.json      |    19 -
 .../arch/x86/broadwell/uncore-other.json      |    25 +-
 .../arch/x86/broadwell/virtual-memory.json    |    76 -
 .../arch/x86/broadwellde/bdwde-metrics.json   |   143 +-
 .../arch/x86/broadwellde/cache.json           |   153 -
 .../arch/x86/broadwellde/floating-point.json  |    40 -
 .../arch/x86/broadwellde/frontend.json        |    56 -
 .../arch/x86/broadwellde/memory.json          |    86 -
 .../arch/x86/broadwellde/other.json           |     8 -
 .../arch/x86/broadwellde/pipeline.json        |   272 -
 .../arch/x86/broadwellde/uncore-cache.json    |   414 +-
 .../arch/x86/broadwellde/uncore-memory.json   |   477 +-
 .../arch/x86/broadwellde/uncore-other.json    |   163 +-
 .../arch/x86/broadwellde/uncore-power.json    |    57 -
 .../arch/x86/broadwellde/virtual-memory.json  |    76 -
 .../arch/x86/broadwellx/bdx-metrics.json      |  1703 +-
 .../pmu-events/arch/x86/broadwellx/cache.json |   191 -
 .../arch/x86/broadwellx/floating-point.json   |    40 -
 .../arch/x86/broadwellx/frontend.json         |    56 -
 .../arch/x86/broadwellx/memory.json           |   143 -
 .../pmu-events/arch/x86/broadwellx/other.json |     8 -
 .../arch/x86/broadwellx/pipeline.json         |   272 -
 .../arch/x86/broadwellx/uncore-cache.json     |  3740 +-
 .../x86/broadwellx/uncore-interconnect.json   |  1225 +-
 .../arch/x86/broadwellx/uncore-memory.json    |  2052 +-
 .../arch/x86/broadwellx/uncore-other.json     |  2410 +-
 .../arch/x86/broadwellx/uncore-power.json     |   198 +-
 .../arch/x86/broadwellx/virtual-memory.json   |    76 -
 .../arch/x86/cascadelakex/cache.json          |  3644 --
 .../arch/x86/cascadelakex/clx-metrics.json    |  2217 +-
 .../arch/x86/cascadelakex/floating-point.json |    24 -
 .../arch/x86/cascadelakex/frontend.json       |   109 -
 .../arch/x86/cascadelakex/memory.json         |  2194 -
 .../arch/x86/cascadelakex/other.json          |   490 -
 .../arch/x86/cascadelakex/pipeline.json       |   194 -
 .../arch/x86/cascadelakex/uncore-memory.json  |  3185 +-
 .../arch/x86/cascadelakex/uncore-other.json   | 29444 +++++-----
 .../arch/x86/cascadelakex/uncore-power.json   |    45 +-
 .../arch/x86/cascadelakex/virtual-memory.json |    56 -
 .../arch/x86/elkhartlake/cache.json           |   252 -
 .../arch/x86/elkhartlake/floating-point.json  |    11 -
 .../arch/x86/elkhartlake/frontend.json        |    36 -
 .../arch/x86/elkhartlake/memory.json          |    84 -
 .../arch/x86/elkhartlake/other.json           |   143 -
 .../arch/x86/elkhartlake/pipeline.json        |   213 -
 .../arch/x86/elkhartlake/virtual-memory.json  |   117 -
 .../pmu-events/arch/x86/goldmont/cache.json   |   288 -
 .../arch/x86/goldmont/floating-point.json     |     6 -
 .../arch/x86/goldmont/frontend.json           |    16 -
 .../pmu-events/arch/x86/goldmont/memory.json  |     6 -
 .../pmu-events/arch/x86/goldmont/other.json   |    10 -
 .../arch/x86/goldmont/pipeline.json           |    77 -
 .../arch/x86/goldmont/virtual-memory.json     |    14 -
 .../arch/x86/goldmontplus/cache.json          |   470 -
 .../arch/x86/goldmontplus/floating-point.json |    11 -
 .../arch/x86/goldmontplus/frontend.json       |    32 -
 .../arch/x86/goldmontplus/memory.json         |    10 -
 .../arch/x86/goldmontplus/other.json          |    20 -
 .../arch/x86/goldmontplus/pipeline.json       |   143 -
 .../arch/x86/goldmontplus/virtual-memory.json |    69 -
 .../pmu-events/arch/x86/haswell/cache.json    |   211 -
 .../arch/x86/haswell/floating-point.json      |    20 -
 .../pmu-events/arch/x86/haswell/frontend.json |    58 -
 .../arch/x86/haswell/hsw-metrics.json         |   117 +-
 .../pmu-events/arch/x86/haswell/memory.json   |   149 -
 .../pmu-events/arch/x86/haswell/other.json    |     8 -
 .../pmu-events/arch/x86/haswell/pipeline.json |   258 -
 .../arch/x86/haswell/uncore-cache.json        |    50 -
 .../arch/x86/haswell/uncore-other.json        |    21 +-
 .../arch/x86/haswell/virtual-memory.json      |    98 -
 .../pmu-events/arch/x86/haswellx/cache.json   |   217 -
 .../arch/x86/haswellx/floating-point.json     |    20 -
 .../arch/x86/haswellx/frontend.json           |    58 -
 .../arch/x86/haswellx/hsx-metrics.json        |  1467 +-
 .../pmu-events/arch/x86/haswellx/memory.json  |   170 -
 .../pmu-events/arch/x86/haswellx/other.json   |     8 -
 .../arch/x86/haswellx/pipeline.json           |   258 -
 .../arch/x86/haswellx/uncore-cache.json       |  2448 +-
 .../x86/haswellx/uncore-interconnect.json     |   722 +-
 .../arch/x86/haswellx/uncore-memory.json      |  2037 +-
 .../arch/x86/haswellx/uncore-other.json       |  1834 +-
 .../arch/x86/haswellx/uncore-power.json       |   150 +-
 .../arch/x86/haswellx/virtual-memory.json     |    98 -
 .../pmu-events/arch/x86/icelake/cache.json    |   412 -
 .../arch/x86/icelake/floating-point.json      |    28 -
 .../pmu-events/arch/x86/icelake/frontend.json |   144 -
 .../arch/x86/icelake/icl-metrics.json         |   151 +-
 .../pmu-events/arch/x86/icelake/memory.json   |   171 -
 .../pmu-events/arch/x86/icelake/other.json    |   132 -
 .../pmu-events/arch/x86/icelake/pipeline.json |   349 +-
 .../arch/x86/icelake/uncore-other.json        |    10 +-
 .../arch/x86/icelake/virtual-memory.json      |    80 -
 .../pmu-events/arch/x86/icelakex/cache.json   |   316 +-
 .../arch/x86/icelakex/floating-point.json     |    28 -
 .../arch/x86/icelakex/frontend.json           |   140 -
 .../arch/x86/icelakex/icx-metrics.json        |  2192 +-
 .../pmu-events/arch/x86/icelakex/memory.json  |   139 +-
 .../pmu-events/arch/x86/icelakex/other.json   |   117 -
 .../arch/x86/icelakex/pipeline.json           |   344 +-
 .../arch/x86/icelakex/uncore-memory.json      |  1878 +-
 .../arch/x86/icelakex/uncore-other.json       | 45144 +++++++---------
 .../arch/x86/icelakex/uncore-power.json       |   115 +-
 .../arch/x86/icelakex/virtual-memory.json     |    88 -
 .../pmu-events/arch/x86/ivybridge/cache.json  |   235 -
 .../arch/x86/ivybridge/floating-point.json    |    34 -
 .../arch/x86/ivybridge/frontend.json          |    60 -
 .../arch/x86/ivybridge/ivb-metrics.json       |   119 +-
 .../pmu-events/arch/x86/ivybridge/memory.json |    54 -
 .../pmu-events/arch/x86/ivybridge/other.json  |     8 -
 .../arch/x86/ivybridge/pipeline.json          |   250 -
 .../arch/x86/ivybridge/uncore-cache.json      |    50 -
 .../arch/x86/ivybridge/uncore-other.json      |    28 +-
 .../arch/x86/ivybridge/virtual-memory.json    |    36 -
 .../pmu-events/arch/x86/ivytown/cache.json    |   274 -
 .../arch/x86/ivytown/floating-point.json      |    34 -
 .../pmu-events/arch/x86/ivytown/frontend.json |    60 -
 .../arch/x86/ivytown/ivt-metrics.json         |   133 +-
 .../pmu-events/arch/x86/ivytown/memory.json   |   121 -
 .../pmu-events/arch/x86/ivytown/other.json    |     8 -
 .../pmu-events/arch/x86/ivytown/pipeline.json |   250 -
 .../arch/x86/ivytown/uncore-cache.json        |   388 +-
 .../arch/x86/ivytown/uncore-interconnect.json |   505 +-
 .../arch/x86/ivytown/uncore-memory.json       |   209 +-
 .../arch/x86/ivytown/uncore-other.json        |   254 +-
 .../arch/x86/ivytown/uncore-power.json        |    95 -
 .../arch/x86/ivytown/virtual-memory.json      |    40 -
 .../pmu-events/arch/x86/jaketown/cache.json   |   289 -
 .../arch/x86/jaketown/floating-point.json     |    30 -
 .../arch/x86/jaketown/frontend.json           |    64 -
 .../arch/x86/jaketown/jkt-metrics.json        |    91 +-
 .../pmu-events/arch/x86/jaketown/memory.json  |   103 -
 .../pmu-events/arch/x86/jaketown/other.json   |    12 -
 .../arch/x86/jaketown/pipeline.json           |   255 -
 .../arch/x86/jaketown/uncore-cache.json       |   266 +-
 .../x86/jaketown/uncore-interconnect.json     |   132 -
 .../arch/x86/jaketown/uncore-memory.json      |    58 -
 .../arch/x86/jaketown/uncore-other.json       |   155 +-
 .../arch/x86/jaketown/uncore-power.json       |    51 -
 .../arch/x86/jaketown/virtual-memory.json     |    32 -
 .../arch/x86/knightslanding/cache.json        |   411 -
 .../x86/knightslanding/floating-point.json    |     3 -
 .../arch/x86/knightslanding/frontend.json     |     7 -
 .../arch/x86/knightslanding/memory.json       |   201 -
 .../arch/x86/knightslanding/pipeline.json     |    44 -
 .../arch/x86/knightslanding/uncore-other.json |  1040 +-
 .../x86/knightslanding/virtual-memory.json    |     7 -
 tools/perf/pmu-events/arch/x86/mapfile.csv    |    14 +-
 .../pmu-events/arch/x86/meteorlake/cache.json |   170 +-
 .../arch/x86/meteorlake/frontend.json         |     6 -
 .../arch/x86/meteorlake/memory.json           |    77 +-
 .../pmu-events/arch/x86/meteorlake/other.json |    24 +-
 .../arch/x86/meteorlake/pipeline.json         |   222 +-
 .../arch/x86/meteorlake/virtual-memory.json   |    28 +-
 .../pmu-events/arch/x86/nehalemep/cache.json  |   524 -
 .../arch/x86/nehalemep/floating-point.json    |    28 -
 .../arch/x86/nehalemep/frontend.json          |     3 -
 .../pmu-events/arch/x86/nehalemep/memory.json |   134 -
 .../pmu-events/arch/x86/nehalemep/other.json  |    18 -
 .../arch/x86/nehalemep/pipeline.json          |   127 +-
 .../arch/x86/nehalemep/virtual-memory.json    |    13 -
 .../pmu-events/arch/x86/nehalemex/cache.json  |   519 -
 .../arch/x86/nehalemex/floating-point.json    |    28 -
 .../arch/x86/nehalemex/frontend.json          |     3 -
 .../pmu-events/arch/x86/nehalemex/memory.json |   134 -
 .../pmu-events/arch/x86/nehalemex/other.json  |    18 -
 .../arch/x86/nehalemex/pipeline.json          |   127 +-
 .../arch/x86/nehalemex/virtual-memory.json    |    13 -
 .../arch/x86/sandybridge/cache.json           |   441 -
 .../arch/x86/sandybridge/floating-point.json  |    30 -
 .../arch/x86/sandybridge/frontend.json        |    64 -
 .../arch/x86/sandybridge/memory.json          |   108 -
 .../arch/x86/sandybridge/other.json           |    12 -
 .../arch/x86/sandybridge/pipeline.json        |   257 -
 .../arch/x86/sandybridge/snb-metrics.json     |    83 +-
 .../arch/x86/sandybridge/uncore-cache.json    |    50 -
 .../arch/x86/sandybridge/uncore-other.json    |    28 +-
 .../arch/x86/sandybridge/virtual-memory.json  |    32 -
 .../arch/x86/sapphirerapids/cache.json        |   350 +-
 .../x86/sapphirerapids/floating-point.json    |    63 -
 .../arch/x86/sapphirerapids/frontend.json     |   144 -
 .../arch/x86/sapphirerapids/memory.json       |   125 +-
 .../arch/x86/sapphirerapids/other.json        |    91 +-
 .../arch/x86/sapphirerapids/pipeline.json     |   424 +-
 .../arch/x86/sapphirerapids/spr-metrics.json  |  2309 +-
 .../x86/sapphirerapids/uncore-memory.json     |   526 +-
 .../arch/x86/sapphirerapids/uncore-other.json |  6606 +--
 .../arch/x86/sapphirerapids/uncore-power.json |    84 +-
 .../x86/sapphirerapids/virtual-memory.json    |    80 -
 .../pmu-events/arch/x86/silvermont/cache.json |   133 -
 .../arch/x86/silvermont/floating-point.json   |     1 -
 .../arch/x86/silvermont/frontend.json         |     8 -
 .../arch/x86/silvermont/memory.json           |     1 -
 .../pmu-events/arch/x86/silvermont/other.json |     2 -
 .../arch/x86/silvermont/pipeline.json         |    35 -
 .../arch/x86/silvermont/virtual-memory.json   |     7 -
 .../pmu-events/arch/x86/skylake/cache.json    |   660 -
 .../arch/x86/skylake/floating-point.json      |    14 -
 .../pmu-events/arch/x86/skylake/frontend.json |   109 -
 .../pmu-events/arch/x86/skylake/memory.json   |   358 -
 .../pmu-events/arch/x86/skylake/other.json    |     4 -
 .../pmu-events/arch/x86/skylake/pipeline.json |   192 -
 .../arch/x86/skylake/skl-metrics.json         |   155 +-
 .../arch/x86/skylake/uncore-cache.json        |    18 -
 .../arch/x86/skylake/uncore-other.json        |    31 +-
 .../arch/x86/skylake/virtual-memory.json      |    56 -
 .../pmu-events/arch/x86/skylakex/cache.json   |   368 -
 .../arch/x86/skylakex/floating-point.json     |    18 -
 .../arch/x86/skylakex/frontend.json           |   109 -
 .../pmu-events/arch/x86/skylakex/memory.json  |   310 -
 .../pmu-events/arch/x86/skylakex/other.json   |    30 -
 .../arch/x86/skylakex/pipeline.json           |   194 -
 .../arch/x86/skylakex/skx-metrics.json        |  2134 +-
 .../arch/x86/skylakex/uncore-memory.json      |  2303 +-
 .../arch/x86/skylakex/uncore-other.json       | 29356 +++++-----
 .../arch/x86/skylakex/uncore-power.json       |    45 +-
 .../arch/x86/skylakex/virtual-memory.json     |    56 -
 .../pmu-events/arch/x86/snowridgex/cache.json |   252 -
 .../arch/x86/snowridgex/floating-point.json   |    11 -
 .../arch/x86/snowridgex/frontend.json         |    36 -
 .../arch/x86/snowridgex/memory.json           |    84 -
 .../pmu-events/arch/x86/snowridgex/other.json |   143 -
 .../arch/x86/snowridgex/pipeline.json         |   213 -
 .../arch/x86/snowridgex/uncore-memory.json    |   624 +-
 .../arch/x86/snowridgex/uncore-other.json     | 26334 ++++-----
 .../arch/x86/snowridgex/uncore-power.json     |   114 +-
 .../arch/x86/snowridgex/virtual-memory.json   |   117 -
 .../pmu-events/arch/x86/tigerlake/cache.json  |   210 +-
 .../arch/x86/tigerlake/floating-point.json    |    27 -
 .../arch/x86/tigerlake/frontend.json          |   125 -
 .../pmu-events/arch/x86/tigerlake/memory.json |    77 -
 .../pmu-events/arch/x86/tigerlake/other.json  |    13 -
 .../arch/x86/tigerlake/pipeline.json          |   287 +-
 .../arch/x86/tigerlake/tgl-metrics.json       |   141 +-
 .../arch/x86/tigerlake/uncore-other.json      |    96 +-
 .../arch/x86/tigerlake/virtual-memory.json    |    60 -
 .../arch/x86/westmereep-dp/cache.json         |   445 -
 .../x86/westmereep-dp/floating-point.json     |    28 -
 .../arch/x86/westmereep-dp/frontend.json      |     3 -
 .../arch/x86/westmereep-dp/memory.json        |   137 -
 .../arch/x86/westmereep-dp/other.json         |    22 -
 .../arch/x86/westmereep-dp/pipeline.json      |   129 +-
 .../x86/westmereep-dp/virtual-memory.json     |    21 -
 .../arch/x86/westmereep-sp/cache.json         |   517 -
 .../x86/westmereep-sp/floating-point.json     |    28 -
 .../arch/x86/westmereep-sp/frontend.json      |     3 -
 .../arch/x86/westmereep-sp/memory.json        |   134 -
 .../arch/x86/westmereep-sp/other.json         |    22 -
 .../arch/x86/westmereep-sp/pipeline.json      |   129 +-
 .../x86/westmereep-sp/virtual-memory.json     |    18 -
 .../pmu-events/arch/x86/westmereex/cache.json |   516 -
 .../arch/x86/westmereex/floating-point.json   |    28 -
 .../arch/x86/westmereex/frontend.json         |     3 -
 .../arch/x86/westmereex/memory.json           |   135 -
 .../pmu-events/arch/x86/westmereex/other.json |    22 -
 .../arch/x86/westmereex/pipeline.json         |   129 +-
 .../arch/x86/westmereex/virtual-memory.json   |    21 -
 tools/perf/tests/pmu-events.c                 |    17 +-
 273 files changed, 87488 insertions(+), 124409 deletions(-)

-- 
2.39.0.314.g84b9a713c41-goog

[PATCH v1 01/32] perf test pmu-events: Fake PMU metric workaround

[Ian Rogers]

We test metrics with fake events with fake values. The fake values may
yield division by zero and so we count both up and down to try to
avoid this. Unfortunately this isn't sufficient for some metrics and
so don't fail the test for them.

Add the metric name to debug output.

Signed-off-by: Ian Rogers <irogers@google.com>
---
 tools/perf/tests/pmu-events.c | 17 +++++++++++------
 1 file changed, 11 insertions(+), 6 deletions(-)

diff --git a/tools/perf/tests/pmu-events.c b/tools/perf/tests/pmu-events.c
index f7b9dbbad97f..a29dd6af8d33 100644
--- a/tools/perf/tests/pmu-events.c
+++ b/tools/perf/tests/pmu-events.c
@@ -959,7 +959,7 @@ static struct test_metric metrics[] = {
 	{ "(imx8_ddr0@read\\-cycles@ + imx8_ddr0@write\\-cycles@)", },
 };
 
-static int metric_parse_fake(const char *str)
+static int metric_parse_fake(const char *metric_name, const char *str)
 {
 	struct expr_parse_ctx *ctx;
 	struct hashmap_entry *cur;
@@ -968,7 +968,7 @@ static int metric_parse_fake(const char *str)
 	size_t bkt;
 	int i;
 
-	pr_debug("parsing '%s'\n", str);
+	pr_debug("parsing '%s': '%s'\n", metric_name, str);
 
 	ctx = expr__ctx_new();
 	if (!ctx) {
@@ -1006,8 +1006,13 @@ static int metric_parse_fake(const char *str)
 		hashmap__for_each_entry(ctx->ids, cur, bkt)
 			expr__add_id_val(ctx, strdup(cur->key), i--);
 		if (expr__parse(&result, ctx, str)) {
-			pr_err("expr__parse failed\n");
-			ret = -1;
+			pr_err("expr__parse failed for %s\n", metric_name);
+			/* The following have hard to avoid divide by zero. */
+			if (!strcmp(metric_name, "tma_clears_resteers") ||
+			    !strcmp(metric_name, "tma_mispredicts_resteers"))
+				ret = 0;
+			else
+				ret = -1;
 		}
 	}
 
@@ -1023,7 +1028,7 @@ static int test__parsing_fake_callback(const struct pmu_event *pe,
 	if (!pe->metric_expr)
 		return 0;
 
-	return metric_parse_fake(pe->metric_expr);
+	return metric_parse_fake(pe->metric_name, pe->metric_expr);
 }
 
 /*
@@ -1037,7 +1042,7 @@ static int test__parsing_fake(struct test_suite *test __maybe_unused,
 	int err = 0;
 
 	for (size_t i = 0; i < ARRAY_SIZE(metrics); i++) {
-		err = metric_parse_fake(metrics[i].str);
+		err = metric_parse_fake("", metrics[i].str);
 		if (err)
 			return err;
 	}
-- 
2.39.0.314.g84b9a713c41-goog

[PATCH v1 02/32] perf vendor events intel: Refresh alderlake metrics

[Ian Rogers]

Update the alderlake metrics using the new tooling from:
https://github.com/intel/perfmon
The metrics are unchanged but the formulas differ due to parentheses,
use of exponents and removal of redundant operations like "* 1".

Signed-off-by: Ian Rogers <irogers@google.com>
---
 .../arch/x86/alderlake/adl-metrics.json       | 116 +++++++++---------
 1 file changed, 58 insertions(+), 58 deletions(-)

diff --git a/tools/perf/pmu-events/arch/x86/alderlake/adl-metrics.json b/tools/perf/pmu-events/arch/x86/alderlake/adl-metrics.json
index edf440e9359a..2eb3d7464d9f 100644
--- a/tools/perf/pmu-events/arch/x86/alderlake/adl-metrics.json
+++ b/tools/perf/pmu-events/arch/x86/alderlake/adl-metrics.json
@@ -10,7 +10,7 @@
     },
     {
         "BriefDescription": "This metric represents fraction of slots the CPU was stalled due to Frontend latency issues",
-        "MetricExpr": "(topdown\\-fetch\\-lat / (topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound) - INT_MISC.UOP_DROPPING / SLOTS)",
+        "MetricExpr": "topdown\\-fetch\\-lat / (topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound) - INT_MISC.UOP_DROPPING / SLOTS",
         "MetricGroup": "Frontend;TopdownL2;tma_L2_group;tma_frontend_bound_group",
         "MetricName": "tma_fetch_latency",
         "PublicDescription": "This metric represents fraction of slots the CPU was stalled due to Frontend latency issues.  For example; instruction-cache misses; iTLB misses or fetch stalls after a branch misprediction are categorized under Frontend Latency. In such cases; the Frontend eventually delivers no uops for some period. Sample with: FRONTEND_RETIRED.LATENCY_GE_16_PS;FRONTEND_RETIRED.LATENCY_GE_8_PS",
@@ -46,7 +46,7 @@
     },
     {
         "BriefDescription": "This metric represents fraction of cycles the CPU was stalled due to Branch Resteers as a result of Branch Misprediction at execution stage",
-        "MetricExpr": "(tma_branch_mispredicts / tma_bad_speculation) * INT_MISC.CLEAR_RESTEER_CYCLES / CLKS",
+        "MetricExpr": "tma_branch_mispredicts / tma_bad_speculation * INT_MISC.CLEAR_RESTEER_CYCLES / CLKS",
         "MetricGroup": "BadSpec;BrMispredicts;TopdownL4;tma_branch_resteers_group",
         "MetricName": "tma_mispredicts_resteers",
         "PublicDescription": "This metric represents fraction of cycles the CPU was stalled due to Branch Resteers as a result of Branch Misprediction at execution stage.  Sample with: INT_MISC.CLEAR_RESTEER_CYCLES",
@@ -55,7 +55,7 @@
     },
     {
         "BriefDescription": "This metric represents fraction of cycles the CPU was stalled due to Branch Resteers as a result of Machine Clears",
-        "MetricExpr": "(1 - (tma_branch_mispredicts / tma_bad_speculation)) * INT_MISC.CLEAR_RESTEER_CYCLES / CLKS",
+        "MetricExpr": "(1 - tma_branch_mispredicts / tma_bad_speculation) * INT_MISC.CLEAR_RESTEER_CYCLES / CLKS",
         "MetricGroup": "BadSpec;MachineClears;TopdownL4;tma_branch_resteers_group",
         "MetricName": "tma_clears_resteers",
         "PublicDescription": "This metric represents fraction of cycles the CPU was stalled due to Branch Resteers as a result of Machine Clears.  Sample with: INT_MISC.CLEAR_RESTEER_CYCLES",
@@ -153,7 +153,7 @@
     },
     {
         "BriefDescription": "This metric represents fraction of slots the CPU has wasted due to Branch Misprediction",
-        "MetricExpr": "topdown\\-br\\-mispredict / (topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound) + 0*SLOTS",
+        "MetricExpr": "topdown\\-br\\-mispredict / (topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound) + 0 * SLOTS",
         "MetricGroup": "BadSpec;BrMispredicts;TopdownL2;tma_L2_group;tma_bad_speculation_group",
         "MetricName": "tma_branch_mispredicts",
         "PublicDescription": "This metric represents fraction of slots the CPU has wasted due to Branch Misprediction.  These slots are either wasted by uops fetched from an incorrectly speculated program path; or stalls when the out-of-order part of the machine needs to recover its state from a speculative path. Sample with: TOPDOWN.BR_MISPREDICT_SLOTS",
@@ -171,7 +171,7 @@
     },
     {
         "BriefDescription": "This category represents fraction of slots where no uops are being delivered due to a lack of required resources for accepting new uops in the Backend",
-        "MetricExpr": "topdown\\-be\\-bound / (topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound) + 0*SLOTS",
+        "MetricExpr": "topdown\\-be\\-bound / (topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound) + 0 * SLOTS",
         "MetricGroup": "TopdownL1;tma_L1_group",
         "MetricName": "tma_backend_bound",
         "PublicDescription": "This category represents fraction of slots where no uops are being delivered due to a lack of required resources for accepting new uops in the Backend. Backend is the portion of the processor core where the out-of-order scheduler dispatches ready uops into their respective execution units; and once completed these uops get retired according to program order. For example; stalls due to data-cache misses or stalls due to the divider unit being overloaded are both categorized under Backend Bound. Backend Bound is further divided into two main categories: Memory Bound and Core Bound. Sample with: TOPDOWN.BACKEND_BOUND_SLOTS",
@@ -180,7 +180,7 @@
     },
     {
         "BriefDescription": "This metric represents fraction of slots the Memory subsystem within the Backend was a bottleneck",
-        "MetricExpr": "topdown\\-mem\\-bound / (topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound) + 0*SLOTS",
+        "MetricExpr": "topdown\\-mem\\-bound / (topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound) + 0 * SLOTS",
         "MetricGroup": "Backend;TopdownL2;tma_L2_group;tma_backend_bound_group",
         "MetricName": "tma_memory_bound",
         "PublicDescription": "This metric represents fraction of slots the Memory subsystem within the Backend was a bottleneck.  Memory Bound estimates fraction of slots where pipeline is likely stalled due to demand load or store instructions. This accounts mainly for (1) non-completed in-flight memory demand loads which coincides with execution units starvation; in addition to (2) cases where stores could impose backpressure on the pipeline when many of them get buffered at the same time (less common out of the two).",
@@ -232,7 +232,7 @@
     },
     {
         "BriefDescription": "This metric represents fraction of cycles the CPU spent handling cache misses due to lock operations",
-        "MetricExpr": "(16 * max(0, MEM_INST_RETIRED.LOCK_LOADS - L2_RQSTS.ALL_RFO) + (MEM_INST_RETIRED.LOCK_LOADS / MEM_INST_RETIRED.ALL_STORES) * (10 * L2_RQSTS.RFO_HIT + min(CPU_CLK_UNHALTED.THREAD, OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_RFO))) / CLKS",
+        "MetricExpr": "(16 * max(0, MEM_INST_RETIRED.LOCK_LOADS - L2_RQSTS.ALL_RFO) + MEM_INST_RETIRED.LOCK_LOADS / MEM_INST_RETIRED.ALL_STORES * (10 * L2_RQSTS.RFO_HIT + min(CPU_CLK_UNHALTED.THREAD, OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_RFO))) / CLKS",
         "MetricGroup": "Offcore;TopdownL4;tma_l1_bound_group",
         "MetricName": "tma_lock_latency",
         "PublicDescription": "This metric represents fraction of cycles the CPU spent handling cache misses due to lock operations. Due to the microarchitecture handling of locks; they are classified as L1_Bound regardless of what memory source satisfied them. Sample with: MEM_INST_RETIRED.LOCK_LOADS_PS",
@@ -277,7 +277,7 @@
     },
     {
         "BriefDescription": "This metric estimates fraction of cycles while the memory subsystem was handling synchronizations due to contested accesses",
-        "MetricExpr": "((25 * Average_Frequency) * (MEM_LOAD_L3_HIT_RETIRED.XSNP_FWD * (OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HITM / (OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HITM + OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD))) + (24 * Average_Frequency) * MEM_LOAD_L3_HIT_RETIRED.XSNP_MISS) * (1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) / 2) / CLKS",
+        "MetricExpr": "(25 * Average_Frequency * (MEM_LOAD_L3_HIT_RETIRED.XSNP_FWD * (OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HITM / (OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HITM + OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD))) + 24 * Average_Frequency * MEM_LOAD_L3_HIT_RETIRED.XSNP_MISS) * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS / 2) / CLKS",
         "MetricGroup": "DataSharing;Offcore;Snoop;TopdownL4;tma_l3_bound_group",
         "MetricName": "tma_contested_accesses",
         "PublicDescription": "This metric estimates fraction of cycles while the memory subsystem was handling synchronizations due to contested accesses. Contested accesses occur when data written by one Logical Processor are read by another Logical Processor on a different Physical Core. Examples of contested accesses include synchronizations such as locks; true data sharing such as modified locked variables; and false sharing. Sample with: MEM_LOAD_L3_HIT_RETIRED.XSNP_FWD;MEM_LOAD_L3_HIT_RETIRED.XSNP_MISS",
@@ -286,7 +286,7 @@
     },
     {
         "BriefDescription": "This metric estimates fraction of cycles while the memory subsystem was handling synchronizations due to data-sharing accesses",
-        "MetricExpr": "(24 * Average_Frequency) * (MEM_LOAD_L3_HIT_RETIRED.XSNP_NO_FWD + MEM_LOAD_L3_HIT_RETIRED.XSNP_FWD * (1 - (OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HITM / (OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HITM + OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD)))) * (1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) / 2) / CLKS",
+        "MetricExpr": "24 * Average_Frequency * (MEM_LOAD_L3_HIT_RETIRED.XSNP_NO_FWD + MEM_LOAD_L3_HIT_RETIRED.XSNP_FWD * (1 - OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HITM / (OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HITM + OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD))) * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS / 2) / CLKS",
         "MetricGroup": "Offcore;Snoop;TopdownL4;tma_l3_bound_group",
         "MetricName": "tma_data_sharing",
         "PublicDescription": "This metric estimates fraction of cycles while the memory subsystem was handling synchronizations due to data-sharing accesses. Data shared by multiple Logical Processors (even just read shared) may cause increased access latency due to cache coherency. Excessive data sharing can drastically harm multithreaded performance. Sample with: MEM_LOAD_L3_HIT_RETIRED.XSNP_NO_FWD",
@@ -295,7 +295,7 @@
     },
     {
         "BriefDescription": "This metric represents fraction of cycles with demand load accesses that hit the L3 cache under unloaded scenarios (possibly L3 latency limited)",
-        "MetricExpr": "(9 * Average_Frequency) * MEM_LOAD_RETIRED.L3_HIT * (1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) / 2) / CLKS",
+        "MetricExpr": "9 * Average_Frequency * MEM_LOAD_RETIRED.L3_HIT * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS / 2) / CLKS",
         "MetricGroup": "MemoryLat;TopdownL4;tma_l3_bound_group",
         "MetricName": "tma_l3_hit_latency",
         "PublicDescription": "This metric represents fraction of cycles with demand load accesses that hit the L3 cache under unloaded scenarios (possibly L3 latency limited).  Avoiding private cache misses (i.e. L2 misses/L3 hits) will improve the latency; reduce contention with sibling physical cores and increase performance.  Note the value of this node may overlap with its siblings. Sample with: MEM_LOAD_RETIRED.L3_HIT_PS",
@@ -313,7 +313,7 @@
     },
     {
         "BriefDescription": "This metric estimates how often the CPU was stalled on accesses to external memory (DRAM) by loads",
-        "MetricExpr": "(MEMORY_ACTIVITY.STALLS_L3_MISS / CLKS)",
+        "MetricExpr": "MEMORY_ACTIVITY.STALLS_L3_MISS / CLKS",
         "MetricGroup": "MemoryBound;TmaL3mem;TopdownL3;tma_memory_bound_group",
         "MetricName": "tma_dram_bound",
         "PublicDescription": "This metric estimates how often the CPU was stalled on accesses to external memory (DRAM) by loads. Better caching can improve the latency and increase performance. Sample with: MEM_LOAD_RETIRED.L3_MISS_PS",
@@ -340,7 +340,7 @@
     },
     {
         "BriefDescription": "This metric estimates how often CPU was stalled  due to RFO store memory accesses; RFO store issue a read-for-ownership request before the write",
-        "MetricExpr": "EXE_ACTIVITY.BOUND_ON_STORES / CLKS",
+        "MetricExpr": "tma_st_buffer",
         "MetricGroup": "MemoryBound;TmaL3mem;TopdownL3;tma_memory_bound_group",
         "MetricName": "tma_store_bound",
         "PublicDescription": "This metric estimates how often CPU was stalled  due to RFO store memory accesses; RFO store issue a read-for-ownership request before the write. Even though store accesses do not typically stall out-of-order CPUs; there are few cases where stores can lead to actual stalls. This metric will be flagged should RFO stores be a bottleneck. Sample with: MEM_INST_RETIRED.ALL_STORES_PS",
@@ -349,7 +349,7 @@
     },
     {
         "BriefDescription": "This metric estimates fraction of cycles the CPU spent handling L1D store misses",
-        "MetricExpr": "((MEM_STORE_RETIRED.L2_HIT * 10 * (1 - (MEM_INST_RETIRED.LOCK_LOADS / MEM_INST_RETIRED.ALL_STORES))) + (1 - (MEM_INST_RETIRED.LOCK_LOADS / MEM_INST_RETIRED.ALL_STORES)) * min(CPU_CLK_UNHALTED.THREAD, OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_RFO)) / CLKS",
+        "MetricExpr": "(MEM_STORE_RETIRED.L2_HIT * 10 * (1 - MEM_INST_RETIRED.LOCK_LOADS / MEM_INST_RETIRED.ALL_STORES) + (1 - MEM_INST_RETIRED.LOCK_LOADS / MEM_INST_RETIRED.ALL_STORES) * min(CPU_CLK_UNHALTED.THREAD, OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_RFO)) / CLKS",
         "MetricGroup": "MemoryLat;Offcore;TopdownL4;tma_store_bound_group",
         "MetricName": "tma_store_latency",
         "PublicDescription": "This metric estimates fraction of cycles the CPU spent handling L1D store misses. Store accesses usually less impact out-of-order core performance; however; holding resources for longer time can lead into undesired implications (e.g. contention on L1D fill-buffer entries - see FB_Full)",
@@ -358,7 +358,7 @@
     },
     {
         "BriefDescription": "This metric roughly estimates how often CPU was handling synchronizations due to False Sharing",
-        "MetricExpr": "(28 * Average_Frequency) * OCR.DEMAND_RFO.L3_HIT.SNOOP_HITM / CLKS",
+        "MetricExpr": "28 * Average_Frequency * OCR.DEMAND_RFO.L3_HIT.SNOOP_HITM / CLKS",
         "MetricGroup": "DataSharing;Offcore;Snoop;TopdownL4;tma_store_bound_group",
         "MetricName": "tma_false_sharing",
         "PublicDescription": "This metric roughly estimates how often CPU was handling synchronizations due to False Sharing. False Sharing is a multithreading hiccup; where multiple Logical Processors contend on different data-elements mapped into the same cache line.  Sample with: OCR.DEMAND_RFO.L3_HIT.SNOOP_HITM",
@@ -428,7 +428,7 @@
     },
     {
         "BriefDescription": "This metric estimates fraction of cycles the CPU performance was potentially limited due to Core computation issues (non divider-related)",
-        "MetricExpr": "(cpu_core@EXE_ACTIVITY.3_PORTS_UTIL\\,umask\\=0x80@ + (EXE_ACTIVITY.1_PORTS_UTIL + tma_retiring * cpu_core@EXE_ACTIVITY.2_PORTS_UTIL\\,umask\\=0xc@)) / CLKS if (ARITH.DIVIDER_ACTIVE < (CYCLE_ACTIVITY.STALLS_TOTAL - EXE_ACTIVITY.BOUND_ON_LOADS)) else (EXE_ACTIVITY.1_PORTS_UTIL + tma_retiring * cpu_core@EXE_ACTIVITY.2_PORTS_UTIL\\,umask\\=0xc@) / CLKS",
+        "MetricExpr": "((cpu_core@EXE_ACTIVITY.3_PORTS_UTIL\\,umask\\=0x80@ + (EXE_ACTIVITY.1_PORTS_UTIL + tma_retiring * cpu_core@EXE_ACTIVITY.2_PORTS_UTIL\\,umask\\=0xc@)) / CLKS if ARITH.DIVIDER_ACTIVE < CYCLE_ACTIVITY.STALLS_TOTAL - EXE_ACTIVITY.BOUND_ON_LOADS else (EXE_ACTIVITY.1_PORTS_UTIL + tma_retiring * cpu_core@EXE_ACTIVITY.2_PORTS_UTIL\\,umask\\=0xc@) / CLKS)",
         "MetricGroup": "PortsUtil;TopdownL3;tma_core_bound_group",
         "MetricName": "tma_ports_utilization",
         "PublicDescription": "This metric estimates fraction of cycles the CPU performance was potentially limited due to Core computation issues (non divider-related).  Two distinct categories can be attributed into this metric: (1) heavy data-dependency among contiguous instructions would manifest in this metric - such cases are often referred to as low Instruction Level Parallelism (ILP). (2) Contention on some hardware execution unit other than Divider. For example; when there are too many multiply operations.",
@@ -556,7 +556,7 @@
     },
     {
         "BriefDescription": "This category represents fraction of slots utilized by useful work i.e. issued uops that eventually get retired",
-        "MetricExpr": "topdown\\-retiring / (topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound) + 0*SLOTS",
+        "MetricExpr": "topdown\\-retiring / (topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound) + 0 * SLOTS",
         "MetricGroup": "TopdownL1;tma_L1_group",
         "MetricName": "tma_retiring",
         "PublicDescription": "This category represents fraction of slots utilized by useful work i.e. issued uops that eventually get retired. Ideally; all pipeline slots would be attributed to the Retiring category.  Retiring of 100% would indicate the maximum Pipeline_Width throughput was achieved.  Maximizing Retiring typically increases the Instructions-per-cycle (see IPC metric). Note that a high Retiring value does not necessary mean there is no room for more performance.  For example; Heavy-operations or Microcode Assists are categorized under Retiring. They often indicate suboptimal performance and can often be optimized or avoided.  Sample with: UOPS_RETIRED.SLOTS",
@@ -704,7 +704,7 @@
     },
     {
         "BriefDescription": "This metric represents fraction of slots where the CPU was retiring heavy-weight operations -- instructions that require two or more uops or microcoded sequences",
-        "MetricExpr": "topdown\\-heavy\\-ops / (topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound) + 0*SLOTS",
+        "MetricExpr": "topdown\\-heavy\\-ops / (topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound) + 0 * SLOTS",
         "MetricGroup": "Retire;TopdownL2;tma_L2_group;tma_retiring_group",
         "MetricName": "tma_heavy_operations",
         "PublicDescription": "This metric represents fraction of slots where the CPU was retiring heavy-weight operations -- instructions that require two or more uops or microcoded sequences. This highly-correlates with the uop length of these instructions/sequences. Sample with: UOPS_RETIRED.HEAVY",
@@ -722,7 +722,7 @@
     },
     {
         "BriefDescription": "This metric represents fraction of slots the CPU was retiring uops fetched by the Microcode Sequencer (MS) unit",
-        "MetricExpr": "UOPS_RETIRED.MS / SLOTS",
+        "MetricExpr": "tma_ms_uops",
         "MetricGroup": "MicroSeq;TopdownL3;tma_heavy_operations_group",
         "MetricName": "tma_microcode_sequencer",
         "PublicDescription": "This metric represents fraction of slots the CPU was retiring uops fetched by the Microcode Sequencer (MS) unit.  The MS is used for CISC instructions not supported by the default decoders (like repeat move strings; or CPUID); or by microcode assists used to address some operation modes (like in Floating Point assists). These cases can often be avoided. Sample with: UOPS_RETIRED.MS",
@@ -782,21 +782,21 @@
     },
     {
         "BriefDescription": "Total pipeline cost of (external) Memory Bandwidth related bottlenecks",
-        "MetricExpr": "100 * tma_memory_bound * ((tma_dram_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_store_bound)) * (tma_mem_bandwidth / (tma_mem_bandwidth + tma_mem_latency)) + (tma_l3_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_store_bound)) * (tma_sq_full / (tma_contested_accesses + tma_data_sharing + tma_l3_hit_latency + tma_sq_full))) + (tma_l1_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_store_bound)) * (tma_fb_full / (tma_dtlb_load + tma_fb_full + tma_lock_latency + tma_split_loads + tma_store_fwd_blk)) ",
+        "MetricExpr": "100 * tma_memory_bound * (tma_dram_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_store_bound) * (tma_mem_bandwidth / (tma_mem_bandwidth + tma_mem_latency)) + tma_l3_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_store_bound) * (tma_sq_full / (tma_contested_accesses + tma_data_sharing + tma_l3_hit_latency + tma_sq_full))) + tma_l1_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_store_bound) * (tma_fb_full / (tma_dtlb_load + tma_fb_full + tma_lock_latency + tma_split_loads + tma_store_fwd_blk))",
         "MetricGroup": "Mem;MemoryBW;Offcore",
         "MetricName": "Memory_Bandwidth",
         "Unit": "cpu_core"
     },
     {
         "BriefDescription": "Total pipeline cost of Memory Latency related bottlenecks (external memory and off-core caches)",
-        "MetricExpr": "100 * tma_memory_bound * ((tma_dram_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_store_bound)) * (tma_mem_latency / (tma_mem_bandwidth + tma_mem_latency)) + (tma_l3_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_store_bound)) * (tma_l3_hit_latency / (tma_contested_accesses + tma_data_sharing + tma_l3_hit_latency + tma_sq_full)) + (tma_l2_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_store_bound)))",
+        "MetricExpr": "100 * tma_memory_bound * (tma_dram_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_store_bound) * (tma_mem_latency / (tma_mem_bandwidth + tma_mem_latency)) + tma_l3_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_store_bound) * (tma_l3_hit_latency / (tma_contested_accesses + tma_data_sharing + tma_l3_hit_latency + tma_sq_full)) + tma_l2_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_store_bound))",
         "MetricGroup": "Mem;MemoryLat;Offcore",
         "MetricName": "Memory_Latency",
         "Unit": "cpu_core"
     },
     {
         "BriefDescription": "Total pipeline cost of Memory Address Translation related bottlenecks (data-side TLBs)",
-        "MetricExpr": "100 * tma_memory_bound * ((tma_l1_bound / max(tma_memory_bound, tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_store_bound)) * (tma_dtlb_load / max(tma_l1_bound, tma_dtlb_load + tma_fb_full + tma_lock_latency + tma_split_loads + tma_store_fwd_blk)) + (tma_store_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_store_bound)) * (tma_dtlb_store / (tma_dtlb_store + tma_false_sharing + tma_split_stores + tma_store_latency + tma_streaming_stores))) ",
+        "MetricExpr": "100 * tma_memory_bound * (tma_l1_bound / max(tma_memory_bound, tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_store_bound) * (tma_dtlb_load / max(tma_l1_bound, tma_dtlb_load + tma_fb_full + tma_lock_latency + tma_split_loads + tma_store_fwd_blk)) + tma_store_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_store_bound) * (tma_dtlb_store / (tma_dtlb_store + tma_false_sharing + tma_split_stores + tma_store_latency + tma_streaming_stores)))",
         "MetricGroup": "Mem;MemoryTLB;Offcore",
         "MetricName": "Memory_Data_TLBs",
         "Unit": "cpu_core"
@@ -831,14 +831,14 @@
     },
     {
         "BriefDescription": "Uops Per Instruction",
-        "MetricExpr": "(tma_retiring * SLOTS) / INST_RETIRED.ANY",
+        "MetricExpr": "tma_retiring * SLOTS / INST_RETIRED.ANY",
         "MetricGroup": "Pipeline;Ret;Retire",
         "MetricName": "UPI",
         "Unit": "cpu_core"
     },
     {
         "BriefDescription": "Instruction per taken branch",
-        "MetricExpr": "(tma_retiring * SLOTS) / BR_INST_RETIRED.NEAR_TAKEN",
+        "MetricExpr": "tma_retiring * SLOTS / BR_INST_RETIRED.NEAR_TAKEN",
         "MetricGroup": "Branches;Fed;FetchBW",
         "MetricName": "UpTB",
         "Unit": "cpu_core"
@@ -866,7 +866,7 @@
     },
     {
         "BriefDescription": "Fraction of Physical Core issue-slots utilized by this Logical Processor",
-        "MetricExpr": "SLOTS / (TOPDOWN.SLOTS / 2) if #SMT_on else 1",
+        "MetricExpr": "(SLOTS / (TOPDOWN.SLOTS / 2) if #SMT_on else 1)",
         "MetricGroup": "SMT;tma_L1_group",
         "MetricName": "Slots_Utilization",
         "Unit": "cpu_core"
@@ -888,7 +888,7 @@
     },
     {
         "BriefDescription": "Floating Point Operations Per Cycle",
-        "MetricExpr": "(1 * (FP_ARITH_INST_RETIRED.SCALAR_SINGLE + FP_ARITH_INST_RETIRED.SCALAR_DOUBLE) + 2 * FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + 4 * (FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE) + 8 * FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE) / CORE_CLKS",
+        "MetricExpr": "(FP_ARITH_INST_RETIRED.SCALAR_SINGLE + FP_ARITH_INST_RETIRED.SCALAR_DOUBLE + 2 * FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + 4 * (FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE) + 8 * FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE) / CORE_CLKS",
         "MetricGroup": "Flops;Ret",
         "MetricName": "FLOPc",
         "Unit": "cpu_core"
@@ -903,14 +903,14 @@
     },
     {
         "BriefDescription": "Instruction-Level-Parallelism (average number of uops executed when there is execution) per-core",
-        "MetricExpr": "UOPS_EXECUTED.THREAD / ((UOPS_EXECUTED.CORE_CYCLES_GE_1 / 2) if #SMT_on else UOPS_EXECUTED.CORE_CYCLES_GE_1)",
+        "MetricExpr": "UOPS_EXECUTED.THREAD / (UOPS_EXECUTED.CORE_CYCLES_GE_1 / 2 if #SMT_on else UOPS_EXECUTED.CORE_CYCLES_GE_1)",
         "MetricGroup": "Backend;Cor;Pipeline;PortsUtil",
         "MetricName": "ILP",
         "Unit": "cpu_core"
     },
     {
         "BriefDescription": "Probability of Core Bound bottleneck hidden by SMT-profiling artifacts",
-        "MetricExpr": "(1 - tma_core_bound / tma_ports_utilization if tma_core_bound < tma_ports_utilization else 1) if SMT_2T_Utilization > 0.5 else 0",
+        "MetricExpr": "((1 - tma_core_bound / tma_ports_utilization if tma_core_bound < tma_ports_utilization else 1) if SMT_2T_Utilization > 0.5 else 0)",
         "MetricGroup": "Cor;SMT",
         "MetricName": "Core_Bound_Likely",
         "Unit": "cpu_core"
@@ -966,14 +966,14 @@
     },
     {
         "BriefDescription": "Instructions per Floating Point (FP) Operation (lower number means higher occurrence rate)",
-        "MetricExpr": "INST_RETIRED.ANY / (1 * (FP_ARITH_INST_RETIRED.SCALAR_SINGLE + FP_ARITH_INST_RETIRED.SCALAR_DOUBLE) + 2 * FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + 4 * (FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE) + 8 * FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE)",
+        "MetricExpr": "INST_RETIRED.ANY / (FP_ARITH_INST_RETIRED.SCALAR_SINGLE + FP_ARITH_INST_RETIRED.SCALAR_DOUBLE + 2 * FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + 4 * (FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE) + 8 * FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE)",
         "MetricGroup": "Flops;InsType",
         "MetricName": "IpFLOP",
         "Unit": "cpu_core"
     },
     {
         "BriefDescription": "Instructions per FP Arithmetic instruction (lower number means higher occurrence rate)",
-        "MetricExpr": "INST_RETIRED.ANY / ((FP_ARITH_INST_RETIRED.SCALAR_SINGLE + FP_ARITH_INST_RETIRED.SCALAR_DOUBLE) + (FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE))",
+        "MetricExpr": "INST_RETIRED.ANY / (FP_ARITH_INST_RETIRED.SCALAR_SINGLE + FP_ARITH_INST_RETIRED.SCALAR_DOUBLE + (FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE))",
         "MetricGroup": "Flops;InsType",
         "MetricName": "IpArith",
         "PublicDescription": "Instructions per FP Arithmetic instruction (lower number means higher occurrence rate). May undercount due to FMA double counting. Approximated prior to BDW.",
@@ -1027,7 +1027,7 @@
     },
     {
         "BriefDescription": "Average number of Uops retired in cycles where at least one uop has retired.",
-        "MetricExpr": "(tma_retiring * SLOTS) / cpu_core@UOPS_RETIRED.SLOTS\\,cmask\\=1@",
+        "MetricExpr": "tma_retiring * SLOTS / cpu_core@UOPS_RETIRED.SLOTS\\,cmask\\=1@",
         "MetricGroup": "Pipeline;Ret",
         "MetricName": "Retire",
         "Unit": "cpu_core"
@@ -1104,7 +1104,7 @@
     },
     {
         "BriefDescription": "Branch Misprediction Cost: Fraction of TMA slots wasted per non-speculative branch misprediction (retired JEClear)",
-        "MetricExpr": " (tma_branch_mispredicts + tma_fetch_latency * tma_mispredicts_resteers / (tma_branch_resteers + tma_dsb_switches + tma_icache_misses + tma_itlb_misses + tma_lcp + tma_ms_switches)) * SLOTS / BR_MISP_RETIRED.ALL_BRANCHES",
+        "MetricExpr": "(tma_branch_mispredicts + tma_fetch_latency * tma_mispredicts_resteers / (tma_branch_resteers + tma_dsb_switches + tma_icache_misses + tma_itlb_misses + tma_lcp + tma_ms_switches)) * SLOTS / BR_MISP_RETIRED.ALL_BRANCHES",
         "MetricGroup": "Bad;BrMispredicts",
         "MetricName": "Branch_Misprediction_Cost",
         "Unit": "cpu_core"
@@ -1160,63 +1160,63 @@
     },
     {
         "BriefDescription": "L1 cache true misses per kilo instruction for retired demand loads",
-        "MetricExpr": "1000 * MEM_LOAD_RETIRED.L1_MISS / INST_RETIRED.ANY",
+        "MetricExpr": "1e3 * MEM_LOAD_RETIRED.L1_MISS / INST_RETIRED.ANY",
         "MetricGroup": "CacheMisses;Mem",
         "MetricName": "L1MPKI",
         "Unit": "cpu_core"
     },
     {
         "BriefDescription": "L1 cache true misses per kilo instruction for all demand loads (including speculative)",
-        "MetricExpr": "1000 * L2_RQSTS.ALL_DEMAND_DATA_RD / INST_RETIRED.ANY",
+        "MetricExpr": "1e3 * L2_RQSTS.ALL_DEMAND_DATA_RD / INST_RETIRED.ANY",
         "MetricGroup": "CacheMisses;Mem",
         "MetricName": "L1MPKI_Load",
         "Unit": "cpu_core"
     },
     {
         "BriefDescription": "L2 cache true misses per kilo instruction for retired demand loads",
-        "MetricExpr": "1000 * MEM_LOAD_RETIRED.L2_MISS / INST_RETIRED.ANY",
+        "MetricExpr": "1e3 * MEM_LOAD_RETIRED.L2_MISS / INST_RETIRED.ANY",
         "MetricGroup": "Backend;CacheMisses;Mem",
         "MetricName": "L2MPKI",
         "Unit": "cpu_core"
     },
     {
         "BriefDescription": "L2 cache ([RKL+] true) misses per kilo instruction for all request types (including speculative)",
-        "MetricExpr": "1000 * L2_RQSTS.MISS / INST_RETIRED.ANY",
+        "MetricExpr": "1e3 * L2_RQSTS.MISS / INST_RETIRED.ANY",
         "MetricGroup": "CacheMisses;Mem;Offcore",
         "MetricName": "L2MPKI_All",
         "Unit": "cpu_core"
     },
     {
         "BriefDescription": "L2 cache ([RKL+] true) misses per kilo instruction for all demand loads  (including speculative)",
-        "MetricExpr": "1000 * L2_RQSTS.DEMAND_DATA_RD_MISS / INST_RETIRED.ANY",
+        "MetricExpr": "1e3 * L2_RQSTS.DEMAND_DATA_RD_MISS / INST_RETIRED.ANY",
         "MetricGroup": "CacheMisses;Mem",
         "MetricName": "L2MPKI_Load",
         "Unit": "cpu_core"
     },
     {
         "BriefDescription": "L2 cache hits per kilo instruction for all request types (including speculative)",
-        "MetricExpr": "1000 * (L2_RQSTS.REFERENCES - L2_RQSTS.MISS) / INST_RETIRED.ANY",
+        "MetricExpr": "1e3 * (L2_RQSTS.REFERENCES - L2_RQSTS.MISS) / INST_RETIRED.ANY",
         "MetricGroup": "CacheMisses;Mem",
         "MetricName": "L2HPKI_All",
         "Unit": "cpu_core"
     },
     {
         "BriefDescription": "L2 cache hits per kilo instruction for all demand loads  (including speculative)",
-        "MetricExpr": "1000 * L2_RQSTS.DEMAND_DATA_RD_HIT / INST_RETIRED.ANY",
+        "MetricExpr": "1e3 * L2_RQSTS.DEMAND_DATA_RD_HIT / INST_RETIRED.ANY",
         "MetricGroup": "CacheMisses;Mem",
         "MetricName": "L2HPKI_Load",
         "Unit": "cpu_core"
     },
     {
         "BriefDescription": "L3 cache true misses per kilo instruction for retired demand loads",
-        "MetricExpr": "1000 * MEM_LOAD_RETIRED.L3_MISS / INST_RETIRED.ANY",
+        "MetricExpr": "1e3 * MEM_LOAD_RETIRED.L3_MISS / INST_RETIRED.ANY",
         "MetricGroup": "CacheMisses;Mem",
         "MetricName": "L3MPKI",
         "Unit": "cpu_core"
     },
     {
         "BriefDescription": "Fill Buffer (FB) hits per kilo instructions for retired demand loads (L1D misses that merge into ongoing miss-handling entries)",
-        "MetricExpr": "1000 * MEM_LOAD_RETIRED.FB_HIT / INST_RETIRED.ANY",
+        "MetricExpr": "1e3 * MEM_LOAD_RETIRED.FB_HIT / INST_RETIRED.ANY",
         "MetricGroup": "CacheMisses;Mem",
         "MetricName": "FB_HPKI",
         "Unit": "cpu_core"
@@ -1231,28 +1231,28 @@
     },
     {
         "BriefDescription": "Average per-core data fill bandwidth to the L1 data cache [GB / sec]",
-        "MetricExpr": "64 * L1D.REPLACEMENT / 1000000000 / duration_time",
+        "MetricExpr": "64 * L1D.REPLACEMENT / 1e9 / duration_time",
         "MetricGroup": "Mem;MemoryBW",
         "MetricName": "L1D_Cache_Fill_BW",
         "Unit": "cpu_core"
     },
     {
         "BriefDescription": "Average per-core data fill bandwidth to the L2 cache [GB / sec]",
-        "MetricExpr": "64 * L2_LINES_IN.ALL / 1000000000 / duration_time",
+        "MetricExpr": "64 * L2_LINES_IN.ALL / 1e9 / duration_time",
         "MetricGroup": "Mem;MemoryBW",
         "MetricName": "L2_Cache_Fill_BW",
         "Unit": "cpu_core"
     },
     {
         "BriefDescription": "Average per-core data fill bandwidth to the L3 cache [GB / sec]",
-        "MetricExpr": "64 * LONGEST_LAT_CACHE.MISS / 1000000000 / duration_time",
+        "MetricExpr": "64 * LONGEST_LAT_CACHE.MISS / 1e9 / duration_time",
         "MetricGroup": "Mem;MemoryBW",
         "MetricName": "L3_Cache_Fill_BW",
         "Unit": "cpu_core"
     },
     {
         "BriefDescription": "Average per-core data access bandwidth to the L3 cache [GB / sec]",
-        "MetricExpr": "64 * OFFCORE_REQUESTS.ALL_REQUESTS / 1000000000 / duration_time",
+        "MetricExpr": "64 * OFFCORE_REQUESTS.ALL_REQUESTS / 1e9 / duration_time",
         "MetricGroup": "Mem;MemoryBW;Offcore",
         "MetricName": "L3_Cache_Access_BW",
         "Unit": "cpu_core"
@@ -1294,14 +1294,14 @@
     },
     {
         "BriefDescription": "Measured Average Frequency for unhalted processors [GHz]",
-        "MetricExpr": "Turbo_Utilization * TSC / 1000000000 / duration_time",
+        "MetricExpr": "Turbo_Utilization * TSC / 1e9 / duration_time",
         "MetricGroup": "Power;Summary",
         "MetricName": "Average_Frequency",
         "Unit": "cpu_core"
     },
     {
         "BriefDescription": "Giga Floating Point Operations Per Second",
-        "MetricExpr": "((1 * (FP_ARITH_INST_RETIRED.SCALAR_SINGLE + FP_ARITH_INST_RETIRED.SCALAR_DOUBLE) + 2 * FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + 4 * (FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE) + 8 * FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE) / 1000000000) / duration_time",
+        "MetricExpr": "(FP_ARITH_INST_RETIRED.SCALAR_SINGLE + FP_ARITH_INST_RETIRED.SCALAR_DOUBLE + 2 * FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + 4 * (FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE) + 8 * FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE) / 1e9 / duration_time",
         "MetricGroup": "Cor;Flops;HPC",
         "MetricName": "GFLOPs",
         "PublicDescription": "Giga Floating Point Operations Per Second. Aggregate across all supported options of: FP precisions, scalar and vector instructions, vector-width and AMX engine.",
@@ -1316,7 +1316,7 @@
     },
     {
         "BriefDescription": "Fraction of cycles where both hardware Logical Processors were active",
-        "MetricExpr": "1 - CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_DISTRIBUTED if #SMT_on else 0",
+        "MetricExpr": "(1 - CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_DISTRIBUTED if #SMT_on else 0)",
         "MetricGroup": "SMT",
         "MetricName": "SMT_2T_Utilization",
         "Unit": "cpu_core"
@@ -1337,7 +1337,7 @@
     },
     {
         "BriefDescription": "Average external Memory Bandwidth Use for reads and writes [GB / sec]",
-        "MetricExpr": "64 * (UNC_ARB_TRK_REQUESTS.ALL + UNC_ARB_COH_TRK_REQUESTS.ALL) / 1000000 / duration_time / 1000",
+        "MetricExpr": "64 * (UNC_ARB_TRK_REQUESTS.ALL + UNC_ARB_COH_TRK_REQUESTS.ALL) / 1e6 / duration_time / 1e3",
         "MetricGroup": "HPC;Mem;MemoryBW;SoC",
         "MetricName": "DRAM_BW_Use",
         "Unit": "cpu_core"
@@ -1365,7 +1365,7 @@
     },
     {
         "BriefDescription": "Uncore frequency per die [GHZ]",
-        "MetricExpr": "Socket_CLKS / #num_dies / duration_time / 1000000000",
+        "MetricExpr": "Socket_CLKS / #num_dies / duration_time / 1e9",
         "MetricGroup": "SoC",
         "MetricName": "UNCORE_FREQ"
     },
@@ -1558,7 +1558,7 @@
     },
     {
         "BriefDescription": "Counts the number of cycles the core is stalled due to stores or loads. ",
-        "MetricExpr": "min((TOPDOWN_BE_BOUND.ALL / SLOTS), (LD_HEAD.ANY_AT_RET / CLKS) + tma_store_bound)",
+        "MetricExpr": "min(tma_backend_bound, LD_HEAD.ANY_AT_RET / CLKS + tma_store_bound)",
         "MetricGroup": "TopdownL2;tma_backend_bound_group",
         "MetricName": "tma_load_store_bound",
         "ScaleUnit": "100%",
@@ -1566,7 +1566,7 @@
     },
     {
         "BriefDescription": "Counts the number of cycles the core is stalled due to store buffer full.",
-        "MetricExpr": "tma_mem_scheduler * (MEM_SCHEDULER_BLOCK.ST_BUF / MEM_SCHEDULER_BLOCK.ALL)",
+        "MetricExpr": "tma_st_buffer",
         "MetricGroup": "TopdownL3;tma_load_store_bound_group",
         "MetricName": "tma_store_bound",
         "ScaleUnit": "100%",
@@ -1614,7 +1614,7 @@
     },
     {
         "BriefDescription": "Counts the number of cycles a core is stalled due to a demand load which hit in the L2 Cache.",
-        "MetricExpr": "(MEM_BOUND_STALLS.LOAD_L2_HIT / CLKS) - (MEM_BOUND_STALLS_AT_RET_CORRECTION * MEM_BOUND_STALLS.LOAD_L2_HIT / MEM_BOUND_STALLS.LOAD)",
+        "MetricExpr": "MEM_BOUND_STALLS.LOAD_L2_HIT / CLKS - MEM_BOUND_STALLS_AT_RET_CORRECTION * MEM_BOUND_STALLS.LOAD_L2_HIT / MEM_BOUND_STALLS.LOAD",
         "MetricGroup": "TopdownL3;tma_load_store_bound_group",
         "MetricName": "tma_l2_bound",
         "ScaleUnit": "100%",
@@ -1622,7 +1622,7 @@
     },
     {
         "BriefDescription": "Counts the number of cycles a core is stalled due to a demand load which hit in the Last Level Cache (LLC) or other core with HITE/F/M.",
-        "MetricExpr": "(MEM_BOUND_STALLS.LOAD_LLC_HIT / CLKS) - (MEM_BOUND_STALLS_AT_RET_CORRECTION * MEM_BOUND_STALLS.LOAD_LLC_HIT / MEM_BOUND_STALLS.LOAD)",
+        "MetricExpr": "MEM_BOUND_STALLS.LOAD_LLC_HIT / CLKS - MEM_BOUND_STALLS_AT_RET_CORRECTION * MEM_BOUND_STALLS.LOAD_LLC_HIT / MEM_BOUND_STALLS.LOAD",
         "MetricGroup": "TopdownL3;tma_load_store_bound_group",
         "MetricName": "tma_l3_bound",
         "ScaleUnit": "100%",
@@ -1630,7 +1630,7 @@
     },
     {
         "BriefDescription": "Counts the number of cycles the core is stalled due to a demand load miss which hit in DRAM or MMIO (Non-DRAM).",
-        "MetricExpr": "(MEM_BOUND_STALLS.LOAD_DRAM_HIT / CLKS) - (MEM_BOUND_STALLS_AT_RET_CORRECTION * MEM_BOUND_STALLS.LOAD_DRAM_HIT / MEM_BOUND_STALLS.LOAD)",
+        "MetricExpr": "MEM_BOUND_STALLS.LOAD_DRAM_HIT / CLKS - MEM_BOUND_STALLS_AT_RET_CORRECTION * MEM_BOUND_STALLS.LOAD_DRAM_HIT / MEM_BOUND_STALLS.LOAD",
         "MetricGroup": "TopdownL3;tma_load_store_bound_group",
         "MetricName": "tma_dram_bound",
         "ScaleUnit": "100%",
@@ -1939,25 +1939,25 @@
     },
     {
         "BriefDescription": "Percent of instruction miss cost that hit in the L2",
-        "MetricExpr": "100 * MEM_BOUND_STALLS.IFETCH_L2_HIT / (MEM_BOUND_STALLS.IFETCH)",
+        "MetricExpr": "100 * MEM_BOUND_STALLS.IFETCH_L2_HIT / MEM_BOUND_STALLS.IFETCH",
         "MetricName": "Inst_Miss_Cost_L2Hit_Percent",
         "Unit": "cpu_atom"
     },
     {
         "BriefDescription": "Percent of instruction miss cost that hit in the L3",
-        "MetricExpr": "100 * MEM_BOUND_STALLS.IFETCH_LLC_HIT / (MEM_BOUND_STALLS.IFETCH)",
+        "MetricExpr": "100 * MEM_BOUND_STALLS.IFETCH_LLC_HIT / MEM_BOUND_STALLS.IFETCH",
         "MetricName": "Inst_Miss_Cost_L3Hit_Percent",
         "Unit": "cpu_atom"
     },
     {
         "BriefDescription": "Percent of instruction miss cost that hit in DRAM",
-        "MetricExpr": "100 * MEM_BOUND_STALLS.IFETCH_DRAM_HIT / (MEM_BOUND_STALLS.IFETCH)",
+        "MetricExpr": "100 * MEM_BOUND_STALLS.IFETCH_DRAM_HIT / MEM_BOUND_STALLS.IFETCH",
         "MetricName": "Inst_Miss_Cost_DRAMHit_Percent",
         "Unit": "cpu_atom"
     },
     {
         "BriefDescription": "load ops retired per 1000 instruction",
-        "MetricExpr": "1000 * MEM_UOPS_RETIRED.ALL_LOADS / INST_RETIRED.ANY",
+        "MetricExpr": "1e3 * MEM_UOPS_RETIRED.ALL_LOADS / INST_RETIRED.ANY",
         "MetricName": "MemLoadPKI",
         "Unit": "cpu_atom"
     },
-- 
2.39.0.314.g84b9a713c41-goog

[PATCH v1 03/32] perf vendor events intel: Refresh alderlake-n metrics

[Ian Rogers]

Update the alderlake-n metrics using the new tooling from:
https://github.com/intel/perfmon
The metrics are unchanged but the formulas differ due to parentheses,
use of exponents and removal of redundant operations like "* 1".

Signed-off-by: Ian Rogers <irogers@google.com>
---
 .../arch/x86/alderlaken/adln-metrics.json     | 22 +++++++++----------
 1 file changed, 11 insertions(+), 11 deletions(-)

diff --git a/tools/perf/pmu-events/arch/x86/alderlaken/adln-metrics.json b/tools/perf/pmu-events/arch/x86/alderlaken/adln-metrics.json
index c57e9f325fb0..9a352a8b6b70 100644
--- a/tools/perf/pmu-events/arch/x86/alderlaken/adln-metrics.json
+++ b/tools/perf/pmu-events/arch/x86/alderlaken/adln-metrics.json
@@ -165,14 +165,14 @@
     },
     {
         "BriefDescription": "Counts the number of cycles the core is stalled due to stores or loads. ",
-        "MetricExpr": "min((TOPDOWN_BE_BOUND.ALL / SLOTS), (LD_HEAD.ANY_AT_RET / CLKS) + tma_store_bound)",
+        "MetricExpr": "min(tma_backend_bound, LD_HEAD.ANY_AT_RET / CLKS + tma_store_bound)",
         "MetricGroup": "TopdownL2;tma_backend_bound_group",
         "MetricName": "tma_load_store_bound",
         "ScaleUnit": "100%"
     },
     {
         "BriefDescription": "Counts the number of cycles the core is stalled due to store buffer full.",
-        "MetricExpr": "tma_mem_scheduler * (MEM_SCHEDULER_BLOCK.ST_BUF / MEM_SCHEDULER_BLOCK.ALL)",
+        "MetricExpr": "tma_st_buffer",
         "MetricGroup": "TopdownL3;tma_load_store_bound_group",
         "MetricName": "tma_store_bound",
         "ScaleUnit": "100%"
@@ -214,21 +214,21 @@
     },
     {
         "BriefDescription": "Counts the number of cycles a core is stalled due to a demand load which hit in the L2 Cache.",
-        "MetricExpr": "(MEM_BOUND_STALLS.LOAD_L2_HIT / CLKS) - (MEM_BOUND_STALLS_AT_RET_CORRECTION * MEM_BOUND_STALLS.LOAD_L2_HIT / MEM_BOUND_STALLS.LOAD)",
+        "MetricExpr": "MEM_BOUND_STALLS.LOAD_L2_HIT / CLKS - MEM_BOUND_STALLS_AT_RET_CORRECTION * MEM_BOUND_STALLS.LOAD_L2_HIT / MEM_BOUND_STALLS.LOAD",
         "MetricGroup": "TopdownL3;tma_load_store_bound_group",
         "MetricName": "tma_l2_bound",
         "ScaleUnit": "100%"
     },
     {
         "BriefDescription": "Counts the number of cycles a core is stalled due to a demand load which hit in the Last Level Cache (LLC) or other core with HITE/F/M.",
-        "MetricExpr": "(MEM_BOUND_STALLS.LOAD_LLC_HIT / CLKS) - (MEM_BOUND_STALLS_AT_RET_CORRECTION * MEM_BOUND_STALLS.LOAD_LLC_HIT / MEM_BOUND_STALLS.LOAD)",
+        "MetricExpr": "MEM_BOUND_STALLS.LOAD_LLC_HIT / CLKS - MEM_BOUND_STALLS_AT_RET_CORRECTION * MEM_BOUND_STALLS.LOAD_LLC_HIT / MEM_BOUND_STALLS.LOAD",
         "MetricGroup": "TopdownL3;tma_load_store_bound_group",
         "MetricName": "tma_l3_bound",
         "ScaleUnit": "100%"
     },
     {
         "BriefDescription": "Counts the number of cycles the core is stalled due to a demand load miss which hit in DRAM or MMIO (Non-DRAM).",
-        "MetricExpr": "(MEM_BOUND_STALLS.LOAD_DRAM_HIT / CLKS) - (MEM_BOUND_STALLS_AT_RET_CORRECTION * MEM_BOUND_STALLS.LOAD_DRAM_HIT / MEM_BOUND_STALLS.LOAD)",
+        "MetricExpr": "MEM_BOUND_STALLS.LOAD_DRAM_HIT / CLKS - MEM_BOUND_STALLS_AT_RET_CORRECTION * MEM_BOUND_STALLS.LOAD_DRAM_HIT / MEM_BOUND_STALLS.LOAD",
         "MetricGroup": "TopdownL3;tma_load_store_bound_group",
         "MetricName": "tma_dram_bound",
         "ScaleUnit": "100%"
@@ -401,12 +401,12 @@
         "MetricName": "Load_Splits"
     },
     {
-        "BriefDescription": "Instructions per Branch (lower number means higher occurrence rate)",
+        "BriefDescription": "Instructions per Branch (lower number means higher occurrence rate)",
         "MetricExpr": "INST_RETIRED.ANY / BR_INST_RETIRED.ALL_BRANCHES",
         "MetricName": "IpBranch"
     },
     {
-        "BriefDescription": "Instruction per (near) call (lower number means higher occurrence rate)",
+        "BriefDescription": "Instruction per (near) call (lower number means higher occurrence rate)",
         "MetricExpr": "INST_RETIRED.ANY / BR_INST_RETIRED.CALL",
         "MetricName": "IpCall"
     },
@@ -492,22 +492,22 @@
     },
     {
         "BriefDescription": "Percent of instruction miss cost that hit in the L2",
-        "MetricExpr": "100 * MEM_BOUND_STALLS.IFETCH_L2_HIT / (MEM_BOUND_STALLS.IFETCH)",
+        "MetricExpr": "100 * MEM_BOUND_STALLS.IFETCH_L2_HIT / MEM_BOUND_STALLS.IFETCH",
         "MetricName": "Inst_Miss_Cost_L2Hit_Percent"
     },
     {
         "BriefDescription": "Percent of instruction miss cost that hit in the L3",
-        "MetricExpr": "100 * MEM_BOUND_STALLS.IFETCH_LLC_HIT / (MEM_BOUND_STALLS.IFETCH)",
+        "MetricExpr": "100 * MEM_BOUND_STALLS.IFETCH_LLC_HIT / MEM_BOUND_STALLS.IFETCH",
         "MetricName": "Inst_Miss_Cost_L3Hit_Percent"
     },
     {
         "BriefDescription": "Percent of instruction miss cost that hit in DRAM",
-        "MetricExpr": "100 * MEM_BOUND_STALLS.IFETCH_DRAM_HIT / (MEM_BOUND_STALLS.IFETCH)",
+        "MetricExpr": "100 * MEM_BOUND_STALLS.IFETCH_DRAM_HIT / MEM_BOUND_STALLS.IFETCH",
         "MetricName": "Inst_Miss_Cost_DRAMHit_Percent"
     },
     {
         "BriefDescription": "load ops retired per 1000 instruction",
-        "MetricExpr": "1000 * MEM_UOPS_RETIRED.ALL_LOADS / INST_RETIRED.ANY",
+        "MetricExpr": "1e3 * MEM_UOPS_RETIRED.ALL_LOADS / INST_RETIRED.ANY",
         "MetricName": "MemLoadPKI"
     },
     {
-- 
2.39.0.314.g84b9a713c41-goog

[PATCH v1 04/32] perf vendor events intel: Refresh bonnell events

[Ian Rogers]

Update the bonnell events using the new tooling from:
https://github.com/intel/perfmon
The events are unchanged but unused json values are removed and
implicit umasks of 0 are dropped. This increases consistency across
the json files.

Signed-off-by: Ian Rogers <irogers@google.com>
---
 .../pmu-events/arch/x86/bonnell/cache.json    | 93 -------------------
 .../arch/x86/bonnell/floating-point.json      | 47 +---------
 .../pmu-events/arch/x86/bonnell/frontend.json | 11 ---
 .../pmu-events/arch/x86/bonnell/memory.json   | 19 ----
 .../pmu-events/arch/x86/bonnell/other.json    | 74 ++-------------
 .../pmu-events/arch/x86/bonnell/pipeline.json | 65 ++-----------
 .../arch/x86/bonnell/virtual-memory.json      | 15 ---
 7 files changed, 18 insertions(+), 306 deletions(-)

diff --git a/tools/perf/pmu-events/arch/x86/bonnell/cache.json b/tools/perf/pmu-events/arch/x86/bonnell/cache.json
index 86582bb8aa39..1ca95a70d48a 100644
--- a/tools/perf/pmu-events/arch/x86/bonnell/cache.json
+++ b/tools/perf/pmu-events/arch/x86/bonnell/cache.json
@@ -1,7 +1,6 @@
 [
     {
         "BriefDescription": "L1 Data Cacheable reads and writes",
-        "Counter": "0,1",
         "EventCode": "0x40",
         "EventName": "L1D_CACHE.ALL_CACHE_REF",
         "SampleAfterValue": "2000000",
@@ -9,7 +8,6 @@
     },
     {
         "BriefDescription": "L1 Data reads and writes",
-        "Counter": "0,1",
         "EventCode": "0x40",
         "EventName": "L1D_CACHE.ALL_REF",
         "SampleAfterValue": "2000000",
@@ -17,7 +15,6 @@
     },
     {
         "BriefDescription": "Modified cache lines evicted from the L1 data cache",
-        "Counter": "0,1",
         "EventCode": "0x40",
         "EventName": "L1D_CACHE.EVICT",
         "SampleAfterValue": "200000",
@@ -25,7 +22,6 @@
     },
     {
         "BriefDescription": "L1 Cacheable Data Reads",
-        "Counter": "0,1",
         "EventCode": "0x40",
         "EventName": "L1D_CACHE.LD",
         "SampleAfterValue": "2000000",
@@ -33,7 +29,6 @@
     },
     {
         "BriefDescription": "L1 Data line replacements",
-        "Counter": "0,1",
         "EventCode": "0x40",
         "EventName": "L1D_CACHE.REPL",
         "SampleAfterValue": "200000",
@@ -41,7 +36,6 @@
     },
     {
         "BriefDescription": "Modified cache lines allocated in the L1 data cache",
-        "Counter": "0,1",
         "EventCode": "0x40",
         "EventName": "L1D_CACHE.REPLM",
         "SampleAfterValue": "200000",
@@ -49,7 +43,6 @@
     },
     {
         "BriefDescription": "L1 Cacheable Data Writes",
-        "Counter": "0,1",
         "EventCode": "0x40",
         "EventName": "L1D_CACHE.ST",
         "SampleAfterValue": "2000000",
@@ -57,7 +50,6 @@
     },
     {
         "BriefDescription": "Cycles L2 address bus is in use.",
-        "Counter": "0,1",
         "EventCode": "0x21",
         "EventName": "L2_ADS.SELF",
         "SampleAfterValue": "200000",
@@ -65,7 +57,6 @@
     },
     {
         "BriefDescription": "All data requests from the L1 data cache",
-        "Counter": "0,1",
         "EventCode": "0x2C",
         "EventName": "L2_DATA_RQSTS.SELF.E_STATE",
         "SampleAfterValue": "200000",
@@ -73,7 +64,6 @@
     },
     {
         "BriefDescription": "All data requests from the L1 data cache",
-        "Counter": "0,1",
         "EventCode": "0x2C",
         "EventName": "L2_DATA_RQSTS.SELF.I_STATE",
         "SampleAfterValue": "200000",
@@ -81,7 +71,6 @@
     },
     {
         "BriefDescription": "All data requests from the L1 data cache",
-        "Counter": "0,1",
         "EventCode": "0x2C",
         "EventName": "L2_DATA_RQSTS.SELF.MESI",
         "SampleAfterValue": "200000",
@@ -89,7 +78,6 @@
     },
     {
         "BriefDescription": "All data requests from the L1 data cache",
-        "Counter": "0,1",
         "EventCode": "0x2C",
         "EventName": "L2_DATA_RQSTS.SELF.M_STATE",
         "SampleAfterValue": "200000",
@@ -97,7 +85,6 @@
     },
     {
         "BriefDescription": "All data requests from the L1 data cache",
-        "Counter": "0,1",
         "EventCode": "0x2C",
         "EventName": "L2_DATA_RQSTS.SELF.S_STATE",
         "SampleAfterValue": "200000",
@@ -105,7 +92,6 @@
     },
     {
         "BriefDescription": "Cycles the L2 cache data bus is busy.",
-        "Counter": "0,1",
         "EventCode": "0x22",
         "EventName": "L2_DBUS_BUSY.SELF",
         "SampleAfterValue": "200000",
@@ -113,7 +99,6 @@
     },
     {
         "BriefDescription": "Cycles the L2 transfers data to the core.",
-        "Counter": "0,1",
         "EventCode": "0x23",
         "EventName": "L2_DBUS_BUSY_RD.SELF",
         "SampleAfterValue": "200000",
@@ -121,7 +106,6 @@
     },
     {
         "BriefDescription": "L2 cacheable instruction fetch requests",
-        "Counter": "0,1",
         "EventCode": "0x28",
         "EventName": "L2_IFETCH.SELF.E_STATE",
         "SampleAfterValue": "200000",
@@ -129,7 +113,6 @@
     },
     {
         "BriefDescription": "L2 cacheable instruction fetch requests",
-        "Counter": "0,1",
         "EventCode": "0x28",
         "EventName": "L2_IFETCH.SELF.I_STATE",
         "SampleAfterValue": "200000",
@@ -137,7 +120,6 @@
     },
     {
         "BriefDescription": "L2 cacheable instruction fetch requests",
-        "Counter": "0,1",
         "EventCode": "0x28",
         "EventName": "L2_IFETCH.SELF.MESI",
         "SampleAfterValue": "200000",
@@ -145,7 +127,6 @@
     },
     {
         "BriefDescription": "L2 cacheable instruction fetch requests",
-        "Counter": "0,1",
         "EventCode": "0x28",
         "EventName": "L2_IFETCH.SELF.M_STATE",
         "SampleAfterValue": "200000",
@@ -153,7 +134,6 @@
     },
     {
         "BriefDescription": "L2 cacheable instruction fetch requests",
-        "Counter": "0,1",
         "EventCode": "0x28",
         "EventName": "L2_IFETCH.SELF.S_STATE",
         "SampleAfterValue": "200000",
@@ -161,7 +141,6 @@
     },
     {
         "BriefDescription": "L2 cache reads",
-        "Counter": "0,1",
         "EventCode": "0x29",
         "EventName": "L2_LD.SELF.ANY.E_STATE",
         "SampleAfterValue": "200000",
@@ -169,7 +148,6 @@
     },
     {
         "BriefDescription": "L2 cache reads",
-        "Counter": "0,1",
         "EventCode": "0x29",
         "EventName": "L2_LD.SELF.ANY.I_STATE",
         "SampleAfterValue": "200000",
@@ -177,7 +155,6 @@
     },
     {
         "BriefDescription": "L2 cache reads",
-        "Counter": "0,1",
         "EventCode": "0x29",
         "EventName": "L2_LD.SELF.ANY.MESI",
         "SampleAfterValue": "200000",
@@ -185,7 +162,6 @@
     },
     {
         "BriefDescription": "L2 cache reads",
-        "Counter": "0,1",
         "EventCode": "0x29",
         "EventName": "L2_LD.SELF.ANY.M_STATE",
         "SampleAfterValue": "200000",
@@ -193,7 +169,6 @@
     },
     {
         "BriefDescription": "L2 cache reads",
-        "Counter": "0,1",
         "EventCode": "0x29",
         "EventName": "L2_LD.SELF.ANY.S_STATE",
         "SampleAfterValue": "200000",
@@ -201,7 +176,6 @@
     },
     {
         "BriefDescription": "L2 cache reads",
-        "Counter": "0,1",
         "EventCode": "0x29",
         "EventName": "L2_LD.SELF.DEMAND.E_STATE",
         "SampleAfterValue": "200000",
@@ -209,7 +183,6 @@
     },
     {
         "BriefDescription": "L2 cache reads",
-        "Counter": "0,1",
         "EventCode": "0x29",
         "EventName": "L2_LD.SELF.DEMAND.I_STATE",
         "SampleAfterValue": "200000",
@@ -217,7 +190,6 @@
     },
     {
         "BriefDescription": "L2 cache reads",
-        "Counter": "0,1",
         "EventCode": "0x29",
         "EventName": "L2_LD.SELF.DEMAND.MESI",
         "SampleAfterValue": "200000",
@@ -225,7 +197,6 @@
     },
     {
         "BriefDescription": "L2 cache reads",
-        "Counter": "0,1",
         "EventCode": "0x29",
         "EventName": "L2_LD.SELF.DEMAND.M_STATE",
         "SampleAfterValue": "200000",
@@ -233,7 +204,6 @@
     },
     {
         "BriefDescription": "L2 cache reads",
-        "Counter": "0,1",
         "EventCode": "0x29",
         "EventName": "L2_LD.SELF.DEMAND.S_STATE",
         "SampleAfterValue": "200000",
@@ -241,7 +211,6 @@
     },
     {
         "BriefDescription": "L2 cache reads",
-        "Counter": "0,1",
         "EventCode": "0x29",
         "EventName": "L2_LD.SELF.PREFETCH.E_STATE",
         "SampleAfterValue": "200000",
@@ -249,7 +218,6 @@
     },
     {
         "BriefDescription": "L2 cache reads",
-        "Counter": "0,1",
         "EventCode": "0x29",
         "EventName": "L2_LD.SELF.PREFETCH.I_STATE",
         "SampleAfterValue": "200000",
@@ -257,7 +225,6 @@
     },
     {
         "BriefDescription": "L2 cache reads",
-        "Counter": "0,1",
         "EventCode": "0x29",
         "EventName": "L2_LD.SELF.PREFETCH.MESI",
         "SampleAfterValue": "200000",
@@ -265,7 +232,6 @@
     },
     {
         "BriefDescription": "L2 cache reads",
-        "Counter": "0,1",
         "EventCode": "0x29",
         "EventName": "L2_LD.SELF.PREFETCH.M_STATE",
         "SampleAfterValue": "200000",
@@ -273,7 +239,6 @@
     },
     {
         "BriefDescription": "L2 cache reads",
-        "Counter": "0,1",
         "EventCode": "0x29",
         "EventName": "L2_LD.SELF.PREFETCH.S_STATE",
         "SampleAfterValue": "200000",
@@ -281,7 +246,6 @@
     },
     {
         "BriefDescription": "All read requests from L1 instruction and data caches",
-        "Counter": "0,1",
         "EventCode": "0x2D",
         "EventName": "L2_LD_IFETCH.SELF.E_STATE",
         "SampleAfterValue": "200000",
@@ -289,7 +253,6 @@
     },
     {
         "BriefDescription": "All read requests from L1 instruction and data caches",
-        "Counter": "0,1",
         "EventCode": "0x2D",
         "EventName": "L2_LD_IFETCH.SELF.I_STATE",
         "SampleAfterValue": "200000",
@@ -297,7 +260,6 @@
     },
     {
         "BriefDescription": "All read requests from L1 instruction and data caches",
-        "Counter": "0,1",
         "EventCode": "0x2D",
         "EventName": "L2_LD_IFETCH.SELF.MESI",
         "SampleAfterValue": "200000",
@@ -305,7 +267,6 @@
     },
     {
         "BriefDescription": "All read requests from L1 instruction and data caches",
-        "Counter": "0,1",
         "EventCode": "0x2D",
         "EventName": "L2_LD_IFETCH.SELF.M_STATE",
         "SampleAfterValue": "200000",
@@ -313,7 +274,6 @@
     },
     {
         "BriefDescription": "All read requests from L1 instruction and data caches",
-        "Counter": "0,1",
         "EventCode": "0x2D",
         "EventName": "L2_LD_IFETCH.SELF.S_STATE",
         "SampleAfterValue": "200000",
@@ -321,7 +281,6 @@
     },
     {
         "BriefDescription": "L2 cache misses.",
-        "Counter": "0,1",
         "EventCode": "0x24",
         "EventName": "L2_LINES_IN.SELF.ANY",
         "SampleAfterValue": "200000",
@@ -329,7 +288,6 @@
     },
     {
         "BriefDescription": "L2 cache misses.",
-        "Counter": "0,1",
         "EventCode": "0x24",
         "EventName": "L2_LINES_IN.SELF.DEMAND",
         "SampleAfterValue": "200000",
@@ -337,7 +295,6 @@
     },
     {
         "BriefDescription": "L2 cache misses.",
-        "Counter": "0,1",
         "EventCode": "0x24",
         "EventName": "L2_LINES_IN.SELF.PREFETCH",
         "SampleAfterValue": "200000",
@@ -345,7 +302,6 @@
     },
     {
         "BriefDescription": "L2 cache lines evicted.",
-        "Counter": "0,1",
         "EventCode": "0x26",
         "EventName": "L2_LINES_OUT.SELF.ANY",
         "SampleAfterValue": "200000",
@@ -353,7 +309,6 @@
     },
     {
         "BriefDescription": "L2 cache lines evicted.",
-        "Counter": "0,1",
         "EventCode": "0x26",
         "EventName": "L2_LINES_OUT.SELF.DEMAND",
         "SampleAfterValue": "200000",
@@ -361,7 +316,6 @@
     },
     {
         "BriefDescription": "L2 cache lines evicted.",
-        "Counter": "0,1",
         "EventCode": "0x26",
         "EventName": "L2_LINES_OUT.SELF.PREFETCH",
         "SampleAfterValue": "200000",
@@ -369,7 +323,6 @@
     },
     {
         "BriefDescription": "L2 locked accesses",
-        "Counter": "0,1",
         "EventCode": "0x2B",
         "EventName": "L2_LOCK.SELF.E_STATE",
         "SampleAfterValue": "200000",
@@ -377,7 +330,6 @@
     },
     {
         "BriefDescription": "L2 locked accesses",
-        "Counter": "0,1",
         "EventCode": "0x2B",
         "EventName": "L2_LOCK.SELF.I_STATE",
         "SampleAfterValue": "200000",
@@ -385,7 +337,6 @@
     },
     {
         "BriefDescription": "L2 locked accesses",
-        "Counter": "0,1",
         "EventCode": "0x2B",
         "EventName": "L2_LOCK.SELF.MESI",
         "SampleAfterValue": "200000",
@@ -393,7 +344,6 @@
     },
     {
         "BriefDescription": "L2 locked accesses",
-        "Counter": "0,1",
         "EventCode": "0x2B",
         "EventName": "L2_LOCK.SELF.M_STATE",
         "SampleAfterValue": "200000",
@@ -401,7 +351,6 @@
     },
     {
         "BriefDescription": "L2 locked accesses",
-        "Counter": "0,1",
         "EventCode": "0x2B",
         "EventName": "L2_LOCK.SELF.S_STATE",
         "SampleAfterValue": "200000",
@@ -409,7 +358,6 @@
     },
     {
         "BriefDescription": "L2 cache line modifications.",
-        "Counter": "0,1",
         "EventCode": "0x25",
         "EventName": "L2_M_LINES_IN.SELF",
         "SampleAfterValue": "200000",
@@ -417,7 +365,6 @@
     },
     {
         "BriefDescription": "Modified lines evicted from the L2 cache",
-        "Counter": "0,1",
         "EventCode": "0x27",
         "EventName": "L2_M_LINES_OUT.SELF.ANY",
         "SampleAfterValue": "200000",
@@ -425,7 +372,6 @@
     },
     {
         "BriefDescription": "Modified lines evicted from the L2 cache",
-        "Counter": "0,1",
         "EventCode": "0x27",
         "EventName": "L2_M_LINES_OUT.SELF.DEMAND",
         "SampleAfterValue": "200000",
@@ -433,7 +379,6 @@
     },
     {
         "BriefDescription": "Modified lines evicted from the L2 cache",
-        "Counter": "0,1",
         "EventCode": "0x27",
         "EventName": "L2_M_LINES_OUT.SELF.PREFETCH",
         "SampleAfterValue": "200000",
@@ -441,7 +386,6 @@
     },
     {
         "BriefDescription": "Cycles no L2 cache requests are pending",
-        "Counter": "0,1",
         "EventCode": "0x32",
         "EventName": "L2_NO_REQ.SELF",
         "SampleAfterValue": "200000",
@@ -449,7 +393,6 @@
     },
     {
         "BriefDescription": "Rejected L2 cache requests",
-        "Counter": "0,1",
         "EventCode": "0x30",
         "EventName": "L2_REJECT_BUSQ.SELF.ANY.E_STATE",
         "SampleAfterValue": "200000",
@@ -457,7 +400,6 @@
     },
     {
         "BriefDescription": "Rejected L2 cache requests",
-        "Counter": "0,1",
         "EventCode": "0x30",
         "EventName": "L2_REJECT_BUSQ.SELF.ANY.I_STATE",
         "SampleAfterValue": "200000",
@@ -465,7 +407,6 @@
     },
     {
         "BriefDescription": "Rejected L2 cache requests",
-        "Counter": "0,1",
         "EventCode": "0x30",
         "EventName": "L2_REJECT_BUSQ.SELF.ANY.MESI",
         "SampleAfterValue": "200000",
@@ -473,7 +414,6 @@
     },
     {
         "BriefDescription": "Rejected L2 cache requests",
-        "Counter": "0,1",
         "EventCode": "0x30",
         "EventName": "L2_REJECT_BUSQ.SELF.ANY.M_STATE",
         "SampleAfterValue": "200000",
@@ -481,7 +421,6 @@
     },
     {
         "BriefDescription": "Rejected L2 cache requests",
-        "Counter": "0,1",
         "EventCode": "0x30",
         "EventName": "L2_REJECT_BUSQ.SELF.ANY.S_STATE",
         "SampleAfterValue": "200000",
@@ -489,7 +428,6 @@
     },
     {
         "BriefDescription": "Rejected L2 cache requests",
-        "Counter": "0,1",
         "EventCode": "0x30",
         "EventName": "L2_REJECT_BUSQ.SELF.DEMAND.E_STATE",
         "SampleAfterValue": "200000",
@@ -497,7 +435,6 @@
     },
     {
         "BriefDescription": "Rejected L2 cache requests",
-        "Counter": "0,1",
         "EventCode": "0x30",
         "EventName": "L2_REJECT_BUSQ.SELF.DEMAND.I_STATE",
         "SampleAfterValue": "200000",
@@ -505,7 +442,6 @@
     },
     {
         "BriefDescription": "Rejected L2 cache requests",
-        "Counter": "0,1",
         "EventCode": "0x30",
         "EventName": "L2_REJECT_BUSQ.SELF.DEMAND.MESI",
         "SampleAfterValue": "200000",
@@ -513,7 +449,6 @@
     },
     {
         "BriefDescription": "Rejected L2 cache requests",
-        "Counter": "0,1",
         "EventCode": "0x30",
         "EventName": "L2_REJECT_BUSQ.SELF.DEMAND.M_STATE",
         "SampleAfterValue": "200000",
@@ -521,7 +456,6 @@
     },
     {
         "BriefDescription": "Rejected L2 cache requests",
-        "Counter": "0,1",
         "EventCode": "0x30",
         "EventName": "L2_REJECT_BUSQ.SELF.DEMAND.S_STATE",
         "SampleAfterValue": "200000",
@@ -529,7 +463,6 @@
     },
     {
         "BriefDescription": "Rejected L2 cache requests",
-        "Counter": "0,1",
         "EventCode": "0x30",
         "EventName": "L2_REJECT_BUSQ.SELF.PREFETCH.E_STATE",
         "SampleAfterValue": "200000",
@@ -537,7 +470,6 @@
     },
     {
         "BriefDescription": "Rejected L2 cache requests",
-        "Counter": "0,1",
         "EventCode": "0x30",
         "EventName": "L2_REJECT_BUSQ.SELF.PREFETCH.I_STATE",
         "SampleAfterValue": "200000",
@@ -545,7 +477,6 @@
     },
     {
         "BriefDescription": "Rejected L2 cache requests",
-        "Counter": "0,1",
         "EventCode": "0x30",
         "EventName": "L2_REJECT_BUSQ.SELF.PREFETCH.MESI",
         "SampleAfterValue": "200000",
@@ -553,7 +484,6 @@
     },
     {
         "BriefDescription": "Rejected L2 cache requests",
-        "Counter": "0,1",
         "EventCode": "0x30",
         "EventName": "L2_REJECT_BUSQ.SELF.PREFETCH.M_STATE",
         "SampleAfterValue": "200000",
@@ -561,7 +491,6 @@
     },
     {
         "BriefDescription": "Rejected L2 cache requests",
-        "Counter": "0,1",
         "EventCode": "0x30",
         "EventName": "L2_REJECT_BUSQ.SELF.PREFETCH.S_STATE",
         "SampleAfterValue": "200000",
@@ -569,7 +498,6 @@
     },
     {
         "BriefDescription": "L2 cache requests",
-        "Counter": "0,1",
         "EventCode": "0x2E",
         "EventName": "L2_RQSTS.SELF.ANY.E_STATE",
         "SampleAfterValue": "200000",
@@ -577,7 +505,6 @@
     },
     {
         "BriefDescription": "L2 cache requests",
-        "Counter": "0,1",
         "EventCode": "0x2E",
         "EventName": "L2_RQSTS.SELF.ANY.I_STATE",
         "SampleAfterValue": "200000",
@@ -585,7 +512,6 @@
     },
     {
         "BriefDescription": "L2 cache requests",
-        "Counter": "0,1",
         "EventCode": "0x2E",
         "EventName": "L2_RQSTS.SELF.ANY.MESI",
         "SampleAfterValue": "200000",
@@ -593,7 +519,6 @@
     },
     {
         "BriefDescription": "L2 cache requests",
-        "Counter": "0,1",
         "EventCode": "0x2E",
         "EventName": "L2_RQSTS.SELF.ANY.M_STATE",
         "SampleAfterValue": "200000",
@@ -601,7 +526,6 @@
     },
     {
         "BriefDescription": "L2 cache requests",
-        "Counter": "0,1",
         "EventCode": "0x2E",
         "EventName": "L2_RQSTS.SELF.ANY.S_STATE",
         "SampleAfterValue": "200000",
@@ -609,7 +533,6 @@
     },
     {
         "BriefDescription": "L2 cache requests",
-        "Counter": "0,1",
         "EventCode": "0x2E",
         "EventName": "L2_RQSTS.SELF.DEMAND.E_STATE",
         "SampleAfterValue": "200000",
@@ -617,7 +540,6 @@
     },
     {
         "BriefDescription": "L2 cache demand requests from this core that missed the L2",
-        "Counter": "0,1",
         "EventCode": "0x2E",
         "EventName": "L2_RQSTS.SELF.DEMAND.I_STATE",
         "SampleAfterValue": "200000",
@@ -625,7 +547,6 @@
     },
     {
         "BriefDescription": "L2 cache demand requests from this core",
-        "Counter": "0,1",
         "EventCode": "0x2E",
         "EventName": "L2_RQSTS.SELF.DEMAND.MESI",
         "SampleAfterValue": "200000",
@@ -633,7 +554,6 @@
     },
     {
         "BriefDescription": "L2 cache requests",
-        "Counter": "0,1",
         "EventCode": "0x2E",
         "EventName": "L2_RQSTS.SELF.DEMAND.M_STATE",
         "SampleAfterValue": "200000",
@@ -641,7 +561,6 @@
     },
     {
         "BriefDescription": "L2 cache requests",
-        "Counter": "0,1",
         "EventCode": "0x2E",
         "EventName": "L2_RQSTS.SELF.DEMAND.S_STATE",
         "SampleAfterValue": "200000",
@@ -649,7 +568,6 @@
     },
     {
         "BriefDescription": "L2 cache requests",
-        "Counter": "0,1",
         "EventCode": "0x2E",
         "EventName": "L2_RQSTS.SELF.PREFETCH.E_STATE",
         "SampleAfterValue": "200000",
@@ -657,7 +575,6 @@
     },
     {
         "BriefDescription": "L2 cache requests",
-        "Counter": "0,1",
         "EventCode": "0x2E",
         "EventName": "L2_RQSTS.SELF.PREFETCH.I_STATE",
         "SampleAfterValue": "200000",
@@ -665,7 +582,6 @@
     },
     {
         "BriefDescription": "L2 cache requests",
-        "Counter": "0,1",
         "EventCode": "0x2E",
         "EventName": "L2_RQSTS.SELF.PREFETCH.MESI",
         "SampleAfterValue": "200000",
@@ -673,7 +589,6 @@
     },
     {
         "BriefDescription": "L2 cache requests",
-        "Counter": "0,1",
         "EventCode": "0x2E",
         "EventName": "L2_RQSTS.SELF.PREFETCH.M_STATE",
         "SampleAfterValue": "200000",
@@ -681,7 +596,6 @@
     },
     {
         "BriefDescription": "L2 cache requests",
-        "Counter": "0,1",
         "EventCode": "0x2E",
         "EventName": "L2_RQSTS.SELF.PREFETCH.S_STATE",
         "SampleAfterValue": "200000",
@@ -689,7 +603,6 @@
     },
     {
         "BriefDescription": "L2 store requests",
-        "Counter": "0,1",
         "EventCode": "0x2A",
         "EventName": "L2_ST.SELF.E_STATE",
         "SampleAfterValue": "200000",
@@ -697,7 +610,6 @@
     },
     {
         "BriefDescription": "L2 store requests",
-        "Counter": "0,1",
         "EventCode": "0x2A",
         "EventName": "L2_ST.SELF.I_STATE",
         "SampleAfterValue": "200000",
@@ -705,7 +617,6 @@
     },
     {
         "BriefDescription": "L2 store requests",
-        "Counter": "0,1",
         "EventCode": "0x2A",
         "EventName": "L2_ST.SELF.MESI",
         "SampleAfterValue": "200000",
@@ -713,7 +624,6 @@
     },
     {
         "BriefDescription": "L2 store requests",
-        "Counter": "0,1",
         "EventCode": "0x2A",
         "EventName": "L2_ST.SELF.M_STATE",
         "SampleAfterValue": "200000",
@@ -721,7 +631,6 @@
     },
     {
         "BriefDescription": "L2 store requests",
-        "Counter": "0,1",
         "EventCode": "0x2A",
         "EventName": "L2_ST.SELF.S_STATE",
         "SampleAfterValue": "200000",
@@ -729,7 +638,6 @@
     },
     {
         "BriefDescription": "Retired loads that hit the L2 cache (precise event).",
-        "Counter": "0,1",
         "EventCode": "0xCB",
         "EventName": "MEM_LOAD_RETIRED.L2_HIT",
         "SampleAfterValue": "200000",
@@ -737,7 +645,6 @@
     },
     {
         "BriefDescription": "Retired loads that miss the L2 cache",
-        "Counter": "0,1",
         "EventCode": "0xCB",
         "EventName": "MEM_LOAD_RETIRED.L2_MISS",
         "SampleAfterValue": "10000",
diff --git a/tools/perf/pmu-events/arch/x86/bonnell/floating-point.json b/tools/perf/pmu-events/arch/x86/bonnell/floating-point.json
index 1fa347d07c98..18bf5ec47e72 100644
--- a/tools/perf/pmu-events/arch/x86/bonnell/floating-point.json
+++ b/tools/perf/pmu-events/arch/x86/bonnell/floating-point.json
@@ -1,7 +1,6 @@
 [
     {
         "BriefDescription": "Floating point assists for retired operations.",
-        "Counter": "0,1",
         "EventCode": "0x11",
         "EventName": "FP_ASSIST.AR",
         "SampleAfterValue": "10000",
@@ -9,7 +8,6 @@
     },
     {
         "BriefDescription": "Floating point assists.",
-        "Counter": "0,1",
         "EventCode": "0x11",
         "EventName": "FP_ASSIST.S",
         "SampleAfterValue": "10000",
@@ -17,15 +15,12 @@
     },
     {
         "BriefDescription": "SIMD assists invoked.",
-        "Counter": "0,1",
         "EventCode": "0xCD",
         "EventName": "SIMD_ASSIST",
-        "SampleAfterValue": "100000",
-        "UMask": "0x0"
+        "SampleAfterValue": "100000"
     },
     {
         "BriefDescription": "Retired computational Streaming SIMD Extensions (SSE) packed-single instructions.",
-        "Counter": "0,1",
         "EventCode": "0xCA",
         "EventName": "SIMD_COMP_INST_RETIRED.PACKED_SINGLE",
         "SampleAfterValue": "2000000",
@@ -33,7 +28,6 @@
     },
     {
         "BriefDescription": "Retired computational Streaming SIMD Extensions 2 (SSE2) scalar-double instructions.",
-        "Counter": "0,1",
         "EventCode": "0xCA",
         "EventName": "SIMD_COMP_INST_RETIRED.SCALAR_DOUBLE",
         "SampleAfterValue": "2000000",
@@ -41,7 +35,6 @@
     },
     {
         "BriefDescription": "Retired computational Streaming SIMD Extensions (SSE) scalar-single instructions.",
-        "Counter": "0,1",
         "EventCode": "0xCA",
         "EventName": "SIMD_COMP_INST_RETIRED.SCALAR_SINGLE",
         "SampleAfterValue": "2000000",
@@ -49,15 +42,12 @@
     },
     {
         "BriefDescription": "SIMD Instructions retired.",
-        "Counter": "0,1",
         "EventCode": "0xCE",
         "EventName": "SIMD_INSTR_RETIRED",
-        "SampleAfterValue": "2000000",
-        "UMask": "0x0"
+        "SampleAfterValue": "2000000"
     },
     {
         "BriefDescription": "Retired Streaming SIMD Extensions (SSE) packed-single instructions.",
-        "Counter": "0,1",
         "EventCode": "0xC7",
         "EventName": "SIMD_INST_RETIRED.PACKED_SINGLE",
         "SampleAfterValue": "2000000",
@@ -65,7 +55,6 @@
     },
     {
         "BriefDescription": "Retired Streaming SIMD Extensions 2 (SSE2) scalar-double instructions.",
-        "Counter": "0,1",
         "EventCode": "0xC7",
         "EventName": "SIMD_INST_RETIRED.SCALAR_DOUBLE",
         "SampleAfterValue": "2000000",
@@ -73,7 +62,6 @@
     },
     {
         "BriefDescription": "Retired Streaming SIMD Extensions (SSE) scalar-single instructions.",
-        "Counter": "0,1",
         "EventCode": "0xC7",
         "EventName": "SIMD_INST_RETIRED.SCALAR_SINGLE",
         "SampleAfterValue": "2000000",
@@ -81,7 +69,6 @@
     },
     {
         "BriefDescription": "Retired Streaming SIMD Extensions 2 (SSE2) vector instructions.",
-        "Counter": "0,1",
         "EventCode": "0xC7",
         "EventName": "SIMD_INST_RETIRED.VECTOR",
         "SampleAfterValue": "2000000",
@@ -89,15 +76,12 @@
     },
     {
         "BriefDescription": "Saturated arithmetic instructions retired.",
-        "Counter": "0,1",
         "EventCode": "0xCF",
         "EventName": "SIMD_SAT_INSTR_RETIRED",
-        "SampleAfterValue": "2000000",
-        "UMask": "0x0"
+        "SampleAfterValue": "2000000"
     },
     {
         "BriefDescription": "SIMD saturated arithmetic micro-ops retired.",
-        "Counter": "0,1",
         "EventCode": "0xB1",
         "EventName": "SIMD_SAT_UOP_EXEC.AR",
         "SampleAfterValue": "2000000",
@@ -105,15 +89,12 @@
     },
     {
         "BriefDescription": "SIMD saturated arithmetic micro-ops executed.",
-        "Counter": "0,1",
         "EventCode": "0xB1",
         "EventName": "SIMD_SAT_UOP_EXEC.S",
-        "SampleAfterValue": "2000000",
-        "UMask": "0x0"
+        "SampleAfterValue": "2000000"
     },
     {
         "BriefDescription": "SIMD micro-ops retired (excluding stores).",
-        "Counter": "0,1",
         "EventCode": "0xB0",
         "EventName": "SIMD_UOPS_EXEC.AR",
         "PEBS": "2",
@@ -122,15 +103,12 @@
     },
     {
         "BriefDescription": "SIMD micro-ops executed (excluding stores).",
-        "Counter": "0,1",
         "EventCode": "0xB0",
         "EventName": "SIMD_UOPS_EXEC.S",
-        "SampleAfterValue": "2000000",
-        "UMask": "0x0"
+        "SampleAfterValue": "2000000"
     },
     {
         "BriefDescription": "SIMD packed arithmetic micro-ops retired",
-        "Counter": "0,1",
         "EventCode": "0xB3",
         "EventName": "SIMD_UOP_TYPE_EXEC.ARITHMETIC.AR",
         "SampleAfterValue": "2000000",
@@ -138,7 +116,6 @@
     },
     {
         "BriefDescription": "SIMD packed arithmetic micro-ops executed",
-        "Counter": "0,1",
         "EventCode": "0xB3",
         "EventName": "SIMD_UOP_TYPE_EXEC.ARITHMETIC.S",
         "SampleAfterValue": "2000000",
@@ -146,7 +123,6 @@
     },
     {
         "BriefDescription": "SIMD packed logical micro-ops retired",
-        "Counter": "0,1",
         "EventCode": "0xB3",
         "EventName": "SIMD_UOP_TYPE_EXEC.LOGICAL.AR",
         "SampleAfterValue": "2000000",
@@ -154,7 +130,6 @@
     },
     {
         "BriefDescription": "SIMD packed logical micro-ops executed",
-        "Counter": "0,1",
         "EventCode": "0xB3",
         "EventName": "SIMD_UOP_TYPE_EXEC.LOGICAL.S",
         "SampleAfterValue": "2000000",
@@ -162,7 +137,6 @@
     },
     {
         "BriefDescription": "SIMD packed multiply micro-ops retired",
-        "Counter": "0,1",
         "EventCode": "0xB3",
         "EventName": "SIMD_UOP_TYPE_EXEC.MUL.AR",
         "SampleAfterValue": "2000000",
@@ -170,7 +144,6 @@
     },
     {
         "BriefDescription": "SIMD packed multiply micro-ops executed",
-        "Counter": "0,1",
         "EventCode": "0xB3",
         "EventName": "SIMD_UOP_TYPE_EXEC.MUL.S",
         "SampleAfterValue": "2000000",
@@ -178,7 +151,6 @@
     },
     {
         "BriefDescription": "SIMD packed micro-ops retired",
-        "Counter": "0,1",
         "EventCode": "0xB3",
         "EventName": "SIMD_UOP_TYPE_EXEC.PACK.AR",
         "SampleAfterValue": "2000000",
@@ -186,7 +158,6 @@
     },
     {
         "BriefDescription": "SIMD packed micro-ops executed",
-        "Counter": "0,1",
         "EventCode": "0xB3",
         "EventName": "SIMD_UOP_TYPE_EXEC.PACK.S",
         "SampleAfterValue": "2000000",
@@ -194,7 +165,6 @@
     },
     {
         "BriefDescription": "SIMD packed shift micro-ops retired",
-        "Counter": "0,1",
         "EventCode": "0xB3",
         "EventName": "SIMD_UOP_TYPE_EXEC.SHIFT.AR",
         "SampleAfterValue": "2000000",
@@ -202,7 +172,6 @@
     },
     {
         "BriefDescription": "SIMD packed shift micro-ops executed",
-        "Counter": "0,1",
         "EventCode": "0xB3",
         "EventName": "SIMD_UOP_TYPE_EXEC.SHIFT.S",
         "SampleAfterValue": "2000000",
@@ -210,7 +179,6 @@
     },
     {
         "BriefDescription": "SIMD unpacked micro-ops retired",
-        "Counter": "0,1",
         "EventCode": "0xB3",
         "EventName": "SIMD_UOP_TYPE_EXEC.UNPACK.AR",
         "SampleAfterValue": "2000000",
@@ -218,7 +186,6 @@
     },
     {
         "BriefDescription": "SIMD unpacked micro-ops executed",
-        "Counter": "0,1",
         "EventCode": "0xB3",
         "EventName": "SIMD_UOP_TYPE_EXEC.UNPACK.S",
         "SampleAfterValue": "2000000",
@@ -226,7 +193,6 @@
     },
     {
         "BriefDescription": "Floating point computational micro-ops retired.",
-        "Counter": "0,1",
         "EventCode": "0x10",
         "EventName": "X87_COMP_OPS_EXE.ANY.AR",
         "PEBS": "2",
@@ -235,7 +201,6 @@
     },
     {
         "BriefDescription": "Floating point computational micro-ops executed.",
-        "Counter": "0,1",
         "EventCode": "0x10",
         "EventName": "X87_COMP_OPS_EXE.ANY.S",
         "SampleAfterValue": "2000000",
@@ -243,7 +208,6 @@
     },
     {
         "BriefDescription": "FXCH uops retired.",
-        "Counter": "0,1",
         "EventCode": "0x10",
         "EventName": "X87_COMP_OPS_EXE.FXCH.AR",
         "PEBS": "2",
@@ -252,7 +216,6 @@
     },
     {
         "BriefDescription": "FXCH uops executed.",
-        "Counter": "0,1",
         "EventCode": "0x10",
         "EventName": "X87_COMP_OPS_EXE.FXCH.S",
         "SampleAfterValue": "2000000",
diff --git a/tools/perf/pmu-events/arch/x86/bonnell/frontend.json b/tools/perf/pmu-events/arch/x86/bonnell/frontend.json
index 21fe5fe229aa..8d2f4edfb597 100644
--- a/tools/perf/pmu-events/arch/x86/bonnell/frontend.json
+++ b/tools/perf/pmu-events/arch/x86/bonnell/frontend.json
@@ -1,7 +1,6 @@
 [
     {
         "BriefDescription": "BACLEARS asserted.",
-        "Counter": "0,1",
         "EventCode": "0xE6",
         "EventName": "BACLEARS.ANY",
         "SampleAfterValue": "2000000",
@@ -9,7 +8,6 @@
     },
     {
         "BriefDescription": "Cycles during which instruction fetches are  stalled.",
-        "Counter": "0,1",
         "EventCode": "0x86",
         "EventName": "CYCLES_ICACHE_MEM_STALLED.ICACHE_MEM_STALLED",
         "SampleAfterValue": "2000000",
@@ -17,7 +15,6 @@
     },
     {
         "BriefDescription": "Decode stall due to IQ full",
-        "Counter": "0,1",
         "EventCode": "0x87",
         "EventName": "DECODE_STALL.IQ_FULL",
         "SampleAfterValue": "2000000",
@@ -25,7 +22,6 @@
     },
     {
         "BriefDescription": "Decode stall due to PFB empty",
-        "Counter": "0,1",
         "EventCode": "0x87",
         "EventName": "DECODE_STALL.PFB_EMPTY",
         "SampleAfterValue": "2000000",
@@ -33,7 +29,6 @@
     },
     {
         "BriefDescription": "Instruction fetches.",
-        "Counter": "0,1",
         "EventCode": "0x80",
         "EventName": "ICACHE.ACCESSES",
         "SampleAfterValue": "200000",
@@ -41,7 +36,6 @@
     },
     {
         "BriefDescription": "Icache hit",
-        "Counter": "0,1",
         "EventCode": "0x80",
         "EventName": "ICACHE.HIT",
         "SampleAfterValue": "200000",
@@ -49,7 +43,6 @@
     },
     {
         "BriefDescription": "Icache miss",
-        "Counter": "0,1",
         "EventCode": "0x80",
         "EventName": "ICACHE.MISSES",
         "SampleAfterValue": "200000",
@@ -57,7 +50,6 @@
     },
     {
         "BriefDescription": "All Instructions decoded",
-        "Counter": "0,1",
         "EventCode": "0xAA",
         "EventName": "MACRO_INSTS.ALL_DECODED",
         "SampleAfterValue": "2000000",
@@ -65,7 +57,6 @@
     },
     {
         "BriefDescription": "CISC macro instructions decoded",
-        "Counter": "0,1",
         "EventCode": "0xAA",
         "EventName": "MACRO_INSTS.CISC_DECODED",
         "SampleAfterValue": "2000000",
@@ -73,7 +64,6 @@
     },
     {
         "BriefDescription": "Non-CISC nacro instructions decoded",
-        "Counter": "0,1",
         "EventCode": "0xAA",
         "EventName": "MACRO_INSTS.NON_CISC_DECODED",
         "SampleAfterValue": "2000000",
@@ -81,7 +71,6 @@
     },
     {
         "BriefDescription": "This event counts the cycles where 1 or more uops are issued by the micro-sequencer (MS), including microcode assists and inserted flows, and written to the IQ.",
-        "Counter": "0,1",
         "CounterMask": "1",
         "EventCode": "0xA9",
         "EventName": "UOPS.MS_CYCLES",
diff --git a/tools/perf/pmu-events/arch/x86/bonnell/memory.json b/tools/perf/pmu-events/arch/x86/bonnell/memory.json
index f8b45b6fb4d3..ac02dc2482c8 100644
--- a/tools/perf/pmu-events/arch/x86/bonnell/memory.json
+++ b/tools/perf/pmu-events/arch/x86/bonnell/memory.json
@@ -1,7 +1,6 @@
 [
     {
         "BriefDescription": "Nonzero segbase 1 bubble",
-        "Counter": "0,1",
         "EventCode": "0x5",
         "EventName": "MISALIGN_MEM_REF.BUBBLE",
         "SampleAfterValue": "200000",
@@ -9,7 +8,6 @@
     },
     {
         "BriefDescription": "Nonzero segbase load 1 bubble",
-        "Counter": "0,1",
         "EventCode": "0x5",
         "EventName": "MISALIGN_MEM_REF.LD_BUBBLE",
         "SampleAfterValue": "200000",
@@ -17,7 +15,6 @@
     },
     {
         "BriefDescription": "Load splits",
-        "Counter": "0,1",
         "EventCode": "0x5",
         "EventName": "MISALIGN_MEM_REF.LD_SPLIT",
         "SampleAfterValue": "200000",
@@ -25,7 +22,6 @@
     },
     {
         "BriefDescription": "Load splits (At Retirement)",
-        "Counter": "0,1",
         "EventCode": "0x5",
         "EventName": "MISALIGN_MEM_REF.LD_SPLIT.AR",
         "SampleAfterValue": "200000",
@@ -33,7 +29,6 @@
     },
     {
         "BriefDescription": "Nonzero segbase ld-op-st 1 bubble",
-        "Counter": "0,1",
         "EventCode": "0x5",
         "EventName": "MISALIGN_MEM_REF.RMW_BUBBLE",
         "SampleAfterValue": "200000",
@@ -41,7 +36,6 @@
     },
     {
         "BriefDescription": "ld-op-st splits",
-        "Counter": "0,1",
         "EventCode": "0x5",
         "EventName": "MISALIGN_MEM_REF.RMW_SPLIT",
         "SampleAfterValue": "200000",
@@ -49,7 +43,6 @@
     },
     {
         "BriefDescription": "Memory references that cross an 8-byte boundary.",
-        "Counter": "0,1",
         "EventCode": "0x5",
         "EventName": "MISALIGN_MEM_REF.SPLIT",
         "SampleAfterValue": "200000",
@@ -57,7 +50,6 @@
     },
     {
         "BriefDescription": "Memory references that cross an 8-byte boundary (At Retirement)",
-        "Counter": "0,1",
         "EventCode": "0x5",
         "EventName": "MISALIGN_MEM_REF.SPLIT.AR",
         "SampleAfterValue": "200000",
@@ -65,7 +57,6 @@
     },
     {
         "BriefDescription": "Nonzero segbase store 1 bubble",
-        "Counter": "0,1",
         "EventCode": "0x5",
         "EventName": "MISALIGN_MEM_REF.ST_BUBBLE",
         "SampleAfterValue": "200000",
@@ -73,7 +64,6 @@
     },
     {
         "BriefDescription": "Store splits",
-        "Counter": "0,1",
         "EventCode": "0x5",
         "EventName": "MISALIGN_MEM_REF.ST_SPLIT",
         "SampleAfterValue": "200000",
@@ -81,7 +71,6 @@
     },
     {
         "BriefDescription": "Store splits (Ar Retirement)",
-        "Counter": "0,1",
         "EventCode": "0x5",
         "EventName": "MISALIGN_MEM_REF.ST_SPLIT.AR",
         "SampleAfterValue": "200000",
@@ -89,7 +78,6 @@
     },
     {
         "BriefDescription": "L1 hardware prefetch request",
-        "Counter": "0,1",
         "EventCode": "0x7",
         "EventName": "PREFETCH.HW_PREFETCH",
         "SampleAfterValue": "2000000",
@@ -97,7 +85,6 @@
     },
     {
         "BriefDescription": "Streaming SIMD Extensions (SSE) Prefetch NTA instructions executed",
-        "Counter": "0,1",
         "EventCode": "0x7",
         "EventName": "PREFETCH.PREFETCHNTA",
         "SampleAfterValue": "200000",
@@ -105,7 +92,6 @@
     },
     {
         "BriefDescription": "Streaming SIMD Extensions (SSE) PrefetchT0 instructions executed.",
-        "Counter": "0,1",
         "EventCode": "0x7",
         "EventName": "PREFETCH.PREFETCHT0",
         "SampleAfterValue": "200000",
@@ -113,7 +99,6 @@
     },
     {
         "BriefDescription": "Streaming SIMD Extensions (SSE) PrefetchT1 instructions executed.",
-        "Counter": "0,1",
         "EventCode": "0x7",
         "EventName": "PREFETCH.PREFETCHT1",
         "SampleAfterValue": "200000",
@@ -121,7 +106,6 @@
     },
     {
         "BriefDescription": "Streaming SIMD Extensions (SSE) PrefetchT2 instructions executed.",
-        "Counter": "0,1",
         "EventCode": "0x7",
         "EventName": "PREFETCH.PREFETCHT2",
         "SampleAfterValue": "200000",
@@ -129,7 +113,6 @@
     },
     {
         "BriefDescription": "Any Software prefetch",
-        "Counter": "0,1",
         "EventCode": "0x7",
         "EventName": "PREFETCH.SOFTWARE_PREFETCH",
         "SampleAfterValue": "200000",
@@ -137,7 +120,6 @@
     },
     {
         "BriefDescription": "Any Software prefetch",
-        "Counter": "0,1",
         "EventCode": "0x7",
         "EventName": "PREFETCH.SOFTWARE_PREFETCH.AR",
         "SampleAfterValue": "200000",
@@ -145,7 +127,6 @@
     },
     {
         "BriefDescription": "Streaming SIMD Extensions (SSE) PrefetchT1 and PrefetchT2 instructions executed",
-        "Counter": "0,1",
         "EventCode": "0x7",
         "EventName": "PREFETCH.SW_L2",
         "SampleAfterValue": "200000",
diff --git a/tools/perf/pmu-events/arch/x86/bonnell/other.json b/tools/perf/pmu-events/arch/x86/bonnell/other.json
index e0bdcfbfa9dc..782594c8bda5 100644
--- a/tools/perf/pmu-events/arch/x86/bonnell/other.json
+++ b/tools/perf/pmu-events/arch/x86/bonnell/other.json
@@ -1,7 +1,6 @@
 [
     {
         "BriefDescription": "Bus queue is empty.",
-        "Counter": "0,1",
         "EventCode": "0x7D",
         "EventName": "BUSQ_EMPTY.SELF",
         "SampleAfterValue": "200000",
@@ -9,7 +8,6 @@
     },
     {
         "BriefDescription": "Number of Bus Not Ready signals asserted.",
-        "Counter": "0,1",
         "EventCode": "0x61",
         "EventName": "BUS_BNR_DRV.ALL_AGENTS",
         "SampleAfterValue": "200000",
@@ -17,15 +15,12 @@
     },
     {
         "BriefDescription": "Number of Bus Not Ready signals asserted.",
-        "Counter": "0,1",
         "EventCode": "0x61",
         "EventName": "BUS_BNR_DRV.THIS_AGENT",
-        "SampleAfterValue": "200000",
-        "UMask": "0x0"
+        "SampleAfterValue": "200000"
     },
     {
         "BriefDescription": "Bus cycles while processor receives data.",
-        "Counter": "0,1",
         "EventCode": "0x64",
         "EventName": "BUS_DATA_RCV.SELF",
         "SampleAfterValue": "200000",
@@ -33,7 +28,6 @@
     },
     {
         "BriefDescription": "Bus cycles when data is sent on the bus.",
-        "Counter": "0,1",
         "EventCode": "0x62",
         "EventName": "BUS_DRDY_CLOCKS.ALL_AGENTS",
         "SampleAfterValue": "200000",
@@ -41,15 +35,12 @@
     },
     {
         "BriefDescription": "Bus cycles when data is sent on the bus.",
-        "Counter": "0,1",
         "EventCode": "0x62",
         "EventName": "BUS_DRDY_CLOCKS.THIS_AGENT",
-        "SampleAfterValue": "200000",
-        "UMask": "0x0"
+        "SampleAfterValue": "200000"
     },
     {
         "BriefDescription": "HITM signal asserted.",
-        "Counter": "0,1",
         "EventCode": "0x7B",
         "EventName": "BUS_HITM_DRV.ALL_AGENTS",
         "SampleAfterValue": "200000",
@@ -57,15 +48,12 @@
     },
     {
         "BriefDescription": "HITM signal asserted.",
-        "Counter": "0,1",
         "EventCode": "0x7B",
         "EventName": "BUS_HITM_DRV.THIS_AGENT",
-        "SampleAfterValue": "200000",
-        "UMask": "0x0"
+        "SampleAfterValue": "200000"
     },
     {
         "BriefDescription": "HIT signal asserted.",
-        "Counter": "0,1",
         "EventCode": "0x7A",
         "EventName": "BUS_HIT_DRV.ALL_AGENTS",
         "SampleAfterValue": "200000",
@@ -73,15 +61,12 @@
     },
     {
         "BriefDescription": "HIT signal asserted.",
-        "Counter": "0,1",
         "EventCode": "0x7A",
         "EventName": "BUS_HIT_DRV.THIS_AGENT",
-        "SampleAfterValue": "200000",
-        "UMask": "0x0"
+        "SampleAfterValue": "200000"
     },
     {
         "BriefDescription": "IO requests waiting in the bus queue.",
-        "Counter": "0,1",
         "EventCode": "0x7F",
         "EventName": "BUS_IO_WAIT.SELF",
         "SampleAfterValue": "200000",
@@ -89,7 +74,6 @@
     },
     {
         "BriefDescription": "Bus cycles when a LOCK signal is asserted.",
-        "Counter": "0,1",
         "EventCode": "0x63",
         "EventName": "BUS_LOCK_CLOCKS.ALL_AGENTS",
         "SampleAfterValue": "200000",
@@ -97,7 +81,6 @@
     },
     {
         "BriefDescription": "Bus cycles when a LOCK signal is asserted.",
-        "Counter": "0,1",
         "EventCode": "0x63",
         "EventName": "BUS_LOCK_CLOCKS.SELF",
         "SampleAfterValue": "200000",
@@ -105,7 +88,6 @@
     },
     {
         "BriefDescription": "Outstanding cacheable data read bus requests duration.",
-        "Counter": "0,1",
         "EventCode": "0x60",
         "EventName": "BUS_REQUEST_OUTSTANDING.ALL_AGENTS",
         "SampleAfterValue": "200000",
@@ -113,7 +95,6 @@
     },
     {
         "BriefDescription": "Outstanding cacheable data read bus requests duration.",
-        "Counter": "0,1",
         "EventCode": "0x60",
         "EventName": "BUS_REQUEST_OUTSTANDING.SELF",
         "SampleAfterValue": "200000",
@@ -121,7 +102,6 @@
     },
     {
         "BriefDescription": "All bus transactions.",
-        "Counter": "0,1",
         "EventCode": "0x70",
         "EventName": "BUS_TRANS_ANY.ALL_AGENTS",
         "SampleAfterValue": "200000",
@@ -129,7 +109,6 @@
     },
     {
         "BriefDescription": "All bus transactions.",
-        "Counter": "0,1",
         "EventCode": "0x70",
         "EventName": "BUS_TRANS_ANY.SELF",
         "SampleAfterValue": "200000",
@@ -137,7 +116,6 @@
     },
     {
         "BriefDescription": "Burst read bus transactions.",
-        "Counter": "0,1",
         "EventCode": "0x65",
         "EventName": "BUS_TRANS_BRD.ALL_AGENTS",
         "SampleAfterValue": "200000",
@@ -145,7 +123,6 @@
     },
     {
         "BriefDescription": "Burst read bus transactions.",
-        "Counter": "0,1",
         "EventCode": "0x65",
         "EventName": "BUS_TRANS_BRD.SELF",
         "SampleAfterValue": "200000",
@@ -153,7 +130,6 @@
     },
     {
         "BriefDescription": "Burst (full cache-line) bus transactions.",
-        "Counter": "0,1",
         "EventCode": "0x6E",
         "EventName": "BUS_TRANS_BURST.ALL_AGENTS",
         "SampleAfterValue": "200000",
@@ -161,7 +137,6 @@
     },
     {
         "BriefDescription": "Burst (full cache-line) bus transactions.",
-        "Counter": "0,1",
         "EventCode": "0x6E",
         "EventName": "BUS_TRANS_BURST.SELF",
         "SampleAfterValue": "200000",
@@ -169,7 +144,6 @@
     },
     {
         "BriefDescription": "Deferred bus transactions.",
-        "Counter": "0,1",
         "EventCode": "0x6D",
         "EventName": "BUS_TRANS_DEF.ALL_AGENTS",
         "SampleAfterValue": "200000",
@@ -177,7 +151,6 @@
     },
     {
         "BriefDescription": "Deferred bus transactions.",
-        "Counter": "0,1",
         "EventCode": "0x6D",
         "EventName": "BUS_TRANS_DEF.SELF",
         "SampleAfterValue": "200000",
@@ -185,7 +158,6 @@
     },
     {
         "BriefDescription": "Instruction-fetch bus transactions.",
-        "Counter": "0,1",
         "EventCode": "0x68",
         "EventName": "BUS_TRANS_IFETCH.ALL_AGENTS",
         "SampleAfterValue": "200000",
@@ -193,7 +165,6 @@
     },
     {
         "BriefDescription": "Instruction-fetch bus transactions.",
-        "Counter": "0,1",
         "EventCode": "0x68",
         "EventName": "BUS_TRANS_IFETCH.SELF",
         "SampleAfterValue": "200000",
@@ -201,7 +172,6 @@
     },
     {
         "BriefDescription": "Invalidate bus transactions.",
-        "Counter": "0,1",
         "EventCode": "0x69",
         "EventName": "BUS_TRANS_INVAL.ALL_AGENTS",
         "SampleAfterValue": "200000",
@@ -209,7 +179,6 @@
     },
     {
         "BriefDescription": "Invalidate bus transactions.",
-        "Counter": "0,1",
         "EventCode": "0x69",
         "EventName": "BUS_TRANS_INVAL.SELF",
         "SampleAfterValue": "200000",
@@ -217,7 +186,6 @@
     },
     {
         "BriefDescription": "IO bus transactions.",
-        "Counter": "0,1",
         "EventCode": "0x6C",
         "EventName": "BUS_TRANS_IO.ALL_AGENTS",
         "SampleAfterValue": "200000",
@@ -225,7 +193,6 @@
     },
     {
         "BriefDescription": "IO bus transactions.",
-        "Counter": "0,1",
         "EventCode": "0x6C",
         "EventName": "BUS_TRANS_IO.SELF",
         "SampleAfterValue": "200000",
@@ -233,7 +200,6 @@
     },
     {
         "BriefDescription": "Memory bus transactions.",
-        "Counter": "0,1",
         "EventCode": "0x6F",
         "EventName": "BUS_TRANS_MEM.ALL_AGENTS",
         "SampleAfterValue": "200000",
@@ -241,7 +207,6 @@
     },
     {
         "BriefDescription": "Memory bus transactions.",
-        "Counter": "0,1",
         "EventCode": "0x6F",
         "EventName": "BUS_TRANS_MEM.SELF",
         "SampleAfterValue": "200000",
@@ -249,7 +214,6 @@
     },
     {
         "BriefDescription": "Partial bus transactions.",
-        "Counter": "0,1",
         "EventCode": "0x6B",
         "EventName": "BUS_TRANS_P.ALL_AGENTS",
         "SampleAfterValue": "200000",
@@ -257,7 +221,6 @@
     },
     {
         "BriefDescription": "Partial bus transactions.",
-        "Counter": "0,1",
         "EventCode": "0x6B",
         "EventName": "BUS_TRANS_P.SELF",
         "SampleAfterValue": "200000",
@@ -265,7 +228,6 @@
     },
     {
         "BriefDescription": "Partial write bus transaction.",
-        "Counter": "0,1",
         "EventCode": "0x6A",
         "EventName": "BUS_TRANS_PWR.ALL_AGENTS",
         "SampleAfterValue": "200000",
@@ -273,7 +235,6 @@
     },
     {
         "BriefDescription": "Partial write bus transaction.",
-        "Counter": "0,1",
         "EventCode": "0x6A",
         "EventName": "BUS_TRANS_PWR.SELF",
         "SampleAfterValue": "200000",
@@ -281,7 +242,6 @@
     },
     {
         "BriefDescription": "RFO bus transactions.",
-        "Counter": "0,1",
         "EventCode": "0x66",
         "EventName": "BUS_TRANS_RFO.ALL_AGENTS",
         "SampleAfterValue": "200000",
@@ -289,7 +249,6 @@
     },
     {
         "BriefDescription": "RFO bus transactions.",
-        "Counter": "0,1",
         "EventCode": "0x66",
         "EventName": "BUS_TRANS_RFO.SELF",
         "SampleAfterValue": "200000",
@@ -297,7 +256,6 @@
     },
     {
         "BriefDescription": "Explicit writeback bus transactions.",
-        "Counter": "0,1",
         "EventCode": "0x67",
         "EventName": "BUS_TRANS_WB.ALL_AGENTS",
         "SampleAfterValue": "200000",
@@ -305,7 +263,6 @@
     },
     {
         "BriefDescription": "Explicit writeback bus transactions.",
-        "Counter": "0,1",
         "EventCode": "0x67",
         "EventName": "BUS_TRANS_WB.SELF",
         "SampleAfterValue": "200000",
@@ -313,7 +270,6 @@
     },
     {
         "BriefDescription": "Cycles during which interrupts are disabled.",
-        "Counter": "0,1",
         "EventCode": "0xC6",
         "EventName": "CYCLES_INT_MASKED.CYCLES_INT_MASKED",
         "SampleAfterValue": "2000000",
@@ -321,7 +277,6 @@
     },
     {
         "BriefDescription": "Cycles during which interrupts are pending and disabled.",
-        "Counter": "0,1",
         "EventCode": "0xC6",
         "EventName": "CYCLES_INT_MASKED.CYCLES_INT_PENDING_AND_MASKED",
         "SampleAfterValue": "2000000",
@@ -329,7 +284,6 @@
     },
     {
         "BriefDescription": "Memory cluster signals to block micro-op dispatch for any reason",
-        "Counter": "0,1",
         "EventCode": "0x9",
         "EventName": "DISPATCH_BLOCKED.ANY",
         "SampleAfterValue": "200000",
@@ -337,15 +291,12 @@
     },
     {
         "BriefDescription": "Number of Enhanced Intel SpeedStep(R) Technology (EIST) transitions",
-        "Counter": "0,1",
         "EventCode": "0x3A",
         "EventName": "EIST_TRANS",
-        "SampleAfterValue": "200000",
-        "UMask": "0x0"
+        "SampleAfterValue": "200000"
     },
     {
         "BriefDescription": "External snoops.",
-        "Counter": "0,1",
         "EventCode": "0x77",
         "EventName": "EXT_SNOOP.ALL_AGENTS.ANY",
         "SampleAfterValue": "200000",
@@ -353,7 +304,6 @@
     },
     {
         "BriefDescription": "External snoops.",
-        "Counter": "0,1",
         "EventCode": "0x77",
         "EventName": "EXT_SNOOP.ALL_AGENTS.CLEAN",
         "SampleAfterValue": "200000",
@@ -361,7 +311,6 @@
     },
     {
         "BriefDescription": "External snoops.",
-        "Counter": "0,1",
         "EventCode": "0x77",
         "EventName": "EXT_SNOOP.ALL_AGENTS.HIT",
         "SampleAfterValue": "200000",
@@ -369,7 +318,6 @@
     },
     {
         "BriefDescription": "External snoops.",
-        "Counter": "0,1",
         "EventCode": "0x77",
         "EventName": "EXT_SNOOP.ALL_AGENTS.HITM",
         "SampleAfterValue": "200000",
@@ -377,7 +325,6 @@
     },
     {
         "BriefDescription": "External snoops.",
-        "Counter": "0,1",
         "EventCode": "0x77",
         "EventName": "EXT_SNOOP.THIS_AGENT.ANY",
         "SampleAfterValue": "200000",
@@ -385,7 +332,6 @@
     },
     {
         "BriefDescription": "External snoops.",
-        "Counter": "0,1",
         "EventCode": "0x77",
         "EventName": "EXT_SNOOP.THIS_AGENT.CLEAN",
         "SampleAfterValue": "200000",
@@ -393,7 +339,6 @@
     },
     {
         "BriefDescription": "External snoops.",
-        "Counter": "0,1",
         "EventCode": "0x77",
         "EventName": "EXT_SNOOP.THIS_AGENT.HIT",
         "SampleAfterValue": "200000",
@@ -401,7 +346,6 @@
     },
     {
         "BriefDescription": "External snoops.",
-        "Counter": "0,1",
         "EventCode": "0x77",
         "EventName": "EXT_SNOOP.THIS_AGENT.HITM",
         "SampleAfterValue": "200000",
@@ -409,15 +353,12 @@
     },
     {
         "BriefDescription": "Hardware interrupts received.",
-        "Counter": "0,1",
         "EventCode": "0xC8",
         "EventName": "HW_INT_RCV",
-        "SampleAfterValue": "200000",
-        "UMask": "0x0"
+        "SampleAfterValue": "200000"
     },
     {
         "BriefDescription": "Number of segment register loads.",
-        "Counter": "0,1",
         "EventCode": "0x6",
         "EventName": "SEGMENT_REG_LOADS.ANY",
         "SampleAfterValue": "200000",
@@ -425,7 +366,6 @@
     },
     {
         "BriefDescription": "Bus stalled for snoops.",
-        "Counter": "0,1",
         "EventCode": "0x7E",
         "EventName": "SNOOP_STALL_DRV.ALL_AGENTS",
         "SampleAfterValue": "200000",
@@ -433,7 +373,6 @@
     },
     {
         "BriefDescription": "Bus stalled for snoops.",
-        "Counter": "0,1",
         "EventCode": "0x7E",
         "EventName": "SNOOP_STALL_DRV.SELF",
         "SampleAfterValue": "200000",
@@ -441,7 +380,6 @@
     },
     {
         "BriefDescription": "Number of thermal trips",
-        "Counter": "0,1",
         "EventCode": "0x3B",
         "EventName": "THERMAL_TRIP",
         "SampleAfterValue": "200000",
diff --git a/tools/perf/pmu-events/arch/x86/bonnell/pipeline.json b/tools/perf/pmu-events/arch/x86/bonnell/pipeline.json
index f5123c99a7ba..91b98ee8ba9a 100644
--- a/tools/perf/pmu-events/arch/x86/bonnell/pipeline.json
+++ b/tools/perf/pmu-events/arch/x86/bonnell/pipeline.json
@@ -1,7 +1,6 @@
 [
     {
         "BriefDescription": "Bogus branches",
-        "Counter": "0,1",
         "EventCode": "0xE4",
         "EventName": "BOGUS_BR",
         "SampleAfterValue": "2000000",
@@ -9,7 +8,6 @@
     },
     {
         "BriefDescription": "Branch instructions decoded",
-        "Counter": "0,1",
         "EventCode": "0xE0",
         "EventName": "BR_INST_DECODED",
         "SampleAfterValue": "2000000",
@@ -17,15 +15,12 @@
     },
     {
         "BriefDescription": "Retired branch instructions.",
-        "Counter": "0,1",
         "EventCode": "0xC4",
         "EventName": "BR_INST_RETIRED.ANY",
-        "SampleAfterValue": "2000000",
-        "UMask": "0x0"
+        "SampleAfterValue": "2000000"
     },
     {
         "BriefDescription": "Retired branch instructions.",
-        "Counter": "0,1",
         "EventCode": "0xC4",
         "EventName": "BR_INST_RETIRED.ANY1",
         "SampleAfterValue": "2000000",
@@ -33,16 +28,13 @@
     },
     {
         "BriefDescription": "Retired mispredicted branch instructions (precise event).",
-        "Counter": "0,1",
         "EventCode": "0xC5",
         "EventName": "BR_INST_RETIRED.MISPRED",
         "PEBS": "1",
-        "SampleAfterValue": "200000",
-        "UMask": "0x0"
+        "SampleAfterValue": "200000"
     },
     {
         "BriefDescription": "Retired branch instructions that were mispredicted not-taken.",
-        "Counter": "0,1",
         "EventCode": "0xC4",
         "EventName": "BR_INST_RETIRED.MISPRED_NOT_TAKEN",
         "SampleAfterValue": "200000",
@@ -50,7 +42,6 @@
     },
     {
         "BriefDescription": "Retired branch instructions that were mispredicted taken.",
-        "Counter": "0,1",
         "EventCode": "0xC4",
         "EventName": "BR_INST_RETIRED.MISPRED_TAKEN",
         "SampleAfterValue": "200000",
@@ -58,7 +49,6 @@
     },
     {
         "BriefDescription": "Retired branch instructions that were predicted not-taken.",
-        "Counter": "0,1",
         "EventCode": "0xC4",
         "EventName": "BR_INST_RETIRED.PRED_NOT_TAKEN",
         "SampleAfterValue": "2000000",
@@ -66,7 +56,6 @@
     },
     {
         "BriefDescription": "Retired branch instructions that were predicted taken.",
-        "Counter": "0,1",
         "EventCode": "0xC4",
         "EventName": "BR_INST_RETIRED.PRED_TAKEN",
         "SampleAfterValue": "2000000",
@@ -74,7 +63,6 @@
     },
     {
         "BriefDescription": "Retired taken branch instructions.",
-        "Counter": "0,1",
         "EventCode": "0xC4",
         "EventName": "BR_INST_RETIRED.TAKEN",
         "SampleAfterValue": "2000000",
@@ -82,7 +70,6 @@
     },
     {
         "BriefDescription": "All macro conditional branch instructions.",
-        "Counter": "0,1",
         "EventCode": "0x88",
         "EventName": "BR_INST_TYPE_RETIRED.COND",
         "SampleAfterValue": "2000000",
@@ -90,7 +77,6 @@
     },
     {
         "BriefDescription": "Only taken macro conditional branch instructions",
-        "Counter": "0,1",
         "EventCode": "0x88",
         "EventName": "BR_INST_TYPE_RETIRED.COND_TAKEN",
         "SampleAfterValue": "2000000",
@@ -98,7 +84,6 @@
     },
     {
         "BriefDescription": "All non-indirect calls",
-        "Counter": "0,1",
         "EventCode": "0x88",
         "EventName": "BR_INST_TYPE_RETIRED.DIR_CALL",
         "SampleAfterValue": "2000000",
@@ -106,7 +91,6 @@
     },
     {
         "BriefDescription": "All indirect branches that are not calls.",
-        "Counter": "0,1",
         "EventCode": "0x88",
         "EventName": "BR_INST_TYPE_RETIRED.IND",
         "SampleAfterValue": "2000000",
@@ -114,7 +98,6 @@
     },
     {
         "BriefDescription": "All indirect calls, including both register and memory indirect.",
-        "Counter": "0,1",
         "EventCode": "0x88",
         "EventName": "BR_INST_TYPE_RETIRED.IND_CALL",
         "SampleAfterValue": "2000000",
@@ -122,7 +105,6 @@
     },
     {
         "BriefDescription": "All indirect branches that have a return mnemonic",
-        "Counter": "0,1",
         "EventCode": "0x88",
         "EventName": "BR_INST_TYPE_RETIRED.RET",
         "SampleAfterValue": "2000000",
@@ -130,7 +112,6 @@
     },
     {
         "BriefDescription": "All macro unconditional branch instructions, excluding calls and indirects",
-        "Counter": "0,1",
         "EventCode": "0x88",
         "EventName": "BR_INST_TYPE_RETIRED.UNCOND",
         "SampleAfterValue": "2000000",
@@ -138,7 +119,6 @@
     },
     {
         "BriefDescription": "Mispredicted cond branch instructions retired",
-        "Counter": "0,1",
         "EventCode": "0x89",
         "EventName": "BR_MISSP_TYPE_RETIRED.COND",
         "SampleAfterValue": "200000",
@@ -146,7 +126,6 @@
     },
     {
         "BriefDescription": "Mispredicted and taken cond branch instructions retired",
-        "Counter": "0,1",
         "EventCode": "0x89",
         "EventName": "BR_MISSP_TYPE_RETIRED.COND_TAKEN",
         "SampleAfterValue": "200000",
@@ -154,7 +133,6 @@
     },
     {
         "BriefDescription": "Mispredicted ind branches that are not calls",
-        "Counter": "0,1",
         "EventCode": "0x89",
         "EventName": "BR_MISSP_TYPE_RETIRED.IND",
         "SampleAfterValue": "200000",
@@ -162,7 +140,6 @@
     },
     {
         "BriefDescription": "Mispredicted indirect calls, including both register and memory indirect.",
-        "Counter": "0,1",
         "EventCode": "0x89",
         "EventName": "BR_MISSP_TYPE_RETIRED.IND_CALL",
         "SampleAfterValue": "200000",
@@ -170,7 +147,6 @@
     },
     {
         "BriefDescription": "Mispredicted return branches",
-        "Counter": "0,1",
         "EventCode": "0x89",
         "EventName": "BR_MISSP_TYPE_RETIRED.RETURN",
         "SampleAfterValue": "200000",
@@ -178,7 +154,6 @@
     },
     {
         "BriefDescription": "Bus cycles when core is not halted",
-        "Counter": "0,1",
         "EventCode": "0x3C",
         "EventName": "CPU_CLK_UNHALTED.BUS",
         "SampleAfterValue": "200000",
@@ -186,31 +161,24 @@
     },
     {
         "BriefDescription": "Core cycles when core is not halted",
-        "Counter": "Fixed counter 2",
         "EventCode": "0xA",
         "EventName": "CPU_CLK_UNHALTED.CORE",
-        "SampleAfterValue": "2000000",
-        "UMask": "0x0"
+        "SampleAfterValue": "2000000"
     },
     {
         "BriefDescription": "Core cycles when core is not halted",
-        "Counter": "0,1",
         "EventCode": "0x3C",
         "EventName": "CPU_CLK_UNHALTED.CORE_P",
-        "SampleAfterValue": "2000000",
-        "UMask": "0x0"
+        "SampleAfterValue": "2000000"
     },
     {
         "BriefDescription": "Reference cycles when core is not halted.",
-        "Counter": "Fixed counter 3",
         "EventCode": "0xA",
         "EventName": "CPU_CLK_UNHALTED.REF",
-        "SampleAfterValue": "2000000",
-        "UMask": "0x0"
+        "SampleAfterValue": "2000000"
     },
     {
         "BriefDescription": "Cycles the divider is busy.",
-        "Counter": "0,1",
         "EventCode": "0x14",
         "EventName": "CYCLES_DIV_BUSY",
         "SampleAfterValue": "2000000",
@@ -218,7 +186,6 @@
     },
     {
         "BriefDescription": "Divide operations retired",
-        "Counter": "0,1",
         "EventCode": "0x13",
         "EventName": "DIV.AR",
         "SampleAfterValue": "2000000",
@@ -226,7 +193,6 @@
     },
     {
         "BriefDescription": "Divide operations executed.",
-        "Counter": "0,1",
         "EventCode": "0x13",
         "EventName": "DIV.S",
         "SampleAfterValue": "2000000",
@@ -234,24 +200,19 @@
     },
     {
         "BriefDescription": "Instructions retired.",
-        "Counter": "Fixed counter 1",
         "EventCode": "0xA",
         "EventName": "INST_RETIRED.ANY",
-        "SampleAfterValue": "2000000",
-        "UMask": "0x0"
+        "SampleAfterValue": "2000000"
     },
     {
         "BriefDescription": "Instructions retired (precise event).",
-        "Counter": "0,1",
         "EventCode": "0xC0",
         "EventName": "INST_RETIRED.ANY_P",
         "PEBS": "2",
-        "SampleAfterValue": "2000000",
-        "UMask": "0x0"
+        "SampleAfterValue": "2000000"
     },
     {
         "BriefDescription": "Self-Modifying Code detected.",
-        "Counter": "0,1",
         "EventCode": "0xC3",
         "EventName": "MACHINE_CLEARS.SMC",
         "SampleAfterValue": "200000",
@@ -259,7 +220,6 @@
     },
     {
         "BriefDescription": "Multiply operations retired",
-        "Counter": "0,1",
         "EventCode": "0x12",
         "EventName": "MUL.AR",
         "SampleAfterValue": "2000000",
@@ -267,7 +227,6 @@
     },
     {
         "BriefDescription": "Multiply operations executed.",
-        "Counter": "0,1",
         "EventCode": "0x12",
         "EventName": "MUL.S",
         "SampleAfterValue": "2000000",
@@ -275,7 +234,6 @@
     },
     {
         "BriefDescription": "Micro-op reissues for any cause",
-        "Counter": "0,1",
         "EventCode": "0x3",
         "EventName": "REISSUE.ANY",
         "SampleAfterValue": "200000",
@@ -283,7 +241,6 @@
     },
     {
         "BriefDescription": "Micro-op reissues for any cause (At Retirement)",
-        "Counter": "0,1",
         "EventCode": "0x3",
         "EventName": "REISSUE.ANY.AR",
         "SampleAfterValue": "200000",
@@ -291,7 +248,6 @@
     },
     {
         "BriefDescription": "Micro-op reissues on a store-load collision",
-        "Counter": "0,1",
         "EventCode": "0x3",
         "EventName": "REISSUE.OVERLAP_STORE",
         "SampleAfterValue": "200000",
@@ -299,7 +255,6 @@
     },
     {
         "BriefDescription": "Micro-op reissues on a store-load collision (At Retirement)",
-        "Counter": "0,1",
         "EventCode": "0x3",
         "EventName": "REISSUE.OVERLAP_STORE.AR",
         "SampleAfterValue": "200000",
@@ -307,7 +262,6 @@
     },
     {
         "BriefDescription": "Cycles issue is stalled due to div busy.",
-        "Counter": "0,1",
         "EventCode": "0xDC",
         "EventName": "RESOURCE_STALLS.DIV_BUSY",
         "SampleAfterValue": "2000000",
@@ -315,7 +269,6 @@
     },
     {
         "BriefDescription": "All store forwards",
-        "Counter": "0,1",
         "EventCode": "0x2",
         "EventName": "STORE_FORWARDS.ANY",
         "SampleAfterValue": "200000",
@@ -323,7 +276,6 @@
     },
     {
         "BriefDescription": "Good store forwards",
-        "Counter": "0,1",
         "EventCode": "0x2",
         "EventName": "STORE_FORWARDS.GOOD",
         "SampleAfterValue": "200000",
@@ -331,7 +283,6 @@
     },
     {
         "BriefDescription": "Micro-ops retired.",
-        "Counter": "0,1",
         "EventCode": "0xC2",
         "EventName": "UOPS_RETIRED.ANY",
         "SampleAfterValue": "2000000",
@@ -339,7 +290,6 @@
     },
     {
         "BriefDescription": "Cycles no micro-ops retired.",
-        "Counter": "0,1",
         "EventCode": "0xC2",
         "EventName": "UOPS_RETIRED.STALLED_CYCLES",
         "SampleAfterValue": "2000000",
@@ -347,7 +297,6 @@
     },
     {
         "BriefDescription": "Periods no micro-ops retired.",
-        "Counter": "0,1",
         "EventCode": "0xC2",
         "EventName": "UOPS_RETIRED.STALLS",
         "SampleAfterValue": "2000000",
diff --git a/tools/perf/pmu-events/arch/x86/bonnell/virtual-memory.json b/tools/perf/pmu-events/arch/x86/bonnell/virtual-memory.json
index e8512c585572..82e07c73cff0 100644
--- a/tools/perf/pmu-events/arch/x86/bonnell/virtual-memory.json
+++ b/tools/perf/pmu-events/arch/x86/bonnell/virtual-memory.json
@@ -1,7 +1,6 @@
 [
     {
         "BriefDescription": "Memory accesses that missed the DTLB.",
-        "Counter": "0,1",
         "EventCode": "0x8",
         "EventName": "DATA_TLB_MISSES.DTLB_MISS",
         "SampleAfterValue": "200000",
@@ -9,7 +8,6 @@
     },
     {
         "BriefDescription": "DTLB misses due to load operations.",
-        "Counter": "0,1",
         "EventCode": "0x8",
         "EventName": "DATA_TLB_MISSES.DTLB_MISS_LD",
         "SampleAfterValue": "200000",
@@ -17,7 +15,6 @@
     },
     {
         "BriefDescription": "DTLB misses due to store operations.",
-        "Counter": "0,1",
         "EventCode": "0x8",
         "EventName": "DATA_TLB_MISSES.DTLB_MISS_ST",
         "SampleAfterValue": "200000",
@@ -25,7 +22,6 @@
     },
     {
         "BriefDescription": "L0 DTLB misses due to load operations.",
-        "Counter": "0,1",
         "EventCode": "0x8",
         "EventName": "DATA_TLB_MISSES.L0_DTLB_MISS_LD",
         "SampleAfterValue": "200000",
@@ -33,7 +29,6 @@
     },
     {
         "BriefDescription": "L0 DTLB misses due to store operations",
-        "Counter": "0,1",
         "EventCode": "0x8",
         "EventName": "DATA_TLB_MISSES.L0_DTLB_MISS_ST",
         "SampleAfterValue": "200000",
@@ -41,7 +36,6 @@
     },
     {
         "BriefDescription": "ITLB flushes.",
-        "Counter": "0,1",
         "EventCode": "0x82",
         "EventName": "ITLB.FLUSH",
         "SampleAfterValue": "200000",
@@ -49,7 +43,6 @@
     },
     {
         "BriefDescription": "ITLB hits.",
-        "Counter": "0,1",
         "EventCode": "0x82",
         "EventName": "ITLB.HIT",
         "SampleAfterValue": "200000",
@@ -57,7 +50,6 @@
     },
     {
         "BriefDescription": "ITLB misses.",
-        "Counter": "0,1",
         "EventCode": "0x82",
         "EventName": "ITLB.MISSES",
         "PEBS": "2",
@@ -66,7 +58,6 @@
     },
     {
         "BriefDescription": "Retired loads that miss the DTLB (precise event).",
-        "Counter": "0,1",
         "EventCode": "0xCB",
         "EventName": "MEM_LOAD_RETIRED.DTLB_MISS",
         "PEBS": "1",
@@ -75,7 +66,6 @@
     },
     {
         "BriefDescription": "Duration of page-walks in core cycles",
-        "Counter": "0,1",
         "EventCode": "0xC",
         "EventName": "PAGE_WALKS.CYCLES",
         "SampleAfterValue": "2000000",
@@ -83,7 +73,6 @@
     },
     {
         "BriefDescription": "Duration of D-side only page walks",
-        "Counter": "0,1",
         "EventCode": "0xC",
         "EventName": "PAGE_WALKS.D_SIDE_CYCLES",
         "SampleAfterValue": "2000000",
@@ -91,7 +80,6 @@
     },
     {
         "BriefDescription": "Number of D-side only page walks",
-        "Counter": "0,1",
         "EventCode": "0xC",
         "EventName": "PAGE_WALKS.D_SIDE_WALKS",
         "SampleAfterValue": "200000",
@@ -99,7 +87,6 @@
     },
     {
         "BriefDescription": "Duration of I-Side page walks",
-        "Counter": "0,1",
         "EventCode": "0xC",
         "EventName": "PAGE_WALKS.I_SIDE_CYCLES",
         "SampleAfterValue": "2000000",
@@ -107,7 +94,6 @@
     },
     {
         "BriefDescription": "Number of I-Side page walks",
-        "Counter": "0,1",
         "EventCode": "0xC",
         "EventName": "PAGE_WALKS.I_SIDE_WALKS",
         "SampleAfterValue": "200000",
@@ -115,7 +101,6 @@
     },
     {
         "BriefDescription": "Number of page-walks executed.",
-        "Counter": "0,1",
         "EventCode": "0xC",
         "EventName": "PAGE_WALKS.WALKS",
         "SampleAfterValue": "200000",
-- 
2.39.0.314.g84b9a713c41-goog

Re: [PATCH v1 00/32] Refresh Intel vendor events

[Liang, Kan]

On 2022-12-15 1:47 a.m., Ian Rogers wrote:
> Use new repository [1] and converter script to regenerate Intel vendor
> metrics. In particular this change removes unnecessary json fields and
> correct uncore events that previously had a buggy converter.
> 

Thanks Ian.

The patch series looks good to me.

Acked-by: Kan Liang <kan.liang@linux.intel.com>

Thanks,
Kan

> [1] https://github.com/intel/perfmon/
> 
> Ian Rogers (32):
>   perf test pmu-events: Fake PMU metric workaround
>   perf vendor events intel: Refresh alderlake metrics
>   perf vendor events intel: Refresh alderlake-n metrics
>   perf vendor events intel: Refresh bonnell events
>   perf vendor events intel: Refresh broadwell metrics and events
>   perf vendor events intel: Refresh broadwellde metrics and events
>   perf vendor events intel: Refresh broadwellx metrics and events
>   perf vendor events intel: Refresh cascadelakex metrics and events
>   perf vendor events intel: Refresh elkhartlake events
>   perf vendor events intel: Refresh goldmont events
>   perf vendor events intel: Refresh goldmontplus events
>   perf vendor events intel: Refresh haswell metrics and events
>   perf vendor events intel: Refresh haswellx metrics and events
>   perf vendor events intel: Refresh icelake metrics and events
>   perf vendor events intel: Refresh icelakex metrics and events
>   perf vendor events intel: Refresh ivybridge metrics and events
>   perf vendor events intel: Refresh ivytown metrics and events
>   perf vendor events intel: Refresh jaketown metrics and events
>   perf vendor events intel: Refresh knightslanding events
>   perf vendor events intel: Refresh meteorlake events
>   perf vendor events intel: Refresh nehalemep events
>   perf vendor events intel: Refresh nehalemex events
>   perf vendor events intel: Refresh sandybridge metrics and events
>   perf vendor events intel: Refresh sapphirerapids metrics and events
>   perf vendor events intel: Refresh silvermont events
>   perf vendor events intel: Refresh skylake metrics and events
>   perf vendor events intel: Refresh skylakex metrics and events
>   perf vendor events intel: Refresh snowridgex events
>   perf vendor events intel: Refresh tigerlake metrics and events
>   perf vendor events intel: Refresh westmereep-dp events
>   perf vendor events intel: Refresh westmereep-sp events
>   perf vendor events intel: Refresh westmereex events
> 
>  .../arch/x86/alderlake/adl-metrics.json       |   116 +-
>  .../arch/x86/alderlaken/adln-metrics.json     |    22 +-
>  .../pmu-events/arch/x86/bonnell/cache.json    |    93 -
>  .../arch/x86/bonnell/floating-point.json      |    47 +-
>  .../pmu-events/arch/x86/bonnell/frontend.json |    11 -
>  .../pmu-events/arch/x86/bonnell/memory.json   |    19 -
>  .../pmu-events/arch/x86/bonnell/other.json    |    74 +-
>  .../pmu-events/arch/x86/bonnell/pipeline.json |    65 +-
>  .../arch/x86/bonnell/virtual-memory.json      |    15 -
>  .../arch/x86/broadwell/bdw-metrics.json       |   137 +-
>  .../pmu-events/arch/x86/broadwell/cache.json  |   957 -
>  .../arch/x86/broadwell/floating-point.json    |    40 -
>  .../arch/x86/broadwell/frontend.json          |    56 -
>  .../pmu-events/arch/x86/broadwell/memory.json |   890 -
>  .../pmu-events/arch/x86/broadwell/other.json  |     8 -
>  .../arch/x86/broadwell/pipeline.json          |   272 -
>  .../arch/x86/broadwell/uncore-cache.json      |    19 -
>  .../arch/x86/broadwell/uncore-other.json      |    25 +-
>  .../arch/x86/broadwell/virtual-memory.json    |    76 -
>  .../arch/x86/broadwellde/bdwde-metrics.json   |   143 +-
>  .../arch/x86/broadwellde/cache.json           |   153 -
>  .../arch/x86/broadwellde/floating-point.json  |    40 -
>  .../arch/x86/broadwellde/frontend.json        |    56 -
>  .../arch/x86/broadwellde/memory.json          |    86 -
>  .../arch/x86/broadwellde/other.json           |     8 -
>  .../arch/x86/broadwellde/pipeline.json        |   272 -
>  .../arch/x86/broadwellde/uncore-cache.json    |   414 +-
>  .../arch/x86/broadwellde/uncore-memory.json   |   477 +-
>  .../arch/x86/broadwellde/uncore-other.json    |   163 +-
>  .../arch/x86/broadwellde/uncore-power.json    |    57 -
>  .../arch/x86/broadwellde/virtual-memory.json  |    76 -
>  .../arch/x86/broadwellx/bdx-metrics.json      |  1703 +-
>  .../pmu-events/arch/x86/broadwellx/cache.json |   191 -
>  .../arch/x86/broadwellx/floating-point.json   |    40 -
>  .../arch/x86/broadwellx/frontend.json         |    56 -
>  .../arch/x86/broadwellx/memory.json           |   143 -
>  .../pmu-events/arch/x86/broadwellx/other.json |     8 -
>  .../arch/x86/broadwellx/pipeline.json         |   272 -
>  .../arch/x86/broadwellx/uncore-cache.json     |  3740 +-
>  .../x86/broadwellx/uncore-interconnect.json   |  1225 +-
>  .../arch/x86/broadwellx/uncore-memory.json    |  2052 +-
>  .../arch/x86/broadwellx/uncore-other.json     |  2410 +-
>  .../arch/x86/broadwellx/uncore-power.json     |   198 +-
>  .../arch/x86/broadwellx/virtual-memory.json   |    76 -
>  .../arch/x86/cascadelakex/cache.json          |  3644 --
>  .../arch/x86/cascadelakex/clx-metrics.json    |  2217 +-
>  .../arch/x86/cascadelakex/floating-point.json |    24 -
>  .../arch/x86/cascadelakex/frontend.json       |   109 -
>  .../arch/x86/cascadelakex/memory.json         |  2194 -
>  .../arch/x86/cascadelakex/other.json          |   490 -
>  .../arch/x86/cascadelakex/pipeline.json       |   194 -
>  .../arch/x86/cascadelakex/uncore-memory.json  |  3185 +-
>  .../arch/x86/cascadelakex/uncore-other.json   | 29444 +++++-----
>  .../arch/x86/cascadelakex/uncore-power.json   |    45 +-
>  .../arch/x86/cascadelakex/virtual-memory.json |    56 -
>  .../arch/x86/elkhartlake/cache.json           |   252 -
>  .../arch/x86/elkhartlake/floating-point.json  |    11 -
>  .../arch/x86/elkhartlake/frontend.json        |    36 -
>  .../arch/x86/elkhartlake/memory.json          |    84 -
>  .../arch/x86/elkhartlake/other.json           |   143 -
>  .../arch/x86/elkhartlake/pipeline.json        |   213 -
>  .../arch/x86/elkhartlake/virtual-memory.json  |   117 -
>  .../pmu-events/arch/x86/goldmont/cache.json   |   288 -
>  .../arch/x86/goldmont/floating-point.json     |     6 -
>  .../arch/x86/goldmont/frontend.json           |    16 -
>  .../pmu-events/arch/x86/goldmont/memory.json  |     6 -
>  .../pmu-events/arch/x86/goldmont/other.json   |    10 -
>  .../arch/x86/goldmont/pipeline.json           |    77 -
>  .../arch/x86/goldmont/virtual-memory.json     |    14 -
>  .../arch/x86/goldmontplus/cache.json          |   470 -
>  .../arch/x86/goldmontplus/floating-point.json |    11 -
>  .../arch/x86/goldmontplus/frontend.json       |    32 -
>  .../arch/x86/goldmontplus/memory.json         |    10 -
>  .../arch/x86/goldmontplus/other.json          |    20 -
>  .../arch/x86/goldmontplus/pipeline.json       |   143 -
>  .../arch/x86/goldmontplus/virtual-memory.json |    69 -
>  .../pmu-events/arch/x86/haswell/cache.json    |   211 -
>  .../arch/x86/haswell/floating-point.json      |    20 -
>  .../pmu-events/arch/x86/haswell/frontend.json |    58 -
>  .../arch/x86/haswell/hsw-metrics.json         |   117 +-
>  .../pmu-events/arch/x86/haswell/memory.json   |   149 -
>  .../pmu-events/arch/x86/haswell/other.json    |     8 -
>  .../pmu-events/arch/x86/haswell/pipeline.json |   258 -
>  .../arch/x86/haswell/uncore-cache.json        |    50 -
>  .../arch/x86/haswell/uncore-other.json        |    21 +-
>  .../arch/x86/haswell/virtual-memory.json      |    98 -
>  .../pmu-events/arch/x86/haswellx/cache.json   |   217 -
>  .../arch/x86/haswellx/floating-point.json     |    20 -
>  .../arch/x86/haswellx/frontend.json           |    58 -
>  .../arch/x86/haswellx/hsx-metrics.json        |  1467 +-
>  .../pmu-events/arch/x86/haswellx/memory.json  |   170 -
>  .../pmu-events/arch/x86/haswellx/other.json   |     8 -
>  .../arch/x86/haswellx/pipeline.json           |   258 -
>  .../arch/x86/haswellx/uncore-cache.json       |  2448 +-
>  .../x86/haswellx/uncore-interconnect.json     |   722 +-
>  .../arch/x86/haswellx/uncore-memory.json      |  2037 +-
>  .../arch/x86/haswellx/uncore-other.json       |  1834 +-
>  .../arch/x86/haswellx/uncore-power.json       |   150 +-
>  .../arch/x86/haswellx/virtual-memory.json     |    98 -
>  .../pmu-events/arch/x86/icelake/cache.json    |   412 -
>  .../arch/x86/icelake/floating-point.json      |    28 -
>  .../pmu-events/arch/x86/icelake/frontend.json |   144 -
>  .../arch/x86/icelake/icl-metrics.json         |   151 +-
>  .../pmu-events/arch/x86/icelake/memory.json   |   171 -
>  .../pmu-events/arch/x86/icelake/other.json    |   132 -
>  .../pmu-events/arch/x86/icelake/pipeline.json |   349 +-
>  .../arch/x86/icelake/uncore-other.json        |    10 +-
>  .../arch/x86/icelake/virtual-memory.json      |    80 -
>  .../pmu-events/arch/x86/icelakex/cache.json   |   316 +-
>  .../arch/x86/icelakex/floating-point.json     |    28 -
>  .../arch/x86/icelakex/frontend.json           |   140 -
>  .../arch/x86/icelakex/icx-metrics.json        |  2192 +-
>  .../pmu-events/arch/x86/icelakex/memory.json  |   139 +-
>  .../pmu-events/arch/x86/icelakex/other.json   |   117 -
>  .../arch/x86/icelakex/pipeline.json           |   344 +-
>  .../arch/x86/icelakex/uncore-memory.json      |  1878 +-
>  .../arch/x86/icelakex/uncore-other.json       | 45144 +++++++---------
>  .../arch/x86/icelakex/uncore-power.json       |   115 +-
>  .../arch/x86/icelakex/virtual-memory.json     |    88 -
>  .../pmu-events/arch/x86/ivybridge/cache.json  |   235 -
>  .../arch/x86/ivybridge/floating-point.json    |    34 -
>  .../arch/x86/ivybridge/frontend.json          |    60 -
>  .../arch/x86/ivybridge/ivb-metrics.json       |   119 +-
>  .../pmu-events/arch/x86/ivybridge/memory.json |    54 -
>  .../pmu-events/arch/x86/ivybridge/other.json  |     8 -
>  .../arch/x86/ivybridge/pipeline.json          |   250 -
>  .../arch/x86/ivybridge/uncore-cache.json      |    50 -
>  .../arch/x86/ivybridge/uncore-other.json      |    28 +-
>  .../arch/x86/ivybridge/virtual-memory.json    |    36 -
>  .../pmu-events/arch/x86/ivytown/cache.json    |   274 -
>  .../arch/x86/ivytown/floating-point.json      |    34 -
>  .../pmu-events/arch/x86/ivytown/frontend.json |    60 -
>  .../arch/x86/ivytown/ivt-metrics.json         |   133 +-
>  .../pmu-events/arch/x86/ivytown/memory.json   |   121 -
>  .../pmu-events/arch/x86/ivytown/other.json    |     8 -
>  .../pmu-events/arch/x86/ivytown/pipeline.json |   250 -
>  .../arch/x86/ivytown/uncore-cache.json        |   388 +-
>  .../arch/x86/ivytown/uncore-interconnect.json |   505 +-
>  .../arch/x86/ivytown/uncore-memory.json       |   209 +-
>  .../arch/x86/ivytown/uncore-other.json        |   254 +-
>  .../arch/x86/ivytown/uncore-power.json        |    95 -
>  .../arch/x86/ivytown/virtual-memory.json      |    40 -
>  .../pmu-events/arch/x86/jaketown/cache.json   |   289 -
>  .../arch/x86/jaketown/floating-point.json     |    30 -
>  .../arch/x86/jaketown/frontend.json           |    64 -
>  .../arch/x86/jaketown/jkt-metrics.json        |    91 +-
>  .../pmu-events/arch/x86/jaketown/memory.json  |   103 -
>  .../pmu-events/arch/x86/jaketown/other.json   |    12 -
>  .../arch/x86/jaketown/pipeline.json           |   255 -
>  .../arch/x86/jaketown/uncore-cache.json       |   266 +-
>  .../x86/jaketown/uncore-interconnect.json     |   132 -
>  .../arch/x86/jaketown/uncore-memory.json      |    58 -
>  .../arch/x86/jaketown/uncore-other.json       |   155 +-
>  .../arch/x86/jaketown/uncore-power.json       |    51 -
>  .../arch/x86/jaketown/virtual-memory.json     |    32 -
>  .../arch/x86/knightslanding/cache.json        |   411 -
>  .../x86/knightslanding/floating-point.json    |     3 -
>  .../arch/x86/knightslanding/frontend.json     |     7 -
>  .../arch/x86/knightslanding/memory.json       |   201 -
>  .../arch/x86/knightslanding/pipeline.json     |    44 -
>  .../arch/x86/knightslanding/uncore-other.json |  1040 +-
>  .../x86/knightslanding/virtual-memory.json    |     7 -
>  tools/perf/pmu-events/arch/x86/mapfile.csv    |    14 +-
>  .../pmu-events/arch/x86/meteorlake/cache.json |   170 +-
>  .../arch/x86/meteorlake/frontend.json         |     6 -
>  .../arch/x86/meteorlake/memory.json           |    77 +-
>  .../pmu-events/arch/x86/meteorlake/other.json |    24 +-
>  .../arch/x86/meteorlake/pipeline.json         |   222 +-
>  .../arch/x86/meteorlake/virtual-memory.json   |    28 +-
>  .../pmu-events/arch/x86/nehalemep/cache.json  |   524 -
>  .../arch/x86/nehalemep/floating-point.json    |    28 -
>  .../arch/x86/nehalemep/frontend.json          |     3 -
>  .../pmu-events/arch/x86/nehalemep/memory.json |   134 -
>  .../pmu-events/arch/x86/nehalemep/other.json  |    18 -
>  .../arch/x86/nehalemep/pipeline.json          |   127 +-
>  .../arch/x86/nehalemep/virtual-memory.json    |    13 -
>  .../pmu-events/arch/x86/nehalemex/cache.json  |   519 -
>  .../arch/x86/nehalemex/floating-point.json    |    28 -
>  .../arch/x86/nehalemex/frontend.json          |     3 -
>  .../pmu-events/arch/x86/nehalemex/memory.json |   134 -
>  .../pmu-events/arch/x86/nehalemex/other.json  |    18 -
>  .../arch/x86/nehalemex/pipeline.json          |   127 +-
>  .../arch/x86/nehalemex/virtual-memory.json    |    13 -
>  .../arch/x86/sandybridge/cache.json           |   441 -
>  .../arch/x86/sandybridge/floating-point.json  |    30 -
>  .../arch/x86/sandybridge/frontend.json        |    64 -
>  .../arch/x86/sandybridge/memory.json          |   108 -
>  .../arch/x86/sandybridge/other.json           |    12 -
>  .../arch/x86/sandybridge/pipeline.json        |   257 -
>  .../arch/x86/sandybridge/snb-metrics.json     |    83 +-
>  .../arch/x86/sandybridge/uncore-cache.json    |    50 -
>  .../arch/x86/sandybridge/uncore-other.json    |    28 +-
>  .../arch/x86/sandybridge/virtual-memory.json  |    32 -
>  .../arch/x86/sapphirerapids/cache.json        |   350 +-
>  .../x86/sapphirerapids/floating-point.json    |    63 -
>  .../arch/x86/sapphirerapids/frontend.json     |   144 -
>  .../arch/x86/sapphirerapids/memory.json       |   125 +-
>  .../arch/x86/sapphirerapids/other.json        |    91 +-
>  .../arch/x86/sapphirerapids/pipeline.json     |   424 +-
>  .../arch/x86/sapphirerapids/spr-metrics.json  |  2309 +-
>  .../x86/sapphirerapids/uncore-memory.json     |   526 +-
>  .../arch/x86/sapphirerapids/uncore-other.json |  6606 +--
>  .../arch/x86/sapphirerapids/uncore-power.json |    84 +-
>  .../x86/sapphirerapids/virtual-memory.json    |    80 -
>  .../pmu-events/arch/x86/silvermont/cache.json |   133 -
>  .../arch/x86/silvermont/floating-point.json   |     1 -
>  .../arch/x86/silvermont/frontend.json         |     8 -
>  .../arch/x86/silvermont/memory.json           |     1 -
>  .../pmu-events/arch/x86/silvermont/other.json |     2 -
>  .../arch/x86/silvermont/pipeline.json         |    35 -
>  .../arch/x86/silvermont/virtual-memory.json   |     7 -
>  .../pmu-events/arch/x86/skylake/cache.json    |   660 -
>  .../arch/x86/skylake/floating-point.json      |    14 -
>  .../pmu-events/arch/x86/skylake/frontend.json |   109 -
>  .../pmu-events/arch/x86/skylake/memory.json   |   358 -
>  .../pmu-events/arch/x86/skylake/other.json    |     4 -
>  .../pmu-events/arch/x86/skylake/pipeline.json |   192 -
>  .../arch/x86/skylake/skl-metrics.json         |   155 +-
>  .../arch/x86/skylake/uncore-cache.json        |    18 -
>  .../arch/x86/skylake/uncore-other.json        |    31 +-
>  .../arch/x86/skylake/virtual-memory.json      |    56 -
>  .../pmu-events/arch/x86/skylakex/cache.json   |   368 -
>  .../arch/x86/skylakex/floating-point.json     |    18 -
>  .../arch/x86/skylakex/frontend.json           |   109 -
>  .../pmu-events/arch/x86/skylakex/memory.json  |   310 -
>  .../pmu-events/arch/x86/skylakex/other.json   |    30 -
>  .../arch/x86/skylakex/pipeline.json           |   194 -
>  .../arch/x86/skylakex/skx-metrics.json        |  2134 +-
>  .../arch/x86/skylakex/uncore-memory.json      |  2303 +-
>  .../arch/x86/skylakex/uncore-other.json       | 29356 +++++-----
>  .../arch/x86/skylakex/uncore-power.json       |    45 +-
>  .../arch/x86/skylakex/virtual-memory.json     |    56 -
>  .../pmu-events/arch/x86/snowridgex/cache.json |   252 -
>  .../arch/x86/snowridgex/floating-point.json   |    11 -
>  .../arch/x86/snowridgex/frontend.json         |    36 -
>  .../arch/x86/snowridgex/memory.json           |    84 -
>  .../pmu-events/arch/x86/snowridgex/other.json |   143 -
>  .../arch/x86/snowridgex/pipeline.json         |   213 -
>  .../arch/x86/snowridgex/uncore-memory.json    |   624 +-
>  .../arch/x86/snowridgex/uncore-other.json     | 26334 ++++-----
>  .../arch/x86/snowridgex/uncore-power.json     |   114 +-
>  .../arch/x86/snowridgex/virtual-memory.json   |   117 -
>  .../pmu-events/arch/x86/tigerlake/cache.json  |   210 +-
>  .../arch/x86/tigerlake/floating-point.json    |    27 -
>  .../arch/x86/tigerlake/frontend.json          |   125 -
>  .../pmu-events/arch/x86/tigerlake/memory.json |    77 -
>  .../pmu-events/arch/x86/tigerlake/other.json  |    13 -
>  .../arch/x86/tigerlake/pipeline.json          |   287 +-
>  .../arch/x86/tigerlake/tgl-metrics.json       |   141 +-
>  .../arch/x86/tigerlake/uncore-other.json      |    96 +-
>  .../arch/x86/tigerlake/virtual-memory.json    |    60 -
>  .../arch/x86/westmereep-dp/cache.json         |   445 -
>  .../x86/westmereep-dp/floating-point.json     |    28 -
>  .../arch/x86/westmereep-dp/frontend.json      |     3 -
>  .../arch/x86/westmereep-dp/memory.json        |   137 -
>  .../arch/x86/westmereep-dp/other.json         |    22 -
>  .../arch/x86/westmereep-dp/pipeline.json      |   129 +-
>  .../x86/westmereep-dp/virtual-memory.json     |    21 -
>  .../arch/x86/westmereep-sp/cache.json         |   517 -
>  .../x86/westmereep-sp/floating-point.json     |    28 -
>  .../arch/x86/westmereep-sp/frontend.json      |     3 -
>  .../arch/x86/westmereep-sp/memory.json        |   134 -
>  .../arch/x86/westmereep-sp/other.json         |    22 -
>  .../arch/x86/westmereep-sp/pipeline.json      |   129 +-
>  .../x86/westmereep-sp/virtual-memory.json     |    18 -
>  .../pmu-events/arch/x86/westmereex/cache.json |   516 -
>  .../arch/x86/westmereex/floating-point.json   |    28 -
>  .../arch/x86/westmereex/frontend.json         |     3 -
>  .../arch/x86/westmereex/memory.json           |   135 -
>  .../pmu-events/arch/x86/westmereex/other.json |    22 -
>  .../arch/x86/westmereex/pipeline.json         |   129 +-
>  .../arch/x86/westmereex/virtual-memory.json   |    21 -
>  tools/perf/tests/pmu-events.c                 |    17 +-
>  273 files changed, 87488 insertions(+), 124409 deletions(-)
> 

Re: [PATCH v1 00/32] Refresh Intel vendor events

[Arnaldo Carvalho de Melo]

Em Thu, Dec 15, 2022 at 12:23:14PM -0500, Liang, Kan escreveu:
> 
> 
> On 2022-12-15 1:47 a.m., Ian Rogers wrote:
> > Use new repository [1] and converter script to regenerate Intel vendor
> > metrics. In particular this change removes unnecessary json fields and
> > correct uncore events that previously had a buggy converter.
> > 
> 
> Thanks Ian.
> 
> The patch series looks good to me.
> 
> Acked-by: Kan Liang <kan.liang@linux.intel.com>

b4 doesn't like it, I'll apply it manually, probably some went over
message size limits?

- Arnaldo

⬢[acme@toolbox perf]$ b4 am -ctsl --cc-trailers bbbe8cb7-bc12-537f-0977-e96ab7cf3cfa@linux.intel.com
Grabbing thread from lore.kernel.org/all/bbbe8cb7-bc12-537f-0977-e96ab7cf3cfa%40linux.intel.com/t.mbox.gz
Checking for newer revisions
Grabbing search results from lore.kernel.org
Analyzing 7 messages in the thread
Checking attestation on all messages, may take a moment...
---
  ✓ [PATCH v1 1/32] perf test pmu-events: Fake PMU metric workaround
    ✓ Signed: DKIM/google.com
    + Acked-by: Kan Liang <kan.liang@linux.intel.com> (✓ DKIM/intel.com)
    + Link: https://lore.kernel.org/r/20221215064755.1620246-2-irogers@google.com
    + Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com>
  ✓ [PATCH v1 2/32] perf vendor events intel: Refresh alderlake metrics
    ✓ Signed: DKIM/google.com
    + Acked-by: Kan Liang <kan.liang@linux.intel.com> (✓ DKIM/intel.com)
    + Link: https://lore.kernel.org/r/20221215064755.1620246-3-irogers@google.com
    + Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com>
  ✓ [PATCH v1 3/32] perf vendor events intel: Refresh alderlake-n metrics
    ✓ Signed: DKIM/google.com
    + Acked-by: Kan Liang <kan.liang@linux.intel.com> (✓ DKIM/intel.com)
    + Link: https://lore.kernel.org/r/20221215064755.1620246-4-irogers@google.com
    + Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com>
  ✓ [PATCH v1 4/32] perf vendor events intel: Refresh bonnell events
    ✓ Signed: DKIM/google.com
    + Acked-by: Kan Liang <kan.liang@linux.intel.com> (✓ DKIM/intel.com)
    + Link: https://lore.kernel.org/r/20221215064755.1620246-5-irogers@google.com
    + Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com>
  ✓ [PATCH v1 5/32] perf vendor events intel: Refresh broadwell metrics and events
    ✓ Signed: DKIM/google.com
    + Acked-by: Kan Liang <kan.liang@linux.intel.com> (✓ DKIM/intel.com)
    + Link: https://lore.kernel.org/r/20221215064755.1620246-6-irogers@google.com
    + Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com>
  ERROR: missing [6/32]!
  ERROR: missing [7/32]!
  ERROR: missing [8/32]!
  ERROR: missing [9/32]!
  ERROR: missing [10/32]!
  ERROR: missing [11/32]!
  ERROR: missing [12/32]!

Re: [PATCH v1 00/32] Refresh Intel vendor events

[Arnaldo Carvalho de Melo]

Em Wed, Dec 21, 2022 at 01:31:11PM -0300, Arnaldo Carvalho de Melo escreveu:
> Em Thu, Dec 15, 2022 at 12:23:14PM -0500, Liang, Kan escreveu:
> > On 2022-12-15 1:47 a.m., Ian Rogers wrote:
> > > Use new repository [1] and converter script to regenerate Intel vendor
> > > metrics. In particular this change removes unnecessary json fields and
> > > correct uncore events that previously had a buggy converter.

> > Thanks Ian.

> > The patch series looks good to me.

> > Acked-by: Kan Liang <kan.liang@linux.intel.com>

> b4 doesn't like it, I'll apply it manually, probably some went over
> message size limits?

Had to adjust the first one manually due, IIRC, to the hashmap changes
that went upstream via the bpf tree, then use b4 3 times, cherrypicking
ranges of the series to get all merged.

Ian, please check what happened so that this isn't this manual next
time.

- Arnaldo