From: "Mi, Dapeng" <dapeng1.mi@linux.intel.com>
To: Peter Zijlstra <peterz@infradead.org>
Cc: Ingo Molnar <mingo@redhat.com>,
Arnaldo Carvalho de Melo <acme@kernel.org>,
Namhyung Kim <namhyung@kernel.org>,
Ian Rogers <irogers@google.com>,
Adrian Hunter <adrian.hunter@intel.com>,
Alexander Shishkin <alexander.shishkin@linux.intel.com>,
Andi Kleen <ak@linux.intel.com>,
Eranian Stephane <eranian@google.com>,
linux-kernel@vger.kernel.org, linux-perf-users@vger.kernel.org,
Dapeng Mi <dapeng1.mi@intel.com>, Zide Chen <zide.chen@intel.com>,
Falcon Thomas <thomas.falcon@intel.com>,
Xudong Hao <xudong.hao@intel.com>
Subject: Re: [Patch v2 3/7] perf/x86/intel: Add core PMU support for DMR
Date: Tue, 13 Jan 2026 09:59:26 +0800 [thread overview]
Message-ID: <c08e5eeb-2949-4a13-951d-b7ae39d1e062@linux.intel.com> (raw)
In-Reply-To: <20260112104131.GF830755@noisy.programming.kicks-ass.net>
On 1/12/2026 6:41 PM, Peter Zijlstra wrote:
> On Mon, Jan 12, 2026 at 01:16:45PM +0800, Dapeng Mi wrote:
>> @@ -7906,6 +8072,22 @@ __init int intel_pmu_init(void)
>> intel_pmu_pebs_data_source_skl(true);
>> break;
>>
>> + case INTEL_DIAMONDRAPIDS_X:
>> + intel_pmu_init_pnc(NULL);
>> + x86_pmu.pebs_ept = 1;
>> + x86_pmu.hw_config = hsw_hw_config;
>> + x86_pmu.pebs_latency_data = pnc_latency_data;
>> + x86_pmu.get_event_constraints = glc_get_event_constraints;
>> + extra_attr = boot_cpu_has(X86_FEATURE_RTM) ?
>> + hsw_format_attr : nhm_format_attr;
>> + extra_skl_attr = skl_format_attr;
>> + mem_attr = glc_events_attrs;
>> + td_attr = glc_td_events_attrs;
>> + tsx_attr = glc_tsx_events_attrs;
>> + pr_cont("Panthercove events, ");
>> + name = "panthercove";
>> + break;
>> +
>> case INTEL_ALDERLAKE:
>> case INTEL_ALDERLAKE_L:
>> case INTEL_RAPTORLAKE:
> Does something like so make sense?
>
>
> --- a/arch/x86/events/intel/core.c
> +++ b/arch/x86/events/intel/core.c
> @@ -8066,6 +8066,9 @@ __init int intel_pmu_init(void)
>
> glc_common:
> intel_pmu_init_glc(NULL);
> + intel_pmu_pebs_data_source_skl(true);
> +
> + glc_base:
> x86_pmu.pebs_ept = 1;
> x86_pmu.hw_config = hsw_hw_config;
> x86_pmu.get_event_constraints = glc_get_event_constraints;
> @@ -8075,24 +8078,14 @@ __init int intel_pmu_init(void)
> mem_attr = glc_events_attrs;
> td_attr = glc_td_events_attrs;
> tsx_attr = glc_tsx_events_attrs;
> - intel_pmu_pebs_data_source_skl(true);
> break;
>
> case INTEL_DIAMONDRAPIDS_X:
> - intel_pmu_init_pnc(NULL);
> - x86_pmu.pebs_ept = 1;
> - x86_pmu.hw_config = hsw_hw_config;
> - x86_pmu.pebs_latency_data = pnc_latency_data;
> - x86_pmu.get_event_constraints = glc_get_event_constraints;
> - extra_attr = boot_cpu_has(X86_FEATURE_RTM) ?
> - hsw_format_attr : nhm_format_attr;
> - extra_skl_attr = skl_format_attr;
> - mem_attr = glc_events_attrs;
> - td_attr = glc_td_events_attrs;
> - tsx_attr = glc_tsx_events_attrs;
> pr_cont("Panthercove events, ");
> name = "panthercove";
> - break;
> + intel_pmu_init_pnc(NULL);
> + x86_pmu.pebs_latency_data = pnc_latency_data;
> + goto glc_base;
>
> case INTEL_ALDERLAKE:
> case INTEL_ALDERLAKE_L:
Yes, that looks better, but "goto behind" seems a little weird, I tweak the
code a little bit. Thanks.
diff --git a/arch/x86/events/intel/core.c b/arch/x86/events/intel/core.c
index 77cf849a1381..85134d80d9fc 100644
--- a/arch/x86/events/intel/core.c
+++ b/arch/x86/events/intel/core.c
@@ -8155,26 +8155,23 @@ __init int intel_pmu_init(void)
x86_pmu.extra_regs = intel_rwc_extra_regs;
pr_cont("Granite Rapids events, ");
name = "granite_rapids";
+ goto glc_common;
+
+ case INTEL_DIAMONDRAPIDS_X:
+ intel_pmu_init_pnc(NULL);
+ x86_pmu.pebs_latency_data = pnc_latency_data;
+
+ pr_cont("Panthercove events, ");
+ name = "panthercove";
+ goto glc_base;
glc_common:
intel_pmu_init_glc(NULL);
- x86_pmu.pebs_ept = 1;
- x86_pmu.hw_config = hsw_hw_config;
- x86_pmu.get_event_constraints = glc_get_event_constraints;
- extra_attr = boot_cpu_has(X86_FEATURE_RTM) ?
- hsw_format_attr : nhm_format_attr;
- extra_skl_attr = skl_format_attr;
- mem_attr = glc_events_attrs;
- td_attr = glc_td_events_attrs;
- tsx_attr = glc_tsx_events_attrs;
intel_pmu_pebs_data_source_skl(true);
- break;
- case INTEL_DIAMONDRAPIDS_X:
- intel_pmu_init_pnc(NULL);
+ glc_base:
x86_pmu.pebs_ept = 1;
x86_pmu.hw_config = hsw_hw_config;
- x86_pmu.pebs_latency_data = pnc_latency_data;
x86_pmu.get_event_constraints = glc_get_event_constraints;
extra_attr = boot_cpu_has(X86_FEATURE_RTM) ?
hsw_format_attr : nhm_format_attr;
@@ -8182,8 +8179,6 @@ __init int intel_pmu_init(void)
mem_attr = glc_events_attrs;
td_attr = glc_td_events_attrs;
tsx_attr = glc_tsx_events_attrs;
- pr_cont("Panthercove events, ");
- name = "panthercove";
next prev parent reply other threads:[~2026-01-13 1:59 UTC|newest]
Thread overview: 19+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-01-12 5:16 [Patch v2 0/7] Enable core PMU for DMR and NVL Dapeng Mi
2026-01-12 5:16 ` [Patch v2 1/7] perf/x86/intel: Support the 4 new OMR MSRs introduced in " Dapeng Mi
2026-01-12 10:27 ` Peter Zijlstra
2026-01-13 1:22 ` Mi, Dapeng
2026-01-12 5:16 ` [Patch v2 2/7] perf/x86/intel: Add support for PEBS memory auxiliary info field in DMR Dapeng Mi
2026-01-12 5:16 ` [Patch v2 3/7] perf/x86/intel: Add core PMU support for DMR Dapeng Mi
2026-01-12 10:41 ` Peter Zijlstra
2026-01-13 1:59 ` Mi, Dapeng [this message]
2026-01-12 5:16 ` [Patch v2 4/7] perf/x86/intel: Add support for PEBS memory auxiliary info field in NVL Dapeng Mi
2026-01-12 5:16 ` [Patch v2 5/7] perf/x86/intel: Add core PMU support for Novalake Dapeng Mi
2026-01-12 5:16 ` [Patch v2 6/7] perf/x86: Use macros to replace magic numbers in attr_rdpmc Dapeng Mi
2026-01-12 5:16 ` [Patch v2 7/7] perf/x86/intel: Add support for rdpmc user disable feature Dapeng Mi
2026-01-12 10:57 ` Peter Zijlstra
2026-01-13 2:29 ` Mi, Dapeng
2026-01-13 10:51 ` Peter Zijlstra
2026-01-13 1:49 ` Ian Rogers
2026-01-13 2:49 ` Mi, Dapeng
2026-03-10 0:04 ` Ian Rogers
2026-03-10 5:28 ` Mi, Dapeng
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