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Dadhania" , "Manali Shukla" , Ravi Bangoria , "Ananth Narayan" , Sandipan Das Subject: [RFC PATCH 0/7] KVM: SVM: Support for PMC virtualization Date: Thu, 13 Nov 2025 11:48:20 +0530 Message-ID: X-Mailer: git-send-email 2.43.0 Precedence: bulk X-Mailing-List: linux-perf-users@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: 8bit X-ClientProxiedBy: satlexmb07.amd.com (10.181.42.216) To satlexmb07.amd.com (10.181.42.216) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CY4PEPF0000FCC3:EE_|LV3PR12MB9215:EE_ X-MS-Office365-Filtering-Correlation-Id: 774fdad7-3c9b-46c5-e807-08de227c7d39 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|82310400026|1800799024|36860700013|376014|13003099007; X-Microsoft-Antispam-Message-Info: =?utf-8?B?UnZjZkFrekRCTGV4TWRVU3JXRTJPbUhSa0o5WktKUjB3aXl1NnlHR3hGVlJO?= =?utf-8?B?UW54ZEplL3JuNE50N09uTWN6V3dBSVBYWGNkM3FtSVZsTUZwUHI0bFpiV0g2?= =?utf-8?B?MzRvUEcrcEhzYnNENC9YMG1tTWJRbG5jdWpWcUpaaklHVnoyektvRmVEN0dp?= =?utf-8?B?VDRXckwzQWpJMEwxU2dPTFpsRFFiODlNRlZsbkNzZ2M3TFFPNC9IRTFpN1k3?= =?utf-8?B?NUxlV0FObHRMVnZwa2IwVEx5UGVmNEdZMGEwWXZRRnhiQ0YxaFc4NlFPQzFj?= =?utf-8?B?cEFhL0JsUEo2M1pHdGRvRWZucElnb2Y3WWRpYmRkZDIzelZmS1hlVCt5Y2Fy?= =?utf-8?B?WUpkRmFwMHhNZGU2WUpVaStqL1NFTFRQK0NqTzZnWTlpendqSXplTS94am81?= =?utf-8?B?VE52MDErZ0hyZHhoMjhzWjlxQzhmZXpxM0VwTEZTelRYZUxDMzY3RWFabXpN?= =?utf-8?B?MFRwQjJPT1RHdVc4aWNNbkdqNVNkOEh6YVdEcFlJYlY1bXVVZVBHNmxzdlRE?= =?utf-8?B?dVhBczRBd05rSkdnR2I2UlJueDlwV3RUZE1WY2FicHpoV205cXJxbGpJd1dB?= =?utf-8?B?RHV5c1Q2WksvZnhYazlWQitSRlA2WHdvTTgzMmp4UWJVR3NKN2NPR0Y1U1Zt?= =?utf-8?B?WldYZXFiVW11YUk4eXdlT1Z2UVYyeW9nM0hFc0NPUThSVDRNd1lZWXlUV21V?= =?utf-8?B?UngvWHp1Y1ZKT0NYM2lGdjNZTkFmNTh5RzdLK0ZPb0JWM2pRVHFOTURyVlVx?= =?utf-8?B?SU9JTnFXRmV3TlpRWGlMblpCZndoY2MzY1RQR3VvOVR4cDF4bUhJU1F3Rkpi?= =?utf-8?B?bW5PUjhWMk1WTkptYmZWMThDVXNySlV6UWsxN2E1RWlOYzk3TWVsU0dWTFlD?= =?utf-8?B?ci9mZE0vbStLY3FYOVVTREFLbzJtb0Vrc0VvM1VPNkVISmlldkl4ODBWendB?= =?utf-8?B?RWgvdGQ0aDkwZGw2UTNvVW16WDdCNVZNVGZXTDJDNUVaNHZxckpvU0tEL01R?= =?utf-8?B?bnFEdTdtRktVREVTVkNEZkFZSmdZeUVuYXZEQ0J3NHRhR3NIMEZERTRGcGhK?= =?utf-8?B?VzFXRjZlR2l6Mk81V3daeE1DNHlpMUhJL3hrZFBrdVZRSEVqWTMvRGliRXgx?= =?utf-8?B?TmpzdW5XUUQ2Vm9SaUxDb25HV2FsbDAwL0tJT3U2eTVhZjFWa2NEaFVEWUtK?= =?utf-8?B?RFVUTG1CQUhnZ3RmVDVXTGFyNkZ6YlplL1Znc25UcUQzamp0ZVp1WTBWTU13?= =?utf-8?B?NmxGY0w0UkUxMk52OFlqc0oweStYcjUwUmZRenJyaFdRZHRncTVjZnZhbEE4?= =?utf-8?B?VTZVV1BNZHBkb1lrd0hLNVdPSEFhSHEyVUlJeFZlaE05dTlHUXZoRHBRTmdy?= =?utf-8?B?clBqRmV3MUJQd3BnSW10MjY4aGFUbXlSVzJTWEJ2bnpIbGdUZWZ3bzM1emtk?= =?utf-8?B?ZkJWTFBrVmVYQ0tCVXlwckFyOEc5QklUWm9OWEYrS3J5RWRvN3ZwZm9LV1Rp?= =?utf-8?B?c1l2cDkvZmM4U0NtZXU1Z0h4RkFjcFVhREEveVJqMTR2MC9hTlBMT2gyRHk0?= =?utf-8?B?NGExbmVubnNNRGFrdlVHbU9oLzMwRzZVL3JtQVRIanM1cnhCdmRxYWhXVElD?= =?utf-8?B?Z043cTYvejViNWVYT1pyR3U0ZkZNWmtTQXJJa3o1Q0tBMmo1eGxrcGNQMklw?= =?utf-8?B?RlRCNmd1dFU1VnJDNS9UNzFwaEtrOGtnZnNtelJaSkVMMlBhZFZ4Y3NsOXY4?= =?utf-8?B?WnhySG15RUptRm1ZUGFEaGVMdmRvYkRRTnBIaDhabXM5QUt2VWN6dG5JcWhM?= =?utf-8?B?NlZycDZJTngrV1hmWmhUSFFlcGs2blgzeE14ZWxWOU5zZm1kSW5FS0RuUVNZ?= =?utf-8?B?Y1hxSXJyZ3JvdUJuRmJuazhLenA3bWNqUjFEYUY4MmFCbW1lQnJuNnNFblpl?= =?utf-8?B?bmYvWEpaTDlmSTJNVm1wY29WMGNBZTNseGpnVjVWemoxU2N2VjNFckxmcHhr?= =?utf-8?B?L1RCVC9OR2FqOWZ2NzZ1bVZxTENQNmpMN1Z1V2VpSlMwOGJOdVdvOGQ3N1Qz?= =?utf-8?Q?aTvlwS?= X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:satlexmb07.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230040)(82310400026)(1800799024)(36860700013)(376014)(13003099007);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 13 Nov 2025 06:18:40.4538 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 774fdad7-3c9b-46c5-e807-08de227c7d39 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[satlexmb07.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CY4PEPF0000FCC3.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: LV3PR12MB9215 AMD Zen 5 processors introduced PMC virtualization. When the feature is enabled, hardware can restore and save the guest PMU state at VM-Entry and VM-Exit respectively. The host PMU state still needs to be managed by software and this is done with the help of the Mediated PMU framework which can schedule the host perf events in or out. This feature is documented under Section 15.39 in Volume 2 of the AMD64 Architecture Programmer’s Manual which can be found below. https://bugzilla.kernel.org/attachment.cgi?id=306250 The guest PMU state is saved in the VMCB. Hence, struct kvm_pmu goes out of sync and does not have the latest PMU state. In some cases, such as during event filtering or instruction emulation, the VMCB needs to be accessed for reading or writing the current register state. This is done using host-initiated MSR accesses but the method may not be ideal and perhaps requires additional PMU ops to be introduced. The goal is to have data in vendor-specific structures like VMCB functions accessible to some of the common KVM x86 PMU functions. Any feedback is appreciated. Patch Summary * The first three patches add new feature bits and capability flags to detect and advertise support for hardware PMU virtualization. * The fourth patch extends Mediated PMU to make use of hardware PMU virtualization. * The remaining patches add the vendor-specific changes for PMC virtualization. TODOs * Add appropriate KVM PMU ops to access MSR states from the VMCB. * Make MSR states in the VMCB accessible via KVM_{GET,SET}_MSRS. * Support for SEV-ES and SEV-SNP guests. * Support for nested guests (nSVM). * Support for the IRPerfCount register which is a free-running instructions retired counter. Testing * Used three different guest PMU configurations. * PerfMonV2 capable - 6 counters with Global Control and Status registers (Zen 4 and later). * PerfCtrExtCore capable - 6 counters but no Global Control and Status registers (Zen 3 and older). * Legacy Guest - 4 counters only (pre-Zen, older than Family 15h). * KVM Unit Tests passed. * Perf Fuzzer passed. The patches should be applied over v5 of the Mediated PMU series [1] along with an RDPMC interception fix [2]. [1] https://lore.kernel.org/all/20250806195706.1650976-1-seanjc@google.com/ [2] https://lore.kernel.org/all/aN1vfykNs8Dmv_g0@google.com/ Sandipan Das (7): perf: Add a capability for hardware virtualized PMUs x86/cpufeatures: Add PerfCtrVirt feature bit perf/x86/amd/core: Set PERF_PMU_CAP_VIRTUALIZED_VPMU KVM: x86/pmu: Add support for hardware virtualized PMUs KVM: SVM: Add VMCB fields for PMC virtualization KVM: SVM: Add support for PMC virtualization KVM: SVM: Adjust MSR index for legacy guests arch/x86/events/amd/core.c | 3 + arch/x86/events/core.c | 1 + arch/x86/include/asm/cpufeatures.h | 1 + arch/x86/include/asm/perf_event.h | 1 + arch/x86/include/asm/svm.h | 12 ++- arch/x86/kvm/pmu.c | 94 ++++++++++++++++++----- arch/x86/kvm/pmu.h | 6 ++ arch/x86/kvm/svm/pmu.c | 115 +++++++++++++++++++++++++++++ arch/x86/kvm/svm/svm.c | 52 +++++++++++++ arch/x86/kvm/svm/svm.h | 1 + arch/x86/kvm/vmx/pmu_intel.c | 1 + arch/x86/kvm/x86.c | 4 + arch/x86/kvm/x86.h | 1 + include/linux/perf_event.h | 1 + 14 files changed, 273 insertions(+), 20 deletions(-) -- 2.43.0