Re: [PATCH] x86/events/intel/cstate: Add Pantherlake support

["Mi, Dapeng" <dapeng1.mi@linux.intel.com>]

Hi Kaushlendra,

The PTL cstate enabling patch had been merged into tip perf/core branch. :)

Thanks,

- Dapeng

On 11/12/2025 5:00 PM, Kaushlendra Kumar wrote:
> It supports the same C-state residency counters as Lunarlake.This
> enables monitoring of C1, C6, C7 core states and C2,C3,C6,C10
> package states residency counters on Pantherlake platforms.
>
> Signed-off-by: Kaushlendra Kumar <kaushlendra.kumar@intel.com>
> ---
>  arch/x86/events/intel/cstate.c | 16 +++++++++-------
>  1 file changed, 9 insertions(+), 7 deletions(-)
>
> diff --git a/arch/x86/events/intel/cstate.c b/arch/x86/events/intel/cstate.c
> index ec753e39b007..b3582eeb6c4b 100644
> --- a/arch/x86/events/intel/cstate.c
> +++ b/arch/x86/events/intel/cstate.c
> @@ -41,7 +41,7 @@
>   *	MSR_CORE_C1_RES: CORE C1 Residency Counter
>   *			 perf code: 0x00
>   *			 Available model: SLM,AMT,GLM,CNL,ICX,TNT,ADL,RPL
> - *					  MTL,SRF,GRR,ARL,LNL
> + *					  MTL,SRF,GRR,ARL,LNL,PTL
>   *			 Scope: Core (each processor core has a MSR)
>   *	MSR_CORE_C3_RESIDENCY: CORE C3 Residency Counter
>   *			       perf code: 0x01
> @@ -53,31 +53,32 @@
>   *			       Available model: SLM,AMT,NHM,WSM,SNB,IVB,HSW,BDW,
>   *						SKL,KNL,GLM,CNL,KBL,CML,ICL,ICX,
>   *						TGL,TNT,RKL,ADL,RPL,SPR,MTL,SRF,
> - *						GRR,ARL,LNL
> + *						GRR,ARL,LNL,PTL
>   *			       Scope: Core
>   *	MSR_CORE_C7_RESIDENCY: CORE C7 Residency Counter
>   *			       perf code: 0x03
>   *			       Available model: SNB,IVB,HSW,BDW,SKL,CNL,KBL,CML,
> - *						ICL,TGL,RKL,ADL,RPL,MTL,ARL,LNL
> + *						ICL,TGL,RKL,ADL,RPL,MTL,ARL,LNL,
> + *						PTL
>   *			       Scope: Core
>   *	MSR_PKG_C2_RESIDENCY:  Package C2 Residency Counter.
>   *			       perf code: 0x00
>   *			       Available model: SNB,IVB,HSW,BDW,SKL,KNL,GLM,CNL,
>   *						KBL,CML,ICL,ICX,TGL,TNT,RKL,ADL,
> - *						RPL,SPR,MTL,ARL,LNL,SRF
> + *						RPL,SPR,MTL,ARL,LNL,SRF,PTL
>   *			       Scope: Package (physical package)
>   *	MSR_PKG_C3_RESIDENCY:  Package C3 Residency Counter.
>   *			       perf code: 0x01
>   *			       Available model: NHM,WSM,SNB,IVB,HSW,BDW,SKL,KNL,
>   *						GLM,CNL,KBL,CML,ICL,TGL,TNT,RKL,
> - *						ADL,RPL,MTL,ARL,LNL
> + *						ADL,RPL,MTL,ARL,LNL,PTL
>   *			       Scope: Package (physical package)
>   *	MSR_PKG_C6_RESIDENCY:  Package C6 Residency Counter.
>   *			       perf code: 0x02
>   *			       Available model: SLM,AMT,NHM,WSM,SNB,IVB,HSW,BDW,
>   *						SKL,KNL,GLM,CNL,KBL,CML,ICL,ICX,
>   *						TGL,TNT,RKL,ADL,RPL,SPR,MTL,SRF,
> - *						ARL,LNL
> + *						ARL,LNL,PTL
>   *			       Scope: Package (physical package)
>   *	MSR_PKG_C7_RESIDENCY:  Package C7 Residency Counter.
>   *			       perf code: 0x03
> @@ -96,7 +97,7 @@
>   *	MSR_PKG_C10_RESIDENCY: Package C10 Residency Counter.
>   *			       perf code: 0x06
>   *			       Available model: HSW ULT,KBL,GLM,CNL,CML,ICL,TGL,
> - *						TNT,RKL,ADL,RPL,MTL,ARL,LNL
> + *						TNT,RKL,ADL,RPL,MTL,ARL,LNL,PTL
>   *			       Scope: Package (physical package)
>   *	MSR_MODULE_C6_RES_MS:  Module C6 Residency Counter.
>   *			       perf code: 0x00
> @@ -652,6 +653,7 @@ static const struct x86_cpu_id intel_cstates_match[] __initconst = {
>  	X86_MATCH_VFM(INTEL_ARROWLAKE_H,	&adl_cstates),
>  	X86_MATCH_VFM(INTEL_ARROWLAKE_U,	&adl_cstates),
>  	X86_MATCH_VFM(INTEL_LUNARLAKE_M,	&lnl_cstates),
> +	X86_MATCH_VFM(INTEL_PANTHERLAKE_L,	&lnl_cstates),
>  	{ },
>  };
>  MODULE_DEVICE_TABLE(x86cpu, intel_cstates_match);