* [PATCH] x86/events/intel/cstate: Add Pantherlake support
@ 2025-11-12 9:00 Kaushlendra Kumar
2025-11-12 20:07 ` Dave Hansen
2025-11-13 6:50 ` Mi, Dapeng
0 siblings, 2 replies; 6+ messages in thread
From: Kaushlendra Kumar @ 2025-11-12 9:00 UTC (permalink / raw)
To: mingo, acme, namhyung, jolsa, adrian.hunter, bp, dave.hansen, x86
Cc: linux-perf-users, linux-kernel, Kaushlendra Kumar
It supports the same C-state residency counters as Lunarlake.This
enables monitoring of C1, C6, C7 core states and C2,C3,C6,C10
package states residency counters on Pantherlake platforms.
Signed-off-by: Kaushlendra Kumar <kaushlendra.kumar@intel.com>
---
arch/x86/events/intel/cstate.c | 16 +++++++++-------
1 file changed, 9 insertions(+), 7 deletions(-)
diff --git a/arch/x86/events/intel/cstate.c b/arch/x86/events/intel/cstate.c
index ec753e39b007..b3582eeb6c4b 100644
--- a/arch/x86/events/intel/cstate.c
+++ b/arch/x86/events/intel/cstate.c
@@ -41,7 +41,7 @@
* MSR_CORE_C1_RES: CORE C1 Residency Counter
* perf code: 0x00
* Available model: SLM,AMT,GLM,CNL,ICX,TNT,ADL,RPL
- * MTL,SRF,GRR,ARL,LNL
+ * MTL,SRF,GRR,ARL,LNL,PTL
* Scope: Core (each processor core has a MSR)
* MSR_CORE_C3_RESIDENCY: CORE C3 Residency Counter
* perf code: 0x01
@@ -53,31 +53,32 @@
* Available model: SLM,AMT,NHM,WSM,SNB,IVB,HSW,BDW,
* SKL,KNL,GLM,CNL,KBL,CML,ICL,ICX,
* TGL,TNT,RKL,ADL,RPL,SPR,MTL,SRF,
- * GRR,ARL,LNL
+ * GRR,ARL,LNL,PTL
* Scope: Core
* MSR_CORE_C7_RESIDENCY: CORE C7 Residency Counter
* perf code: 0x03
* Available model: SNB,IVB,HSW,BDW,SKL,CNL,KBL,CML,
- * ICL,TGL,RKL,ADL,RPL,MTL,ARL,LNL
+ * ICL,TGL,RKL,ADL,RPL,MTL,ARL,LNL,
+ * PTL
* Scope: Core
* MSR_PKG_C2_RESIDENCY: Package C2 Residency Counter.
* perf code: 0x00
* Available model: SNB,IVB,HSW,BDW,SKL,KNL,GLM,CNL,
* KBL,CML,ICL,ICX,TGL,TNT,RKL,ADL,
- * RPL,SPR,MTL,ARL,LNL,SRF
+ * RPL,SPR,MTL,ARL,LNL,SRF,PTL
* Scope: Package (physical package)
* MSR_PKG_C3_RESIDENCY: Package C3 Residency Counter.
* perf code: 0x01
* Available model: NHM,WSM,SNB,IVB,HSW,BDW,SKL,KNL,
* GLM,CNL,KBL,CML,ICL,TGL,TNT,RKL,
- * ADL,RPL,MTL,ARL,LNL
+ * ADL,RPL,MTL,ARL,LNL,PTL
* Scope: Package (physical package)
* MSR_PKG_C6_RESIDENCY: Package C6 Residency Counter.
* perf code: 0x02
* Available model: SLM,AMT,NHM,WSM,SNB,IVB,HSW,BDW,
* SKL,KNL,GLM,CNL,KBL,CML,ICL,ICX,
* TGL,TNT,RKL,ADL,RPL,SPR,MTL,SRF,
- * ARL,LNL
+ * ARL,LNL,PTL
* Scope: Package (physical package)
* MSR_PKG_C7_RESIDENCY: Package C7 Residency Counter.
* perf code: 0x03
@@ -96,7 +97,7 @@
* MSR_PKG_C10_RESIDENCY: Package C10 Residency Counter.
* perf code: 0x06
* Available model: HSW ULT,KBL,GLM,CNL,CML,ICL,TGL,
- * TNT,RKL,ADL,RPL,MTL,ARL,LNL
+ * TNT,RKL,ADL,RPL,MTL,ARL,LNL,PTL
* Scope: Package (physical package)
* MSR_MODULE_C6_RES_MS: Module C6 Residency Counter.
* perf code: 0x00
@@ -652,6 +653,7 @@ static const struct x86_cpu_id intel_cstates_match[] __initconst = {
X86_MATCH_VFM(INTEL_ARROWLAKE_H, &adl_cstates),
X86_MATCH_VFM(INTEL_ARROWLAKE_U, &adl_cstates),
X86_MATCH_VFM(INTEL_LUNARLAKE_M, &lnl_cstates),
+ X86_MATCH_VFM(INTEL_PANTHERLAKE_L, &lnl_cstates),
{ },
};
MODULE_DEVICE_TABLE(x86cpu, intel_cstates_match);
--
2.34.1
^ permalink raw reply related [flat|nested] 6+ messages in thread
* Re: [PATCH] x86/events/intel/cstate: Add Pantherlake support
2025-11-12 9:00 [PATCH] x86/events/intel/cstate: Add Pantherlake support Kaushlendra Kumar
@ 2025-11-12 20:07 ` Dave Hansen
2025-11-13 4:05 ` Kumar, Kaushlendra
2025-11-13 6:50 ` Mi, Dapeng
1 sibling, 1 reply; 6+ messages in thread
From: Dave Hansen @ 2025-11-12 20:07 UTC (permalink / raw)
To: Kaushlendra Kumar, mingo, acme, namhyung, jolsa, adrian.hunter,
bp, dave.hansen, x86
Cc: linux-perf-users, linux-kernel
On 11/12/25 01:00, Kaushlendra Kumar wrote:
> It supports the same C-state residency counters as Lunarlake.This
> enables monitoring of C1, C6, C7 core states and C2,C3,C6,C10
> package states residency counters on Pantherlake platforms.
Is this actually documented? Or is there just a smoke-filled room at
Intel somewhere where this is decided?
> diff --git a/arch/x86/events/intel/cstate.c b/arch/x86/events/intel/cstate.c
> index ec753e39b007..b3582eeb6c4b 100644
> --- a/arch/x86/events/intel/cstate.c
> +++ b/arch/x86/events/intel/cstate.c
> @@ -41,7 +41,7 @@
> * MSR_CORE_C1_RES: CORE C1 Residency Counter
> * perf code: 0x00
> * Available model: SLM,AMT,GLM,CNL,ICX,TNT,ADL,RPL
> - * MTL,SRF,GRR,ARL,LNL
> + * MTL,SRF,GRR,ARL,LNL,PTL
Could we get rid of these, please?
Folks can 100% figure this out from the data structures themselves.
Unless there's a compelling reason, this is pure churn.
> @@ -652,6 +653,7 @@ static const struct x86_cpu_id intel_cstates_match[] __initconst = {
> X86_MATCH_VFM(INTEL_ARROWLAKE_H, &adl_cstates),
> X86_MATCH_VFM(INTEL_ARROWLAKE_U, &adl_cstates),
> X86_MATCH_VFM(INTEL_LUNARLAKE_M, &lnl_cstates),
> + X86_MATCH_VFM(INTEL_PANTHERLAKE_L, &lnl_cstates),
> { },
> };
> MODULE_DEVICE_TABLE(x86cpu, intel_cstates_match);
Also, why *can't* this just be enumerated?
^ permalink raw reply [flat|nested] 6+ messages in thread
* RE: [PATCH] x86/events/intel/cstate: Add Pantherlake support
2025-11-12 20:07 ` Dave Hansen
@ 2025-11-13 4:05 ` Kumar, Kaushlendra
2025-11-13 18:20 ` Dave Hansen
0 siblings, 1 reply; 6+ messages in thread
From: Kumar, Kaushlendra @ 2025-11-13 4:05 UTC (permalink / raw)
To: Hansen, Dave, mingo@redhat.com, acme@kernel.org,
namhyung@kernel.org, jolsa@kernel.org, Hunter, Adrian,
bp@alien8.de, dave.hansen@linux.intel.com, x86@kernel.org
Cc: linux-perf-users@vger.kernel.org, linux-kernel@vger.kernel.org
On 11/12/25, [Reviewer Name] wrote:
> On 11/12/25 01:00, Kaushlendra Kumar wrote:
> > It supports the same C-state residency counters as Lunarlake.This
> > enables monitoring of C1, C6, C7 core states and C2,C3,C6,C10 package
> > states residency counters on Pantherlake platforms.
>
> Is this actually documented? Or is there just a smoke-filled room at
> Intel somewhere where this is decided?
Good point. Baseline for Pantherlake is Lunarlake with respect to C states. It is documented in internal documents. This approach is consistent with similar implementations
throughout the kernel codebase for related CPU families.
> > @@ -41,7 +41,7 @@
> > * MSR_CORE_C1_RES: CORE C1 Residency Counter
> > * perf code: 0x00
> > * Available model: SLM,AMT,GLM,CNL,ICX,TNT,ADL,RPL
> > - * MTL,SRF,GRR,ARL,LNL
> > + * MTL,SRF,GRR,ARL,LNL,PTL
>
> Could we get rid of these, please?
>
> Folks can 100% figure this out from the data structures themselves.
> Unless there's a compelling reason, this is pure churn.
Agreed. These comments are indeed redundant.
If we all agree, I'll remove those.
> > @@ -652,6 +653,7 @@ static const struct x86_cpu_id intel_cstates_match[] __initconst = {
> > X86_MATCH_VFM(INTEL_ARROWLAKE_H, &adl_cstates),
> > X86_MATCH_VFM(INTEL_ARROWLAKE_U, &adl_cstates),
> > X86_MATCH_VFM(INTEL_LUNARLAKE_M, &lnl_cstates),
> > + X86_MATCH_VFM(INTEL_PANTHERLAKE_L, &lnl_cstates),
> > { },
> > };
> > MODULE_DEVICE_TABLE(x86cpu, intel_cstates_match);
>
> Also, why *can't* this just be enumerated?
Could you clarify what you mean by "enumerated"? Are you suggesting:
1. Runtime detection instead of static matching?
2. A different approach to CPU model matching?
3. Something else?
The current approach follows the established pattern for other Intel
CPU models in this driver. If there's a preferred alternative approach,
I'm happy to implement it.
^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH] x86/events/intel/cstate: Add Pantherlake support
2025-11-12 9:00 [PATCH] x86/events/intel/cstate: Add Pantherlake support Kaushlendra Kumar
2025-11-12 20:07 ` Dave Hansen
@ 2025-11-13 6:50 ` Mi, Dapeng
2025-11-13 6:59 ` Mi, Dapeng
1 sibling, 1 reply; 6+ messages in thread
From: Mi, Dapeng @ 2025-11-13 6:50 UTC (permalink / raw)
To: Kaushlendra Kumar, mingo, acme, namhyung, jolsa, adrian.hunter,
bp, dave.hansen, x86
Cc: linux-perf-users, linux-kernel
Hi Kaushlendra,
The PTL cstate enabling patch had been merged into tip perf/core branch. :)
Thanks,
- Dapeng
On 11/12/2025 5:00 PM, Kaushlendra Kumar wrote:
> It supports the same C-state residency counters as Lunarlake.This
> enables monitoring of C1, C6, C7 core states and C2,C3,C6,C10
> package states residency counters on Pantherlake platforms.
>
> Signed-off-by: Kaushlendra Kumar <kaushlendra.kumar@intel.com>
> ---
> arch/x86/events/intel/cstate.c | 16 +++++++++-------
> 1 file changed, 9 insertions(+), 7 deletions(-)
>
> diff --git a/arch/x86/events/intel/cstate.c b/arch/x86/events/intel/cstate.c
> index ec753e39b007..b3582eeb6c4b 100644
> --- a/arch/x86/events/intel/cstate.c
> +++ b/arch/x86/events/intel/cstate.c
> @@ -41,7 +41,7 @@
> * MSR_CORE_C1_RES: CORE C1 Residency Counter
> * perf code: 0x00
> * Available model: SLM,AMT,GLM,CNL,ICX,TNT,ADL,RPL
> - * MTL,SRF,GRR,ARL,LNL
> + * MTL,SRF,GRR,ARL,LNL,PTL
> * Scope: Core (each processor core has a MSR)
> * MSR_CORE_C3_RESIDENCY: CORE C3 Residency Counter
> * perf code: 0x01
> @@ -53,31 +53,32 @@
> * Available model: SLM,AMT,NHM,WSM,SNB,IVB,HSW,BDW,
> * SKL,KNL,GLM,CNL,KBL,CML,ICL,ICX,
> * TGL,TNT,RKL,ADL,RPL,SPR,MTL,SRF,
> - * GRR,ARL,LNL
> + * GRR,ARL,LNL,PTL
> * Scope: Core
> * MSR_CORE_C7_RESIDENCY: CORE C7 Residency Counter
> * perf code: 0x03
> * Available model: SNB,IVB,HSW,BDW,SKL,CNL,KBL,CML,
> - * ICL,TGL,RKL,ADL,RPL,MTL,ARL,LNL
> + * ICL,TGL,RKL,ADL,RPL,MTL,ARL,LNL,
> + * PTL
> * Scope: Core
> * MSR_PKG_C2_RESIDENCY: Package C2 Residency Counter.
> * perf code: 0x00
> * Available model: SNB,IVB,HSW,BDW,SKL,KNL,GLM,CNL,
> * KBL,CML,ICL,ICX,TGL,TNT,RKL,ADL,
> - * RPL,SPR,MTL,ARL,LNL,SRF
> + * RPL,SPR,MTL,ARL,LNL,SRF,PTL
> * Scope: Package (physical package)
> * MSR_PKG_C3_RESIDENCY: Package C3 Residency Counter.
> * perf code: 0x01
> * Available model: NHM,WSM,SNB,IVB,HSW,BDW,SKL,KNL,
> * GLM,CNL,KBL,CML,ICL,TGL,TNT,RKL,
> - * ADL,RPL,MTL,ARL,LNL
> + * ADL,RPL,MTL,ARL,LNL,PTL
> * Scope: Package (physical package)
> * MSR_PKG_C6_RESIDENCY: Package C6 Residency Counter.
> * perf code: 0x02
> * Available model: SLM,AMT,NHM,WSM,SNB,IVB,HSW,BDW,
> * SKL,KNL,GLM,CNL,KBL,CML,ICL,ICX,
> * TGL,TNT,RKL,ADL,RPL,SPR,MTL,SRF,
> - * ARL,LNL
> + * ARL,LNL,PTL
> * Scope: Package (physical package)
> * MSR_PKG_C7_RESIDENCY: Package C7 Residency Counter.
> * perf code: 0x03
> @@ -96,7 +97,7 @@
> * MSR_PKG_C10_RESIDENCY: Package C10 Residency Counter.
> * perf code: 0x06
> * Available model: HSW ULT,KBL,GLM,CNL,CML,ICL,TGL,
> - * TNT,RKL,ADL,RPL,MTL,ARL,LNL
> + * TNT,RKL,ADL,RPL,MTL,ARL,LNL,PTL
> * Scope: Package (physical package)
> * MSR_MODULE_C6_RES_MS: Module C6 Residency Counter.
> * perf code: 0x00
> @@ -652,6 +653,7 @@ static const struct x86_cpu_id intel_cstates_match[] __initconst = {
> X86_MATCH_VFM(INTEL_ARROWLAKE_H, &adl_cstates),
> X86_MATCH_VFM(INTEL_ARROWLAKE_U, &adl_cstates),
> X86_MATCH_VFM(INTEL_LUNARLAKE_M, &lnl_cstates),
> + X86_MATCH_VFM(INTEL_PANTHERLAKE_L, &lnl_cstates),
> { },
> };
> MODULE_DEVICE_TABLE(x86cpu, intel_cstates_match);
^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH] x86/events/intel/cstate: Add Pantherlake support
2025-11-13 6:50 ` Mi, Dapeng
@ 2025-11-13 6:59 ` Mi, Dapeng
0 siblings, 0 replies; 6+ messages in thread
From: Mi, Dapeng @ 2025-11-13 6:59 UTC (permalink / raw)
To: Kaushlendra Kumar, mingo, acme, namhyung, jolsa, adrian.hunter,
bp, dave.hansen, x86
Cc: linux-perf-users, linux-kernel
On 11/13/2025 2:50 PM, Mi, Dapeng wrote:
> Hi Kaushlendra,
>
> The PTL cstate enabling patch had been merged into tip perf/core branch. :)
Sorry, forgot to paste the link.
https://lore.kernel.org/all/20251023223754.1743928-4-zide.chen@intel.com/
>
> Thanks,
>
> - Dapeng
>
> On 11/12/2025 5:00 PM, Kaushlendra Kumar wrote:
>> It supports the same C-state residency counters as Lunarlake.This
>> enables monitoring of C1, C6, C7 core states and C2,C3,C6,C10
>> package states residency counters on Pantherlake platforms.
>>
>> Signed-off-by: Kaushlendra Kumar <kaushlendra.kumar@intel.com>
>> ---
>> arch/x86/events/intel/cstate.c | 16 +++++++++-------
>> 1 file changed, 9 insertions(+), 7 deletions(-)
>>
>> diff --git a/arch/x86/events/intel/cstate.c b/arch/x86/events/intel/cstate.c
>> index ec753e39b007..b3582eeb6c4b 100644
>> --- a/arch/x86/events/intel/cstate.c
>> +++ b/arch/x86/events/intel/cstate.c
>> @@ -41,7 +41,7 @@
>> * MSR_CORE_C1_RES: CORE C1 Residency Counter
>> * perf code: 0x00
>> * Available model: SLM,AMT,GLM,CNL,ICX,TNT,ADL,RPL
>> - * MTL,SRF,GRR,ARL,LNL
>> + * MTL,SRF,GRR,ARL,LNL,PTL
>> * Scope: Core (each processor core has a MSR)
>> * MSR_CORE_C3_RESIDENCY: CORE C3 Residency Counter
>> * perf code: 0x01
>> @@ -53,31 +53,32 @@
>> * Available model: SLM,AMT,NHM,WSM,SNB,IVB,HSW,BDW,
>> * SKL,KNL,GLM,CNL,KBL,CML,ICL,ICX,
>> * TGL,TNT,RKL,ADL,RPL,SPR,MTL,SRF,
>> - * GRR,ARL,LNL
>> + * GRR,ARL,LNL,PTL
>> * Scope: Core
>> * MSR_CORE_C7_RESIDENCY: CORE C7 Residency Counter
>> * perf code: 0x03
>> * Available model: SNB,IVB,HSW,BDW,SKL,CNL,KBL,CML,
>> - * ICL,TGL,RKL,ADL,RPL,MTL,ARL,LNL
>> + * ICL,TGL,RKL,ADL,RPL,MTL,ARL,LNL,
>> + * PTL
>> * Scope: Core
>> * MSR_PKG_C2_RESIDENCY: Package C2 Residency Counter.
>> * perf code: 0x00
>> * Available model: SNB,IVB,HSW,BDW,SKL,KNL,GLM,CNL,
>> * KBL,CML,ICL,ICX,TGL,TNT,RKL,ADL,
>> - * RPL,SPR,MTL,ARL,LNL,SRF
>> + * RPL,SPR,MTL,ARL,LNL,SRF,PTL
>> * Scope: Package (physical package)
>> * MSR_PKG_C3_RESIDENCY: Package C3 Residency Counter.
>> * perf code: 0x01
>> * Available model: NHM,WSM,SNB,IVB,HSW,BDW,SKL,KNL,
>> * GLM,CNL,KBL,CML,ICL,TGL,TNT,RKL,
>> - * ADL,RPL,MTL,ARL,LNL
>> + * ADL,RPL,MTL,ARL,LNL,PTL
>> * Scope: Package (physical package)
>> * MSR_PKG_C6_RESIDENCY: Package C6 Residency Counter.
>> * perf code: 0x02
>> * Available model: SLM,AMT,NHM,WSM,SNB,IVB,HSW,BDW,
>> * SKL,KNL,GLM,CNL,KBL,CML,ICL,ICX,
>> * TGL,TNT,RKL,ADL,RPL,SPR,MTL,SRF,
>> - * ARL,LNL
>> + * ARL,LNL,PTL
>> * Scope: Package (physical package)
>> * MSR_PKG_C7_RESIDENCY: Package C7 Residency Counter.
>> * perf code: 0x03
>> @@ -96,7 +97,7 @@
>> * MSR_PKG_C10_RESIDENCY: Package C10 Residency Counter.
>> * perf code: 0x06
>> * Available model: HSW ULT,KBL,GLM,CNL,CML,ICL,TGL,
>> - * TNT,RKL,ADL,RPL,MTL,ARL,LNL
>> + * TNT,RKL,ADL,RPL,MTL,ARL,LNL,PTL
>> * Scope: Package (physical package)
>> * MSR_MODULE_C6_RES_MS: Module C6 Residency Counter.
>> * perf code: 0x00
>> @@ -652,6 +653,7 @@ static const struct x86_cpu_id intel_cstates_match[] __initconst = {
>> X86_MATCH_VFM(INTEL_ARROWLAKE_H, &adl_cstates),
>> X86_MATCH_VFM(INTEL_ARROWLAKE_U, &adl_cstates),
>> X86_MATCH_VFM(INTEL_LUNARLAKE_M, &lnl_cstates),
>> + X86_MATCH_VFM(INTEL_PANTHERLAKE_L, &lnl_cstates),
>> { },
>> };
>> MODULE_DEVICE_TABLE(x86cpu, intel_cstates_match);
^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH] x86/events/intel/cstate: Add Pantherlake support
2025-11-13 4:05 ` Kumar, Kaushlendra
@ 2025-11-13 18:20 ` Dave Hansen
0 siblings, 0 replies; 6+ messages in thread
From: Dave Hansen @ 2025-11-13 18:20 UTC (permalink / raw)
To: Kumar, Kaushlendra, mingo@redhat.com, acme@kernel.org,
namhyung@kernel.org, jolsa@kernel.org, Hunter, Adrian,
bp@alien8.de, dave.hansen@linux.intel.com, x86@kernel.org
Cc: linux-perf-users@vger.kernel.org, linux-kernel@vger.kernel.org
On 11/12/25 20:05, Kumar, Kaushlendra wrote:
> On 11/12/25, [Reviewer Name] wrote:
>> On 11/12/25 01:00, Kaushlendra Kumar wrote:
>>> It supports the same C-state residency counters as
>>> Lunarlake.This enables monitoring of C1, C6, C7 core states and
>>> C2,C3,C6,C10 package states residency counters on Pantherlake
>>> platforms.
>>
>> Is this actually documented? Or is there just a smoke-filled room
>> at Intel somewhere where this is decided?
>
> Good point. Baseline for Pantherlake is Lunarlake with respect to C
> states. It is documented in internal documents. This approach is
> consistent with similar implementations throughout the kernel
> codebase for related CPU families.
It needs to be publicly documented somewhere. It doesn't have to be
fancy: a web page or white paper would be fine.
I know it's been allowed to slide up until now. But, according to[1]:
We (Intel) continuously improve, enabling us to be more curious,
bold and innovative.
So, can we try to improve this, please?
...>> Also, why *can't* this just be enumerated?
>
> Could you clarify what you mean by "enumerated"? Are you suggesting:
> 1. Runtime detection instead of static matching?
> 2. A different approach to CPU model matching?
> 3. Something else?
>
> The current approach follows the established pattern for other Intel
> CPU models in this driver. If there's a preferred alternative approach,
> I'm happy to implement it.
Your patch effectively says:
PTL supports C10 package states residency counters
(among others of course). Why can't there be a bit in CPUID or an MSR
somewhere that, when set, means the same thing? That way, we don't have
to keep patching the kernel every time there's a new CPU model.
I guess in general PMU things haven't been architectural. But this seems
like something that wouldn't be too hard for the CPU itself to enumerate
to software.
1.
https://www.intel.com/content/www/us/en/corporate-responsibility/our-values.html
^ permalink raw reply [flat|nested] 6+ messages in thread
end of thread, other threads:[~2025-11-13 18:20 UTC | newest]
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2025-11-12 9:00 [PATCH] x86/events/intel/cstate: Add Pantherlake support Kaushlendra Kumar
2025-11-12 20:07 ` Dave Hansen
2025-11-13 4:05 ` Kumar, Kaushlendra
2025-11-13 18:20 ` Dave Hansen
2025-11-13 6:50 ` Mi, Dapeng
2025-11-13 6:59 ` Mi, Dapeng
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