Re: [Patch v3 4/4] perf/x86/intel: Consolidate MSR_IA32_PERF_CFG_C tracking

Mi, Dapeng
2026-04-29T00:51:05Z

On 4/28/2026 9:00 PM, Peter Zijlstra wrote:
> On Mon, Apr 27, 2026 at 04:55:13PM +0800, Dapeng Mi wrote:
>> Both Auto Counter Reload (ACR) and Architectural PEBS use the PERF_CFG_C
>> MSRs to configure event behavior. Currently, the driver maintains two
>> independent variables acr_cfg_c and cfg_c_val to cache the values intended
>> for these MSRs.
>>
>> Using separate variables to track a single hardware register state is
>> error-prone and can lead to configuration conflicts. Consolidate the
>> tracking into a single cfg_c_val variable to ensure a unified and
>> consistent view of the PERF_CFG_C MSR state.
>>
>> Signed-off-by: Dapeng Mi <dapeng1.mi@linux.intel.com>
> So the earlier patches deserve to be in perf/urgent, but this one
> doesn't actually fix anything and goes in perf/core ?

Yes, I suppose so.

But Sashiko found a new corner issue.

"

If Event A moves to a new counter but Event B itself does not move,
match_prev_assignment() would evaluate to true for Event B, and
x86_pmu_start() would be skipped.

Does this mean the updated hw.config1 for Event B is never written to the
physical hardware MSR, breaking the Auto Counter Reload functionality?

"

and the Patch 1/4 can be further optimized and simplified.

I would post an new version patchset to fix all these.

Thanks.

>