* [PATCH v2 1/3] perf vendor events arm64: Fix incorrect Hisi hip08 L3 metrics
2022-10-21 10:50 [PATCH v2 0/3] perf vendor events arm64: Fix incorrect metrics and improve readability Shang XiaoJing
@ 2022-10-21 10:50 ` Shang XiaoJing
2022-10-26 9:07 ` John Garry
2022-10-21 10:50 ` [PATCH v2 2/3] perf vendor events arm64: Add HiSilicon hip08 core events Shang XiaoJing
2022-10-21 10:50 ` [PATCH v2 3/3] perf vendor events arm64: Use event name instead of event code Shang XiaoJing
2 siblings, 1 reply; 8+ messages in thread
From: Shang XiaoJing @ 2022-10-21 10:50 UTC (permalink / raw)
To: john.garry, will, james.clark, mike.leach, leo.yan, peterz, mingo,
acme, mark.rutland, alexander.shishkin, jolsa, namhyung, kjain,
linux-arm-kernel, linux-perf-users
Cc: shangxiaojing
Commit 0cc177cfc95d ("perf vendor events arm64: Add Hisi hip08 L3
metrics") add L3 metrics of hip08, but some metrics (IF_BP_MISP_BR_RET,
IF_BP_MISP_BR_RET, IF_BP_MISP_BR_BL) have incorrect event number due to
the mistakes in document, which caused incorrect result. Fix the
incorrect metrics.
before:
65,811,214,308 armv8_pmuv3_0/event=0x1014/ # 18.87 push_branch
# -40.19 other_branch
3,564,316,780 BR_MIS_PRED # 0.51 indirect_branch
# 21.81 pop_branch
after:
6,537,146,245 BR_MIS_PRED # 0.48 indirect_branch
# 0.47 pop_branch
# 0.00 push_branch
# 0.05 other_branch
Fixes: 0cc177cfc95d ("perf vendor events arm64: Add Hisi hip08 L3 metrics")
Signed-off-by: Shang XiaoJing <shangxiaojing@huawei.com>
Cc: John Garry <john.garry@huawei.com>
Acked-by: James Clark <james.clark@arm.com>
---
changes in v2:
- adjust commit msg.
---
.../perf/pmu-events/arch/arm64/hisilicon/hip08/metrics.json | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/tools/perf/pmu-events/arch/arm64/hisilicon/hip08/metrics.json b/tools/perf/pmu-events/arch/arm64/hisilicon/hip08/metrics.json
index 6970203cb247..6443a061e22a 100644
--- a/tools/perf/pmu-events/arch/arm64/hisilicon/hip08/metrics.json
+++ b/tools/perf/pmu-events/arch/arm64/hisilicon/hip08/metrics.json
@@ -112,21 +112,21 @@
"MetricName": "indirect_branch"
},
{
- "MetricExpr": "(armv8_pmuv3_0@event\\=0x1014@ + armv8_pmuv3_0@event\\=0x1018@) / BR_MIS_PRED",
+ "MetricExpr": "(armv8_pmuv3_0@event\\=0x1013@ + armv8_pmuv3_0@event\\=0x1016@) / BR_MIS_PRED",
"PublicDescription": "Push branch L3 topdown metric",
"BriefDescription": "Push branch L3 topdown metric",
"MetricGroup": "TopDownL3",
"MetricName": "push_branch"
},
{
- "MetricExpr": "armv8_pmuv3_0@event\\=0x100c@ / BR_MIS_PRED",
+ "MetricExpr": "armv8_pmuv3_0@event\\=0x100d@ / BR_MIS_PRED",
"PublicDescription": "Pop branch L3 topdown metric",
"BriefDescription": "Pop branch L3 topdown metric",
"MetricGroup": "TopDownL3",
"MetricName": "pop_branch"
},
{
- "MetricExpr": "(BR_MIS_PRED - armv8_pmuv3_0@event\\=0x1010@ - armv8_pmuv3_0@event\\=0x1014@ - armv8_pmuv3_0@event\\=0x1018@ - armv8_pmuv3_0@event\\=0x100c@) / BR_MIS_PRED",
+ "MetricExpr": "(BR_MIS_PRED - armv8_pmuv3_0@event\\=0x1010@ - armv8_pmuv3_0@event\\=0x1013@ - armv8_pmuv3_0@event\\=0x1016@ - armv8_pmuv3_0@event\\=0x100d@) / BR_MIS_PRED",
"PublicDescription": "Other branch L3 topdown metric",
"BriefDescription": "Other branch L3 topdown metric",
"MetricGroup": "TopDownL3",
--
2.17.1
^ permalink raw reply related [flat|nested] 8+ messages in thread* Re: [PATCH v2 1/3] perf vendor events arm64: Fix incorrect Hisi hip08 L3 metrics
2022-10-21 10:50 ` [PATCH v2 1/3] perf vendor events arm64: Fix incorrect Hisi hip08 L3 metrics Shang XiaoJing
@ 2022-10-26 9:07 ` John Garry
2022-10-26 14:03 ` Arnaldo Carvalho de Melo
0 siblings, 1 reply; 8+ messages in thread
From: John Garry @ 2022-10-26 9:07 UTC (permalink / raw)
To: Shang XiaoJing, will, james.clark, mike.leach, leo.yan, peterz,
mingo, acme, mark.rutland, alexander.shishkin, jolsa, namhyung,
kjain, linux-arm-kernel, linux-perf-users
On 21/10/2022 11:50, Shang XiaoJing wrote:
> Commit 0cc177cfc95d ("perf vendor events arm64: Add Hisi hip08 L3
> metrics") add L3 metrics of hip08, but some metrics (IF_BP_MISP_BR_RET,
> IF_BP_MISP_BR_RET, IF_BP_MISP_BR_BL) have incorrect event number due to
> the mistakes in document, which caused incorrect result. Fix the
> incorrect metrics.
>
> before:
> 65,811,214,308 armv8_pmuv3_0/event=0x1014/ # 18.87 push_branch
> # -40.19 other_branch
> 3,564,316,780 BR_MIS_PRED # 0.51 indirect_branch
> # 21.81 pop_branch
>
> after:
> 6,537,146,245 BR_MIS_PRED # 0.48 indirect_branch
> # 0.47 pop_branch
> # 0.00 push_branch
> # 0.05 other_branch
>
> Fixes: 0cc177cfc95d ("perf vendor events arm64: Add Hisi hip08 L3 metrics")
> Signed-off-by: Shang XiaoJing<shangxiaojing@huawei.com>
> Cc: John Garry<john.garry@huawei.com>
> Acked-by: James Clark<james.clark@arm.com>
Reviewed-by: John Garry <john.garry@huawei.com>
> ---
^ permalink raw reply [flat|nested] 8+ messages in thread* Re: [PATCH v2 1/3] perf vendor events arm64: Fix incorrect Hisi hip08 L3 metrics
2022-10-26 9:07 ` John Garry
@ 2022-10-26 14:03 ` Arnaldo Carvalho de Melo
0 siblings, 0 replies; 8+ messages in thread
From: Arnaldo Carvalho de Melo @ 2022-10-26 14:03 UTC (permalink / raw)
To: John Garry
Cc: Shang XiaoJing, will, james.clark, mike.leach, leo.yan, peterz,
mingo, mark.rutland, alexander.shishkin, jolsa, namhyung, kjain,
linux-arm-kernel, linux-perf-users
Em Wed, Oct 26, 2022 at 10:07:44AM +0100, John Garry escreveu:
> On 21/10/2022 11:50, Shang XiaoJing wrote:
> > Commit 0cc177cfc95d ("perf vendor events arm64: Add Hisi hip08 L3
> > metrics") add L3 metrics of hip08, but some metrics (IF_BP_MISP_BR_RET,
> > IF_BP_MISP_BR_RET, IF_BP_MISP_BR_BL) have incorrect event number due to
> > the mistakes in document, which caused incorrect result. Fix the
> > incorrect metrics.
> >
> > before:
> > 65,811,214,308 armv8_pmuv3_0/event=0x1014/ # 18.87 push_branch
> > # -40.19 other_branch
> > 3,564,316,780 BR_MIS_PRED # 0.51 indirect_branch
> > # 21.81 pop_branch
> >
> > after:
> > 6,537,146,245 BR_MIS_PRED # 0.48 indirect_branch
> > # 0.47 pop_branch
> > # 0.00 push_branch
> > # 0.05 other_branch
> >
> > Fixes: 0cc177cfc95d ("perf vendor events arm64: Add Hisi hip08 L3 metrics")
> > Signed-off-by: Shang XiaoJing<shangxiaojing@huawei.com>
> > Cc: John Garry<john.garry@huawei.com>
> > Acked-by: James Clark<james.clark@arm.com>
>
> Reviewed-by: John Garry <john.garry@huawei.com>
Applied to perf/urgent.
- Arnaldo
^ permalink raw reply [flat|nested] 8+ messages in thread
* [PATCH v2 2/3] perf vendor events arm64: Add HiSilicon hip08 core events
2022-10-21 10:50 [PATCH v2 0/3] perf vendor events arm64: Fix incorrect metrics and improve readability Shang XiaoJing
2022-10-21 10:50 ` [PATCH v2 1/3] perf vendor events arm64: Fix incorrect Hisi hip08 L3 metrics Shang XiaoJing
@ 2022-10-21 10:50 ` Shang XiaoJing
2022-10-26 9:23 ` John Garry
2022-10-21 10:50 ` [PATCH v2 3/3] perf vendor events arm64: Use event name instead of event code Shang XiaoJing
2 siblings, 1 reply; 8+ messages in thread
From: Shang XiaoJing @ 2022-10-21 10:50 UTC (permalink / raw)
To: john.garry, will, james.clark, mike.leach, leo.yan, peterz, mingo,
acme, mark.rutland, alexander.shishkin, jolsa, namhyung, kjain,
linux-arm-kernel, linux-perf-users
Cc: shangxiaojing
Add some core events of hip08 to the corresponding core-imp-def.json.
Signed-off-by: Shang XiaoJing <shangxiaojing@huawei.com>
Acked-by: James Clark <james.clark@arm.com>
---
.../arm64/hisilicon/hip08/core-imp-def.json | 132 ++++++++++++++++++
1 file changed, 132 insertions(+)
diff --git a/tools/perf/pmu-events/arch/arm64/hisilicon/hip08/core-imp-def.json b/tools/perf/pmu-events/arch/arm64/hisilicon/hip08/core-imp-def.json
index a4a6408639b4..f9a90d6a958d 100644
--- a/tools/perf/pmu-events/arch/arm64/hisilicon/hip08/core-imp-def.json
+++ b/tools/perf/pmu-events/arch/arm64/hisilicon/hip08/core-imp-def.json
@@ -53,6 +53,36 @@
{
"ArchStdEvent": "L2D_CACHE_INVAL"
},
+ {
+ "PublicDescription": "Number of predictable branches predicted by static predictor",
+ "EventCode": "0x1001",
+ "EventName": "IF_BP_PRED_BR_SP",
+ "BriefDescription": "Static predictor predict count"
+ },
+ {
+ "PublicDescription": "Number of mispredicted procedure returns",
+ "EventCode": "0x100d",
+ "EventName": "IF_BP_MISP_BR_RET",
+ "BriefDescription": "Mispredicted procedures"
+ },
+ {
+ "PublicDescription": "Number of mispredicted indirect branches",
+ "EventCode": "0x1010",
+ "EventName": "IF_BP_MISP_BR_IND",
+ "BriefDescription": "Mispredicted indirect branches"
+ },
+ {
+ "PublicDescription": "Number of mispredicted BLR branches",
+ "EventCode": "0x1013",
+ "EventName": "IF_BP_MISP_BR_BLR",
+ "BriefDescription": "Mispredicted BLR branches"
+ },
+ {
+ "PublicDescription": "Number of mispredicted BL branches",
+ "EventCode": "0x1016",
+ "EventName": "IF_BP_MISP_BR_BL",
+ "BriefDescription": "Mispredicted BL branches"
+ },
{
"PublicDescription": "Level 1 instruction cache prefetch access count",
"EventCode": "0x102e",
@@ -77,12 +107,90 @@
"EventName": "IF_IS_STALL",
"BriefDescription": "Instruction fetch stall cycles"
},
+ {
+ "PublicDescription": "Number of times ROB is full",
+ "EventCode": "0x2004",
+ "EventName": "ROB_STALL",
+ "BriefDescription": "ROB stall"
+ },
+ {
+ "PublicDescription": "Number of times PC buffer is full",
+ "EventCode": "0x2005",
+ "EventName": "PCBUF_STALL",
+ "BriefDescription": "PC buffer stall"
+ },
+ {
+ "PublicDescription": "No INT ptag allocated from free list",
+ "EventCode": "0x2006",
+ "EventName": "INT_PTAG_STALL",
+ "BriefDescription": "INT ptag stall"
+ },
+ {
+ "PublicDescription": "No CC ptag allocated from free list",
+ "EventCode": "0x2007",
+ "EventName": "CC_PTAG_STALL",
+ "BriefDescription": "CC ptag stall"
+ },
+ {
+ "PublicDescription": "No VFP ptag allocated from free list",
+ "EventCode": "0x2008",
+ "EventName": "VFP_PTAG_STALL",
+ "BriefDescription": "VFP ptag stall"
+ },
+ {
+ "PublicDescription": "Issue queue of ALU is full",
+ "EventCode": "0x200b",
+ "EventName": "ALU_ISQ_STALL",
+ "BriefDescription": "ALU issue queue stall"
+ },
+ {
+ "PublicDescription": "Issue queue of LSU is full",
+ "EventCode": "0x200c",
+ "EventName": "LSU_ISQ_STALL",
+ "BriefDescription": "LSU issueQ stall"
+ },
+ {
+ "PublicDescription": "Issue queue of FSU is full",
+ "EventCode": "0x200d",
+ "EventName": "FSU_ISQ_STALL",
+ "BriefDescription": "FSU issueQ stall"
+ },
+ {
+ "PublicDescription": "Sync buffer is full",
+ "EventCode": "0x2010",
+ "EventName": "SYNC_STALL",
+ "BriefDescription": "Sync buffer stall"
+ },
+ {
+ "PublicDescription": "LSU nuke flush caused by incorrect data from speculative execution",
+ "EventCode": "0x2012",
+ "EventName": "NUKE_FLUSH",
+ "BriefDescription": "LSU nuke flush"
+ },
+ {
+ "PublicDescription": "OoO ROB flush",
+ "EventCode": "0x2013",
+ "EventName": "OOO_FLUSH",
+ "BriefDescription": "OoO ROB flush"
+ },
{
"PublicDescription": "Instructions can receive, but not send",
"EventCode": "0x2014",
"EventName": "FETCH_BUBBLE",
"BriefDescription": "Instructions can receive, but not send"
},
+ {
+ "PublicDescription": "Cycles of Fetch bubble >= 4",
+ "EventCode": "0x201d",
+ "EventName": "FETCH_BUBBLE_EXCEEDMIW",
+ "BriefDescription": "Cycles of Fetch bubble >= 4"
+ },
+ {
+ "PublicDescription": "SaveOp queue is full",
+ "EventCode": "0x201e",
+ "EventName": "SAVEOP_QUEUE_STALL",
+ "BriefDescription": "SaveOp queue stall"
+ },
{
"PublicDescription": "Prefetch request from LSU",
"EventCode": "0x6013",
@@ -95,18 +203,42 @@
"EventName": "HIT_ON_PRF",
"BriefDescription": "Hit on prefetched data"
},
+ {
+ "PublicDescription": "OoO Stall & Inst in OoO but No_Dispatch & IssueQ_can_Accept",
+ "EventCode": "0x7000",
+ "EventName": "RESOURCE_BOUND",
+ "BriefDescription": "OoO Stall & Inst in OoO but No_Dispatch & IssueQ_can_Accept"
+ },
{
"PublicDescription": "Cycles of that the number of issuing micro operations are less than 4",
"EventCode": "0x7001",
"EventName": "EXE_STALL_CYCLE",
"BriefDescription": "Cycles of that the number of issue ups are less than 4"
},
+ {
+ "PublicDescription": "No any micro operation is issued & no memstall & executing DIV operation",
+ "EventCode": "0x7002",
+ "EventName": "EXE_STALL_DIV",
+ "BriefDescription": "No any micro operation is issued & no memstall & executing DIV operation"
+ },
+ {
+ "PublicDescription": "No INT operation is issued & no FSU operation is issued & executing FSU operation",
+ "EventCode": "0x7003",
+ "EventName": "FSU_STALL",
+ "BriefDescription": "No INT operation is issued & no FSU operation is issued & executing FSU operation"
+ },
{
"PublicDescription": "No any micro operation is issued and meanwhile any load operation is not resolved",
"EventCode": "0x7004",
"EventName": "MEM_STALL_ANYLOAD",
"BriefDescription": "No any micro operation is issued and meanwhile any load operation is not resolved"
},
+ {
+ "PublicDescription": "No any micro operation is issued and meanwhile any store operation is not resolved",
+ "EventCode": "0x7005",
+ "EventName": "MEM_STALL_ANYSTORE",
+ "BriefDescription": "No any micro operation is issued and meanwhile any store operation is not resolved"
+ },
{
"PublicDescription": "No any micro operation is issued and meanwhile there is any load operation missing L1 cache and pending data refill",
"EventCode": "0x7006",
--
2.17.1
^ permalink raw reply related [flat|nested] 8+ messages in thread* Re: [PATCH v2 2/3] perf vendor events arm64: Add HiSilicon hip08 core events
2022-10-21 10:50 ` [PATCH v2 2/3] perf vendor events arm64: Add HiSilicon hip08 core events Shang XiaoJing
@ 2022-10-26 9:23 ` John Garry
0 siblings, 0 replies; 8+ messages in thread
From: John Garry @ 2022-10-26 9:23 UTC (permalink / raw)
To: Shang XiaoJing, will, james.clark, mike.leach, leo.yan, peterz,
mingo, acme, mark.rutland, alexander.shishkin, jolsa, namhyung,
kjain, linux-arm-kernel, linux-perf-users
On 21/10/2022 11:50, Shang XiaoJing wrote:
> Add some core events of hip08 to the corresponding core-imp-def.json.
Are they actually useful? When I upsteamed the original events, I was
told that they were the only useful ones
>
> Signed-off-by: Shang XiaoJing <shangxiaojing@huawei.com>
> Acked-by: James Clark <james.clark@arm.com>
Generally looks ok, but some event descriptions are hard to understand,
below.
Reveiewed-by: John Garry <john.garry@huawei.com<
> ---
> .../arm64/hisilicon/hip08/core-imp-def.json | 132 ++++++++++++++++++
> 1 file changed, 132 insertions(+)
>
> diff --git a/tools/perf/pmu-events/arch/arm64/hisilicon/hip08/core-imp-def.json b/tools/perf/pmu-events/arch/arm64/hisilicon/hip08/core-imp-def.json
> index a4a6408639b4..f9a90d6a958d 100644
> --- a/tools/perf/pmu-events/arch/arm64/hisilicon/hip08/core-imp-def.json
> +++ b/tools/perf/pmu-events/arch/arm64/hisilicon/hip08/core-imp-def.json
> @@ -53,6 +53,36 @@
> {
> "ArchStdEvent": "L2D_CACHE_INVAL"
> },
> + {
> + "PublicDescription": "Number of predictable branches predicted by static predictor",
> + "EventCode": "0x1001",
> + "EventName": "IF_BP_PRED_BR_SP",
> + "BriefDescription": "Static predictor predict count"
> + },
> + {
> + "PublicDescription": "Number of mispredicted procedure returns",
> + "EventCode": "0x100d",
> + "EventName": "IF_BP_MISP_BR_RET",
> + "BriefDescription": "Mispredicted procedures"
> + },
> + {
> + "PublicDescription": "Number of mispredicted indirect branches",
> + "EventCode": "0x1010",
> + "EventName": "IF_BP_MISP_BR_IND",
> + "BriefDescription": "Mispredicted indirect branches"
> + },
> + {
> + "PublicDescription": "Number of mispredicted BLR branches",
maybe telling what BLR is would be helpful
> + "EventCode": "0x1013",
> + "EventName": "IF_BP_MISP_BR_BLR",
> + "BriefDescription": "Mispredicted BLR branches"
> + },
> + {
> + "PublicDescription": "Number of mispredicted BL branches",
> + "EventCode": "0x1016",
> + "EventName": "IF_BP_MISP_BR_BL",
> + "BriefDescription": "Mispredicted BL branches"
> + },
> {
> "PublicDescription": "Level 1 instruction cache prefetch access count",
> "EventCode": "0x102e",
> @@ -77,12 +107,90 @@
> "EventName": "IF_IS_STALL",
> "BriefDescription": "Instruction fetch stall cycles"
> },
> + {
> + "PublicDescription": "Number of times ROB is full",
> + "EventCode": "0x2004",
> + "EventName": "ROB_STALL",
> + "BriefDescription": "ROB stall"
> + },
> + {
> + "PublicDescription": "Number of times PC buffer is full",
> + "EventCode": "0x2005",
> + "EventName": "PCBUF_STALL",
> + "BriefDescription": "PC buffer stall"
> + },
> + {
> + "PublicDescription": "No INT ptag allocated from free list",
> + "EventCode": "0x2006",
> + "EventName": "INT_PTAG_STALL",
> + "BriefDescription": "INT ptag stall"
> + },
> + {
> + "PublicDescription": "No CC ptag allocated from free list",
> + "EventCode": "0x2007",
> + "EventName": "CC_PTAG_STALL",
> + "BriefDescription": "CC ptag stall"
> + },
> + {
> + "PublicDescription": "No VFP ptag allocated from free list",
> + "EventCode": "0x2008",
> + "EventName": "VFP_PTAG_STALL",
> + "BriefDescription": "VFP ptag stall"
> + },
> + {
> + "PublicDescription": "Issue queue of ALU is full",
> + "EventCode": "0x200b",
> + "EventName": "ALU_ISQ_STALL",
> + "BriefDescription": "ALU issue queue stall"
> + },
> + {
> + "PublicDescription": "Issue queue of LSU is full",
> + "EventCode": "0x200c",
> + "EventName": "LSU_ISQ_STALL",
> + "BriefDescription": "LSU issueQ stall"
> + },
> + {
> + "PublicDescription": "Issue queue of FSU is full",
> + "EventCode": "0x200d",
> + "EventName": "FSU_ISQ_STALL",
> + "BriefDescription": "FSU issueQ stall"
> + },
> + {
> + "PublicDescription": "Sync buffer is full",
> + "EventCode": "0x2010",
> + "EventName": "SYNC_STALL",
> + "BriefDescription": "Sync buffer stall"
> + },
> + {
> + "PublicDescription": "LSU nuke flush caused by incorrect data from speculative execution",
> + "EventCode": "0x2012",
> + "EventName": "NUKE_FLUSH",
> + "BriefDescription": "LSU nuke flush"
> + },
> + {
> + "PublicDescription": "OoO ROB flush",
> + "EventCode": "0x2013",
> + "EventName": "OOO_FLUSH",
> + "BriefDescription": "OoO ROB flush"
> + },
> {
> "PublicDescription": "Instructions can receive, but not send",
> "EventCode": "0x2014",
> "EventName": "FETCH_BUBBLE",
> "BriefDescription": "Instructions can receive, but not send"
> },
> + {
> + "PublicDescription": "Cycles of Fetch bubble >= 4",
/s/Fetch/fetch/
> + "EventCode": "0x201d",
> + "EventName": "FETCH_BUBBLE_EXCEEDMIW",
> + "BriefDescription": "Cycles of Fetch bubble >= 4"
> + },
> + {
> + "PublicDescription": "SaveOp queue is full",
> + "EventCode": "0x201e",
> + "EventName": "SAVEOP_QUEUE_STALL",
> + "BriefDescription": "SaveOp queue stall"
> + },
> {
> "PublicDescription": "Prefetch request from LSU",
> "EventCode": "0x6013",
> @@ -95,18 +203,42 @@
> "EventName": "HIT_ON_PRF",
> "BriefDescription": "Hit on prefetched data"
> },
> + {
> + "PublicDescription": "OoO Stall & Inst in OoO but No_Dispatch & IssueQ_can_Accept",
This is hard to understand
> + "EventCode": "0x7000",
> + "EventName": "RESOURCE_BOUND",
> + "BriefDescription": "OoO Stall & Inst in OoO but No_Dispatch & IssueQ_can_Accept"
> + },
> {
> "PublicDescription": "Cycles of that the number of issuing micro operations are less than 4",
> "EventCode": "0x7001",
> "EventName": "EXE_STALL_CYCLE",
> "BriefDescription": "Cycles of that the number of issue ups are less than 4"
> },
> + {
> + "PublicDescription": "No any micro operation is issued & no memstall & executing DIV operation",
> + "EventCode": "0x7002",
> + "EventName": "EXE_STALL_DIV",
> + "BriefDescription": "No any micro operation is issued & no memstall & executing DIV operation"
> + },
> + {
> + "PublicDescription": "No INT operation is issued & no FSU operation is issued & executing FSU operation",
> + "EventCode": "0x7003",
> + "EventName": "FSU_STALL",
> + "BriefDescription": "No INT operation is issued & no FSU operation is issued & executing FSU operation"
> + },
> {
> "PublicDescription": "No any micro operation is issued and meanwhile any load operation is not resolved",
> "EventCode": "0x7004",
> "EventName": "MEM_STALL_ANYLOAD",
> "BriefDescription": "No any micro operation is issued and meanwhile any load operation is not resolved"
> },
> + {
> + "PublicDescription": "No any micro operation is issued and meanwhile any store operation is not resolved",
The grammar here is understand, specifically "No any micro ...". There
are many instances of this in the above events.
> + "EventCode": "0x7005",
> + "EventName": "MEM_STALL_ANYSTORE",
> + "BriefDescription": "No any micro operation is issued and meanwhile any store operation is not resolved"
> + },
> {
> "PublicDescription": "No any micro operation is issued and meanwhile there is any load operation missing L1 cache and pending data refill",
> "EventCode": "0x7006",
^ permalink raw reply [flat|nested] 8+ messages in thread
* [PATCH v2 3/3] perf vendor events arm64: Use event name instead of event code
2022-10-21 10:50 [PATCH v2 0/3] perf vendor events arm64: Fix incorrect metrics and improve readability Shang XiaoJing
2022-10-21 10:50 ` [PATCH v2 1/3] perf vendor events arm64: Fix incorrect Hisi hip08 L3 metrics Shang XiaoJing
2022-10-21 10:50 ` [PATCH v2 2/3] perf vendor events arm64: Add HiSilicon hip08 core events Shang XiaoJing
@ 2022-10-21 10:50 ` Shang XiaoJing
2022-10-26 9:25 ` John Garry
2 siblings, 1 reply; 8+ messages in thread
From: Shang XiaoJing @ 2022-10-21 10:50 UTC (permalink / raw)
To: john.garry, will, james.clark, mike.leach, leo.yan, peterz, mingo,
acme, mark.rutland, alexander.shishkin, jolsa, namhyung, kjain,
linux-arm-kernel, linux-perf-users
Cc: shangxiaojing
Use the event name instead of the corresponding event code for more
clear, which makes the result of perf more readable.
Signed-off-by: Shang XiaoJing <shangxiaojing@huawei.com>
Acked-by: James Clark <james.clark@arm.com>
---
changes in v2:
- fix the tab.
---
.../arch/arm64/hisilicon/hip08/metrics.json | 48 +++++++++----------
1 file changed, 24 insertions(+), 24 deletions(-)
diff --git a/tools/perf/pmu-events/arch/arm64/hisilicon/hip08/metrics.json b/tools/perf/pmu-events/arch/arm64/hisilicon/hip08/metrics.json
index 6443a061e22a..59c693236ad2 100644
--- a/tools/perf/pmu-events/arch/arm64/hisilicon/hip08/metrics.json
+++ b/tools/perf/pmu-events/arch/arm64/hisilicon/hip08/metrics.json
@@ -28,7 +28,7 @@
"MetricName": "backend_bound"
},
{
- "MetricExpr": "armv8_pmuv3_0@event\\=0x201d@ / CPU_CYCLES",
+ "MetricExpr": "FETCH_BUBBLE_EXCEEDMIW / CPU_CYCLES",
"PublicDescription": "Fetch latency bound L2 topdown metric",
"BriefDescription": "Fetch latency bound L2 topdown metric",
"MetricGroup": "TopDownL2",
@@ -42,7 +42,7 @@
"MetricName": "fetch_bandwidth_bound"
},
{
- "MetricExpr": "(bad_speculation * BR_MIS_PRED) / (BR_MIS_PRED + armv8_pmuv3_0@event\\=0x2013@)",
+ "MetricExpr": "(bad_speculation * BR_MIS_PRED) / (BR_MIS_PRED + OOO_FLUSH)",
"PublicDescription": "Branch mispredicts L2 topdown metric",
"BriefDescription": "Branch mispredicts L2 topdown metric",
"MetricGroup": "TopDownL2",
@@ -56,14 +56,14 @@
"MetricName": "machine_clears"
},
{
- "MetricExpr": "(EXE_STALL_CYCLE - (MEM_STALL_ANYLOAD + armv8_pmuv3_0@event\\=0x7005@)) / CPU_CYCLES",
+ "MetricExpr": "(EXE_STALL_CYCLE - (MEM_STALL_ANYLOAD + MEM_STALL_ANYSTORE)) / CPU_CYCLES",
"PublicDescription": "Core bound L2 topdown metric",
"BriefDescription": "Core bound L2 topdown metric",
"MetricGroup": "TopDownL2",
"MetricName": "core_bound"
},
{
- "MetricExpr": "(MEM_STALL_ANYLOAD + armv8_pmuv3_0@event\\=0x7005@) / CPU_CYCLES",
+ "MetricExpr": "(MEM_STALL_ANYLOAD + MEM_STALL_ANYSTORE) / CPU_CYCLES",
"PublicDescription": "Memory bound L2 topdown metric",
"BriefDescription": "Memory bound L2 topdown metric",
"MetricGroup": "TopDownL2",
@@ -91,53 +91,53 @@
"MetricName": "bp_misp_flush"
},
{
- "MetricExpr": "(armv8_pmuv3_0@event\\=0x2013@ * 5) / CPU_CYCLES",
+ "MetricExpr": "(OOO_FLUSH * 5) / CPU_CYCLES",
"PublicDescription": "OOO flush L3 topdown metric",
"BriefDescription": "OOO flush L3 topdown metric",
"MetricGroup": "TopDownL3",
- "MetricName": "ooo_flush"
+ "MetricName": "ooo_flush_ratio"
},
{
- "MetricExpr": "(armv8_pmuv3_0@event\\=0x1001@ * 5) / CPU_CYCLES",
+ "MetricExpr": "(IF_BP_PRED_BR_SP * 5) / CPU_CYCLES",
"PublicDescription": "Static predictor flush L3 topdown metric",
"BriefDescription": "Static predictor flush L3 topdown metric",
"MetricGroup": "TopDownL3",
"MetricName": "sp_flush"
},
{
- "MetricExpr": "armv8_pmuv3_0@event\\=0x1010@ / BR_MIS_PRED",
+ "MetricExpr": "IF_BP_MISP_BR_IND / BR_MIS_PRED",
"PublicDescription": "Indirect branch L3 topdown metric",
"BriefDescription": "Indirect branch L3 topdown metric",
"MetricGroup": "TopDownL3",
"MetricName": "indirect_branch"
},
{
- "MetricExpr": "(armv8_pmuv3_0@event\\=0x1013@ + armv8_pmuv3_0@event\\=0x1016@) / BR_MIS_PRED",
+ "MetricExpr": "(IF_BP_MISP_BR_BLR + IF_BP_MISP_BR_BL) / BR_MIS_PRED",
"PublicDescription": "Push branch L3 topdown metric",
"BriefDescription": "Push branch L3 topdown metric",
"MetricGroup": "TopDownL3",
"MetricName": "push_branch"
},
{
- "MetricExpr": "armv8_pmuv3_0@event\\=0x100d@ / BR_MIS_PRED",
+ "MetricExpr": "IF_BP_MISP_BR_RET / BR_MIS_PRED",
"PublicDescription": "Pop branch L3 topdown metric",
"BriefDescription": "Pop branch L3 topdown metric",
"MetricGroup": "TopDownL3",
"MetricName": "pop_branch"
},
{
- "MetricExpr": "(BR_MIS_PRED - armv8_pmuv3_0@event\\=0x1010@ - armv8_pmuv3_0@event\\=0x1013@ - armv8_pmuv3_0@event\\=0x1016@ - armv8_pmuv3_0@event\\=0x100d@) / BR_MIS_PRED",
+ "MetricExpr": "(BR_MIS_PRED - IF_BP_MISP_BR_IND - IF_BP_MISP_BR_BLR - IF_BP_MISP_BR_BL - IF_BP_MISP_BR_RET) / BR_MIS_PRED",
"PublicDescription": "Other branch L3 topdown metric",
"BriefDescription": "Other branch L3 topdown metric",
"MetricGroup": "TopDownL3",
"MetricName": "other_branch"
},
{
- "MetricExpr": "armv8_pmuv3_0@event\\=0x2012@ / armv8_pmuv3_0@event\\=0x2013@",
+ "MetricExpr": "NUKE_FLUSH / OOO_FLUSH",
"PublicDescription": "Nuke flush L3 topdown metric",
"BriefDescription": "Nuke flush L3 topdown metric",
"MetricGroup": "TopDownL3",
- "MetricName": "nuke_flush"
+ "MetricName": "nuke_flush_ratio"
},
{
"MetricExpr": "1 - nuke_flush",
@@ -147,53 +147,53 @@
"MetricName": "other_flush"
},
{
- "MetricExpr": "armv8_pmuv3_0@event\\=0x2010@ / CPU_CYCLES",
+ "MetricExpr": "SYNC_STALL / CPU_CYCLES",
"PublicDescription": "Sync stall L3 topdown metric",
"BriefDescription": "Sync stall L3 topdown metric",
"MetricGroup": "TopDownL3",
- "MetricName": "sync_stall"
+ "MetricName": "sync_stall_ratio"
},
{
- "MetricExpr": "armv8_pmuv3_0@event\\=0x2004@ / CPU_CYCLES",
+ "MetricExpr": "ROB_STALL / CPU_CYCLES",
"PublicDescription": "Rob stall L3 topdown metric",
"BriefDescription": "Rob stall L3 topdown metric",
"MetricGroup": "TopDownL3",
- "MetricName": "rob_stall"
+ "MetricName": "rob_stall_ratio"
},
{
- "MetricExpr": "(armv8_pmuv3_0@event\\=0x2006@ + armv8_pmuv3_0@event\\=0x2007@ + armv8_pmuv3_0@event\\=0x2008@) / CPU_CYCLES",
+ "MetricExpr": "(INT_PTAG_STALL + CC_PTAG_STALL + VFP_PTAG_STALL) / CPU_CYCLES",
"PublicDescription": "Ptag stall L3 topdown metric",
"BriefDescription": "Ptag stall L3 topdown metric",
"MetricGroup": "TopDownL3",
"MetricName": "ptag_stall"
},
{
- "MetricExpr": "armv8_pmuv3_0@event\\=0x201e@ / CPU_CYCLES",
+ "MetricExpr": "SAVEOP_QUEUE_STALL / CPU_CYCLES",
"PublicDescription": "SaveOpQ stall L3 topdown metric",
"BriefDescription": "SaveOpQ stall L3 topdown metric",
"MetricGroup": "TopDownL3",
"MetricName": "saveopq_stall"
},
{
- "MetricExpr": "armv8_pmuv3_0@event\\=0x2005@ / CPU_CYCLES",
+ "MetricExpr": "PCBUF_STALL / CPU_CYCLES",
"PublicDescription": "PC buffer stall L3 topdown metric",
"BriefDescription": "PC buffer stall L3 topdown metric",
"MetricGroup": "TopDownL3",
"MetricName": "pc_buffer_stall"
},
{
- "MetricExpr": "armv8_pmuv3_0@event\\=0x7002@ / CPU_CYCLES",
+ "MetricExpr": "EXE_STALL_DIV / CPU_CYCLES",
"PublicDescription": "Divider L3 topdown metric",
"BriefDescription": "Divider L3 topdown metric",
"MetricGroup": "TopDownL3",
"MetricName": "divider"
},
{
- "MetricExpr": "armv8_pmuv3_0@event\\=0x7003@ / CPU_CYCLES",
+ "MetricExpr": "FSU_STALL / CPU_CYCLES",
"PublicDescription": "FSU stall L3 topdown metric",
"BriefDescription": "FSU stall L3 topdown metric",
"MetricGroup": "TopDownL3",
- "MetricName": "fsu_stall"
+ "MetricName": "fsu_stall_ratio"
},
{
"MetricExpr": "core_bound - divider - fsu_stall",
@@ -224,7 +224,7 @@
"MetricName": "mem_bound"
},
{
- "MetricExpr": "armv8_pmuv3_0@event\\=0x7005@ / CPU_CYCLES",
+ "MetricExpr": "MEM_STALL_ANYSTORE / CPU_CYCLES",
"PublicDescription": "Store bound L3 topdown metric",
"BriefDescription": "Store bound L3 topdown metric",
"MetricGroup": "TopDownL3",
--
2.17.1
^ permalink raw reply related [flat|nested] 8+ messages in thread* Re: [PATCH v2 3/3] perf vendor events arm64: Use event name instead of event code
2022-10-21 10:50 ` [PATCH v2 3/3] perf vendor events arm64: Use event name instead of event code Shang XiaoJing
@ 2022-10-26 9:25 ` John Garry
0 siblings, 0 replies; 8+ messages in thread
From: John Garry @ 2022-10-26 9:25 UTC (permalink / raw)
To: Shang XiaoJing, will, james.clark, mike.leach, leo.yan, peterz,
mingo, acme, mark.rutland, alexander.shishkin, jolsa, namhyung,
kjain, linux-arm-kernel, linux-perf-users
On 21/10/2022 11:50, Shang XiaoJing wrote:
> Use the event name instead of the corresponding event code for more
> clear, which makes the result of perf more readable.
>
> Signed-off-by: Shang XiaoJing<shangxiaojing@huawei.com>
> Acked-by: James Clark<james.clark@arm.com>
Uh, you prob could have added these in patch 2/3. anyway,
Reviewed-by: John Garry <john.garry@huawei.com>
^ permalink raw reply [flat|nested] 8+ messages in thread