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X-IronPort-AV: E=McAfee;i="6600,9927,10999"; a="3764687" X-IronPort-AV: E=Sophos;i="6.06,196,1705392000"; d="scan'208";a="3764687" Received: from orviesa007.jf.intel.com ([10.64.159.147]) by orvoesa113.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 01 Mar 2024 05:53:30 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.06,196,1705392000"; d="scan'208";a="8603825" Received: from linux.intel.com ([10.54.29.200]) by orviesa007.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 01 Mar 2024 05:53:31 -0800 Received: from [10.209.156.90] (kliang2-mobl1.ccr.corp.intel.com [10.209.156.90]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by linux.intel.com (Postfix) with ESMTPS id 57568580DA4; Fri, 1 Mar 2024 05:53:27 -0800 (PST) Message-ID: Date: Fri, 1 Mar 2024 08:53:26 -0500 Precedence: bulk X-Mailing-List: linux-perf-users@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v1 13/20] perf jevents: Add cycles breakdown metric for Intel To: Ian Rogers Cc: Perry Taylor , Samantha Alt , Caleb Biggers , Weilin Wang , Edward Baker , Andi Kleen , Peter Zijlstra , Ingo Molnar , Arnaldo Carvalho de Melo , Namhyung Kim , Mark Rutland , Alexander Shishkin , Jiri Olsa , Adrian Hunter , John Garry , Jing Zhang , Thomas Richter , James Clark , linux-kernel@vger.kernel.org, linux-perf-users@vger.kernel.org, Stephane Eranian References: <20240229001806.4158429-1-irogers@google.com> <20240229001806.4158429-14-irogers@google.com> Content-Language: en-US From: "Liang, Kan" In-Reply-To: Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit On 2024-02-29 7:48 p.m., Ian Rogers wrote: > On Thu, Feb 29, 2024 at 1:30 PM Liang, Kan wrote: >> >> >> >> On 2024-02-28 7:17 p.m., Ian Rogers wrote: >>> Breakdown cycles to user, kernel and guest. >>> >>> Signed-off-by: Ian Rogers >>> --- >>> tools/perf/pmu-events/intel_metrics.py | 18 ++++++++++++++++++ >>> 1 file changed, 18 insertions(+) >>> >>> diff --git a/tools/perf/pmu-events/intel_metrics.py b/tools/perf/pmu-events/intel_metrics.py >>> index dae44d296861..fef40969a4b8 100755 >>> --- a/tools/perf/pmu-events/intel_metrics.py >>> +++ b/tools/perf/pmu-events/intel_metrics.py >>> @@ -26,6 +26,23 @@ core_cycles = Event("CPU_CLK_UNHALTED.THREAD_P_ANY", >>> smt_cycles = Select(core_cycles / 2, Literal("#smt_on"), core_cycles) >>> >>> >>> +def Cycles() -> MetricGroup: >>> + cyc_k = Event("cycles:kHh") >>> + cyc_g = Event("cycles:G") >>> + cyc_u = Event("cycles:uH") >>> + cyc = cyc_k + cyc_g + cyc_u >>> + >>> + return MetricGroup("cycles", [ >>> + Metric("cycles_total", "Total number of cycles", cyc, "cycles"), >>> + Metric("cycles_user", "User cycles as a percentage of all cycles", >>> + d_ratio(cyc_u, cyc), "100%"), >>> + Metric("cycles_kernel", "Kernel cycles as a percentage of all cycles", >>> + d_ratio(cyc_k, cyc), "100%"), >>> + Metric("cycles_guest", "Hypervisor guest cycles as a percentage of all cycles", >>> + d_ratio(cyc_g, cyc), "100%"), >>> + ], description = "cycles breakdown per privilege level (users, kernel, guest)") >>> + >>> + >>> def Idle() -> Metric: >>> cyc = Event("msr/mperf/") >>> tsc = Event("msr/tsc/") >>> @@ -770,6 +787,7 @@ def IntelLdSt() -> Optional[MetricGroup]: >>> >>> >>> all_metrics = MetricGroup("", [ >>> + Cycles(), >> >> The metric group seem exactly the same on AMD and ARM. Maybe we can have >> tools/perf/pmu-events/common_metrics.py for all the common metrics. > > Agreed. I think we can drop cycles in the three sets and then once > then do the common_metrics.py as a follow up. > Sounds good to me. Thanks, Kan > Thanks, > Ian > >> Thanks, >> Kan >> >>> Idle(), >>> Rapl(), >>> Smi(), >