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X-CSE-ConnectionGUID: vja2KxOtRTW4YPMtfF1Yew== X-CSE-MsgGUID: dGNqeXcqQ4yYK3rLfS8ROg== X-IronPort-AV: E=McAfee;i="6800,10657,11635"; a="67160280" X-IronPort-AV: E=Sophos;i="6.20,258,1758610800"; d="scan'208";a="67160280" Received: from fmviesa009.fm.intel.com ([10.60.135.149]) by orvoesa110.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 07 Dec 2025 22:10:51 -0800 X-CSE-ConnectionGUID: OpqZbjoqSGy6jxlsYl1Zvw== X-CSE-MsgGUID: 3hLHdUyQQAmh0tye3JLACg== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.20,258,1758610800"; d="scan'208";a="196313275" Received: from dapengmi-mobl1.ccr.corp.intel.com (HELO [10.124.240.12]) ([10.124.240.12]) by fmviesa009-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 07 Dec 2025 22:10:45 -0800 Message-ID: Date: Mon, 8 Dec 2025 14:10:42 +0800 Precedence: bulk X-Mailing-List: linux-perf-users@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [Patch v5 08/19] perf/x86: Enable XMM sampling using sample_simd_vec_reg_* fields To: Peter Zijlstra Cc: Ingo Molnar , Arnaldo Carvalho de Melo , Namhyung Kim , Thomas Gleixner , Dave Hansen , Ian Rogers , Adrian Hunter , Jiri Olsa , Alexander Shishkin , Andi Kleen , Eranian Stephane , Mark Rutland , broonie@kernel.org, Ravi Bangoria , linux-kernel@vger.kernel.org, linux-perf-users@vger.kernel.org, Zide Chen , Falcon Thomas , Dapeng Mi , Xudong Hao , Kan Liang References: <20251203065500.2597594-1-dapeng1.mi@linux.intel.com> <20251203065500.2597594-9-dapeng1.mi@linux.intel.com> <20251205112516.GU2528459@noisy.programming.kicks-ass.net> Content-Language: en-US From: "Mi, Dapeng" In-Reply-To: <20251205112516.GU2528459@noisy.programming.kicks-ass.net> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit On 12/5/2025 7:25 PM, Peter Zijlstra wrote: > On Wed, Dec 03, 2025 at 02:54:49PM +0800, Dapeng Mi wrote: > >> diff --git a/arch/x86/include/uapi/asm/perf_regs.h b/arch/x86/include/uapi/asm/perf_regs.h >> index 7c9d2bb3833b..c3862e5fdd6d 100644 >> --- a/arch/x86/include/uapi/asm/perf_regs.h >> +++ b/arch/x86/include/uapi/asm/perf_regs.h >> @@ -55,4 +55,21 @@ enum perf_event_x86_regs { >> >> #define PERF_REG_EXTENDED_MASK (~((1ULL << PERF_REG_X86_XMM0) - 1)) >> >> +enum { >> + PERF_REG_X86_XMM, >> + PERF_REG_X86_MAX_SIMD_REGS, >> +}; >> + >> +enum { >> + PERF_X86_SIMD_XMM_REGS = 16, >> + PERF_X86_SIMD_VEC_REGS_MAX = PERF_X86_SIMD_XMM_REGS, >> +}; >> + >> +#define PERF_X86_SIMD_VEC_MASK GENMASK_ULL(PERF_X86_SIMD_VEC_REGS_MAX - 1, 0) >> + >> +enum { >> + PERF_X86_XMM_QWORDS = 2, >> + PERF_X86_SIMD_QWORDS_MAX = PERF_X86_XMM_QWORDS, >> +}; >> + >> #endif /* _ASM_X86_PERF_REGS_H */ > I don't understand this bit -- the next few patches add to it for YMM > and ZMM, but what's the point? I don't see why this is needed at all, > let alone why it needs to be UABI. Currently these bits are only used in user space perf tools. Let me remove it from the header perf_regs.h. >