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X-CSE-ConnectionGUID: c/SNDqcCRau9M/LgO6szDA== X-CSE-MsgGUID: YVlPe/SFQZmQoJguj2IsmA== X-IronPort-AV: E=McAfee;i="6600,9927,11066"; a="11075454" X-IronPort-AV: E=Sophos;i="6.08,143,1712646000"; d="scan'208";a="11075454" Received: from orviesa007.jf.intel.com ([10.64.159.147]) by orvoesa108.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 07 May 2024 14:40:16 -0700 X-CSE-ConnectionGUID: jkXc046ETtetd+nqogpjcA== X-CSE-MsgGUID: CqxJUta2QbmxYjSKhZFigQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.08,143,1712646000"; d="scan'208";a="29190963" Received: from soc-cp83kr3.jf.intel.com (HELO [10.24.10.59]) ([10.24.10.59]) by orviesa007-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 07 May 2024 14:40:16 -0700 Message-ID: Date: Tue, 7 May 2024 14:40:15 -0700 Precedence: bulk X-Mailing-List: linux-perf-users@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v2 12/54] perf: x86: Add x86 function to switch PMI handler To: Mingwei Zhang , Sean Christopherson , Paolo Bonzini , Xiong Zhang , Dapeng Mi , Kan Liang , Zhenyu Wang , Manali Shukla , Sandipan Das Cc: Jim Mattson , Stephane Eranian , Ian Rogers , Namhyung Kim , gce-passthrou-pmu-dev@google.com, Samantha Alt , Zhiyuan Lv , Yanfei Xu , maobibo , Like Xu , Peter Zijlstra , kvm@vger.kernel.org, linux-perf-users@vger.kernel.org References: <20240506053020.3911940-1-mizhang@google.com> <20240506053020.3911940-13-mizhang@google.com> Content-Language: en-US From: "Chen, Zide" In-Reply-To: <20240506053020.3911940-13-mizhang@google.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit On 5/5/2024 10:29 PM, Mingwei Zhang wrote: > From: Xiong Zhang > > Add x86 specific function to switch PMI handler since passthrough PMU and host > PMU use different interrupt vectors. > > x86_perf_guest_enter() switch PMU vector from NMI to KVM_GUEST_PMI_VECTOR, > and guest LVTPC_MASK value should be reflected onto HW to indicate whether > guest has cleared LVTPC_MASK or not, so guest lvt_pc is passed as parameter. > > x86_perf_guest_exit() switch PMU vector from KVM_GUEST_PMI_VECTOR to NMI. > > Signed-off-by: Xiong Zhang > Signed-off-by: Dapeng Mi > --- > arch/x86/events/core.c | 17 +++++++++++++++++ > arch/x86/include/asm/perf_event.h | 3 +++ > 2 files changed, 20 insertions(+) > > diff --git a/arch/x86/events/core.c b/arch/x86/events/core.c > index 09050641ce5d..8167f2230d3a 100644 > --- a/arch/x86/events/core.c > +++ b/arch/x86/events/core.c > @@ -701,6 +701,23 @@ struct perf_guest_switch_msr *perf_guest_get_msrs(int *nr, void *data) > } > EXPORT_SYMBOL_GPL(perf_guest_get_msrs); > > +void x86_perf_guest_enter(u32 guest_lvtpc) > +{ > + lockdep_assert_irqs_disabled(); > + > + apic_write(APIC_LVTPC, APIC_DM_FIXED | KVM_GUEST_PMI_VECTOR | > + (guest_lvtpc & APIC_LVT_MASKED)); If CONFIG_KVM is not defined, KVM_GUEST_PMI_VECTOR is not available and it causes compiling error.