* [PATCH 1/3] x86/cpu/zhaoxin: Introduce macros for Zhaoxin family numbers
2023-03-23 2:40 [PATCH 0/3] Add PMC support for Zhaoxin Yongfeng architecture silviazhao
@ 2023-03-23 2:40 ` silviazhao
2023-03-23 2:40 ` [PATCH 2/3] perf/x86/zhaoxin: Replace open-coded model number with macros silviazhao
` (2 subsequent siblings)
3 siblings, 0 replies; 5+ messages in thread
From: silviazhao @ 2023-03-23 2:40 UTC (permalink / raw)
To: peterz, mingo, acme, mark.rutland, alexander.shishkin, jolsa,
namhyung, irogers, adrian.hunter, tglx, bp, dave.hansen, x86, hpa,
linux-perf-users, linux-kernel
Cc: cobechen, louisqi, silviazhao, cooperyan
Create zhaoxin-family.h to define Zhaoxin family numbers in one header
file. So we can use the macros instead of open-coded model numbers in
other files.
Signed-off-by: silviazhao <silviazhao-oc@zhaoxin.com>
---
arch/x86/include/asm/zhaoxin-family.h | 19 +++++++++++++++++++
1 file changed, 19 insertions(+)
create mode 100644 arch/x86/include/asm/zhaoxin-family.h
diff --git a/arch/x86/include/asm/zhaoxin-family.h b/arch/x86/include/asm/zhaoxin-family.h
new file mode 100644
index 000000000000..d54e0112207a
--- /dev/null
+++ b/arch/x86/include/asm/zhaoxin-family.h
@@ -0,0 +1,19 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+#ifndef _ASM_X86_ZHAOXIN_FAMILY_H
+#define _ASM_X86_ZHAOXIN_FAMILY_H
+
+/*
+ * The defined symbol names have the following form:
+ * ZHAOXIN_FAM7{OPTFAMILY}_{MICROARCH}
+ * where:
+ * OPTFAMILY Describes the family of CPUs that this belongs to. Default
+ * is assumed to be omitted.
+ * MICROARCH Is the code name for the micro-architecture for this core.
+ */
+
+
+#define ZHAOXIN_FAM7_WUDAOKOU 0x1B
+#define ZHAOXIN_FAM7_LUJIAZUI 0x3B
+#define ZHAOXIN_FAM7_YONGFENG 0x5B
+
+#endif /* _ASM_X86_ZHAOXIN_FAMILY_H */
--
2.17.1
^ permalink raw reply related [flat|nested] 5+ messages in thread* [PATCH 2/3] perf/x86/zhaoxin: Replace open-coded model number with macros
2023-03-23 2:40 [PATCH 0/3] Add PMC support for Zhaoxin Yongfeng architecture silviazhao
2023-03-23 2:40 ` [PATCH 1/3] x86/cpu/zhaoxin: Introduce macros for Zhaoxin family numbers silviazhao
@ 2023-03-23 2:40 ` silviazhao
2023-03-23 2:40 ` [PATCH 3/3] perf/x86/zhaoxin: Add Yongfeng support silviazhao
2023-05-09 8:45 ` [PATCH 0/3] Add PMC support for Zhaoxin Yongfeng architecture silviazhao
3 siblings, 0 replies; 5+ messages in thread
From: silviazhao @ 2023-03-23 2:40 UTC (permalink / raw)
To: peterz, mingo, acme, mark.rutland, alexander.shishkin, jolsa,
namhyung, irogers, adrian.hunter, tglx, bp, dave.hansen, x86, hpa,
linux-perf-users, linux-kernel
Cc: cobechen, louisqi, silviazhao, cooperyan
Replace open-coded family-7 model number in arch/x86/events/zhaoxin/
core.c with the macros defined in zhaoxin-family.h.
Zhaoxin used to use non-canonical name for family 7 processors in
arch/x86/events/zhaoxin/core.c. Replace them with architecture name
to keep consistent with the macros. Following are the correspondences:
ZXD -> Wudaokou
ZXE -> Lujiazui
Signed-off-by: silviazhao <silviazhao-oc@zhaoxin.com>
---
arch/x86/events/zhaoxin/core.c | 25 +++++++++++++------------
1 file changed, 13 insertions(+), 12 deletions(-)
diff --git a/arch/x86/events/zhaoxin/core.c b/arch/x86/events/zhaoxin/core.c
index 3e9acdaeed1e..34ccb214478c 100644
--- a/arch/x86/events/zhaoxin/core.c
+++ b/arch/x86/events/zhaoxin/core.c
@@ -14,6 +14,7 @@
#include <asm/cpufeature.h>
#include <asm/hardirq.h>
+#include <asm/zhaoxin-family.h>
#include <asm/apic.h>
#include "../perf_event.h"
@@ -36,7 +37,7 @@ static struct event_constraint zxc_event_constraints[] __read_mostly = {
EVENT_CONSTRAINT_END
};
-static struct event_constraint zxd_event_constraints[] __read_mostly = {
+static struct event_constraint wudaokou_event_constraints[] __read_mostly = {
FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* retired instructions */
FIXED_EVENT_CONSTRAINT(0x0082, 1), /* unhalted core clock cycles */
@@ -44,7 +45,7 @@ static struct event_constraint zxd_event_constraints[] __read_mostly = {
EVENT_CONSTRAINT_END
};
-static __initconst const u64 zxd_hw_cache_event_ids
+static __initconst const u64 wudaokou_hw_cache_event_ids
[PERF_COUNT_HW_CACHE_MAX]
[PERF_COUNT_HW_CACHE_OP_MAX]
[PERF_COUNT_HW_CACHE_RESULT_MAX] = {
@@ -148,7 +149,7 @@ static __initconst const u64 zxd_hw_cache_event_ids
},
};
-static __initconst const u64 zxe_hw_cache_event_ids
+static __initconst const u64 lujiazui_hw_cache_event_ids
[PERF_COUNT_HW_CACHE_MAX]
[PERF_COUNT_HW_CACHE_OP_MAX]
[PERF_COUNT_HW_CACHE_RESULT_MAX] = {
@@ -471,7 +472,7 @@ static const struct x86_pmu zhaoxin_pmu __initconst = {
.max_events = ARRAY_SIZE(zx_pmon_event_map),
.apic = 1,
/*
- * For zxd/zxe, read/write operation for PMCx MSR is 48 bits.
+ * For wudaokou/lujiazui, read/write operation for PMCx MSR is 48 bits.
*/
.max_period = (1ULL << 47) - 1,
.get_event_constraints = zhaoxin_get_event_constraints,
@@ -573,27 +574,27 @@ __init int zhaoxin_pmu_init(void)
X86_CONFIG(.event = 0x0f, .umask = 0x04, .inv = 0, .cmask = 0);
switch (boot_cpu_data.x86_model) {
- case 0x1b:
- memcpy(hw_cache_event_ids, zxd_hw_cache_event_ids,
+ case ZHAOXIN_FAM7_WUDAOKOU:
+ memcpy(hw_cache_event_ids, wudaokou_hw_cache_event_ids,
sizeof(hw_cache_event_ids));
- x86_pmu.event_constraints = zxd_event_constraints;
+ x86_pmu.event_constraints = wudaokou_event_constraints;
zx_pmon_event_map[PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = 0x0700;
zx_pmon_event_map[PERF_COUNT_HW_BRANCH_MISSES] = 0x0709;
- pr_cont("ZXD events, ");
+ pr_cont("Wudaokou events, ");
break;
- case 0x3b:
- memcpy(hw_cache_event_ids, zxe_hw_cache_event_ids,
+ case ZHAOXIN_FAM7_LUJIAZUI:
+ memcpy(hw_cache_event_ids, lujiazui_hw_cache_event_ids,
sizeof(hw_cache_event_ids));
- x86_pmu.event_constraints = zxd_event_constraints;
+ x86_pmu.event_constraints = wudaokou_event_constraints;
zx_pmon_event_map[PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = 0x0028;
zx_pmon_event_map[PERF_COUNT_HW_BRANCH_MISSES] = 0x0029;
- pr_cont("ZXE events, ");
+ pr_cont("Lujiazui events, ");
break;
default:
return -ENODEV;
--
2.17.1
^ permalink raw reply related [flat|nested] 5+ messages in thread* [PATCH 3/3] perf/x86/zhaoxin: Add Yongfeng support
2023-03-23 2:40 [PATCH 0/3] Add PMC support for Zhaoxin Yongfeng architecture silviazhao
2023-03-23 2:40 ` [PATCH 1/3] x86/cpu/zhaoxin: Introduce macros for Zhaoxin family numbers silviazhao
2023-03-23 2:40 ` [PATCH 2/3] perf/x86/zhaoxin: Replace open-coded model number with macros silviazhao
@ 2023-03-23 2:40 ` silviazhao
2023-05-09 8:45 ` [PATCH 0/3] Add PMC support for Zhaoxin Yongfeng architecture silviazhao
3 siblings, 0 replies; 5+ messages in thread
From: silviazhao @ 2023-03-23 2:40 UTC (permalink / raw)
To: peterz, mingo, acme, mark.rutland, alexander.shishkin, jolsa,
namhyung, irogers, adrian.hunter, tglx, bp, dave.hansen, x86, hpa,
linux-perf-users, linux-kernel
Cc: cobechen, louisqi, silviazhao, cooperyan
Add support for Yongfeng which is Zhaoxin's successor microarchitecture
to Lujiazui.
Remove PERF_COUNT_HW_CACHE_REFERENCES and PERF_COUNT_HW_CACHE_MISSES
from global zx_pmon_event_map, since the cache hierarchy was changed
from Yongfeng, and these pmc event map changed too.
Add PERF_COUNT_HW_BRANCH_INSTRUCTIONS and PERF_COUNT_HW_BRANCH_MISSES
to global zx_pmon_event_map, since these two events will keep
consistent for Lujiazui and later.
Signed-off-by: silviazhao <silviazhao-oc@zhaoxin.com>
---
arch/x86/events/zhaoxin/core.c | 30 +++++++++++++++++++++++++-----
1 file changed, 25 insertions(+), 5 deletions(-)
diff --git a/arch/x86/events/zhaoxin/core.c b/arch/x86/events/zhaoxin/core.c
index 34ccb214478c..634aa0c4a8c6 100644
--- a/arch/x86/events/zhaoxin/core.c
+++ b/arch/x86/events/zhaoxin/core.c
@@ -20,15 +20,15 @@
#include "../perf_event.h"
/*
- * Zhaoxin PerfMon, used on zxc and later.
+ * Zhaoxin PerfMon, used on Lujiazui and later.
*/
static u64 zx_pmon_event_map[PERF_COUNT_HW_MAX] __read_mostly = {
[PERF_COUNT_HW_CPU_CYCLES] = 0x0082,
[PERF_COUNT_HW_INSTRUCTIONS] = 0x00c0,
- [PERF_COUNT_HW_CACHE_REFERENCES] = 0x0515,
- [PERF_COUNT_HW_CACHE_MISSES] = 0x051a,
[PERF_COUNT_HW_BUS_CYCLES] = 0x0083,
+ [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = 0x0028,
+ [PERF_COUNT_HW_BRANCH_MISSES] = 0x0029,
};
static struct event_constraint zxc_event_constraints[] __read_mostly = {
@@ -560,6 +560,8 @@ __init int zhaoxin_pmu_init(void)
zx_pmon_event_map[PERF_COUNT_HW_CACHE_REFERENCES] = 0;
zx_pmon_event_map[PERF_COUNT_HW_CACHE_MISSES] = 0;
zx_pmon_event_map[PERF_COUNT_HW_BUS_CYCLES] = 0;
+ zx_pmon_event_map[PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = 0;
+ zx_pmon_event_map[PERF_COUNT_HW_BRANCH_MISSES] = 0;
pr_cont("ZXC events, ");
break;
@@ -580,6 +582,9 @@ __init int zhaoxin_pmu_init(void)
x86_pmu.event_constraints = wudaokou_event_constraints;
+ zx_pmon_event_map[PERF_COUNT_HW_CACHE_REFERENCES] = 0x0515,
+ zx_pmon_event_map[PERF_COUNT_HW_CACHE_MISSES] = 0x051a,
+
zx_pmon_event_map[PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = 0x0700;
zx_pmon_event_map[PERF_COUNT_HW_BRANCH_MISSES] = 0x0709;
@@ -591,11 +596,26 @@ __init int zhaoxin_pmu_init(void)
x86_pmu.event_constraints = wudaokou_event_constraints;
- zx_pmon_event_map[PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = 0x0028;
- zx_pmon_event_map[PERF_COUNT_HW_BRANCH_MISSES] = 0x0029;
+ zx_pmon_event_map[PERF_COUNT_HW_CACHE_REFERENCES] = 0x0515,
+ zx_pmon_event_map[PERF_COUNT_HW_CACHE_MISSES] = 0x051a,
pr_cont("Lujiazui events, ");
break;
+ case ZHAOXIN_FAM7_YONGFENG:
+ zx_pmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_FRONTEND] =
+ X86_CONFIG(.event = 0x02, .umask = 0x01, .inv = 0x01,
+ .cmask = 0x01);
+
+ memcpy(hw_cache_event_ids, lujiazui_hw_cache_event_ids,
+ sizeof(hw_cache_event_ids));
+
+ x86_pmu.event_constraints = wudaokou_event_constraints;
+
+ zx_pmon_event_map[PERF_COUNT_HW_CACHE_REFERENCES] = 0x051a;
+ zx_pmon_event_map[PERF_COUNT_HW_CACHE_MISSES] = 0;
+
+ pr_cont("Yongfeng events, ");
+ break;
default:
return -ENODEV;
}
--
2.17.1
^ permalink raw reply related [flat|nested] 5+ messages in thread* Re: [PATCH 0/3] Add PMC support for Zhaoxin Yongfeng architecture
2023-03-23 2:40 [PATCH 0/3] Add PMC support for Zhaoxin Yongfeng architecture silviazhao
` (2 preceding siblings ...)
2023-03-23 2:40 ` [PATCH 3/3] perf/x86/zhaoxin: Add Yongfeng support silviazhao
@ 2023-05-09 8:45 ` silviazhao
3 siblings, 0 replies; 5+ messages in thread
From: silviazhao @ 2023-05-09 8:45 UTC (permalink / raw)
To: peterz, mingo, acme, mark.rutland, alexander.shishkin, jolsa,
namhyung, irogers, adrian.hunter, tglx, bp, dave.hansen, x86, hpa,
linux-perf-users, linux-kernel
Cc: cobechen, louisqi, cooperyan, Silvia Zhao(BJ-RD)
On 2023/3/23 10:40, silviazhao wrote:
> Add PMC support for Zhaoxin Yongfeng architecture.
> Dave Hansen suggested to use macros instead of open-coded model numbers.
> So create arch/x86/include/asm/zhaoxin-family.h to introduce macros for
> Zhaoxin family numbers.
> https://lkml.org/lkml/2023/3/16/841
>
> silviazhao (3):
> x86/cpu/zhaoxin: Introduce macros for Zhaoxin family numbers
> perf/x86/zhaoxin: Replace open-coded model number with macros
> perf/x86/zhaoxin: Add Yongfeng support
>
> arch/x86/events/zhaoxin/core.c | 55 ++++++++++++++++++---------
> arch/x86/include/asm/zhaoxin-family.h | 19 +++++++++
> 2 files changed, 57 insertions(+), 17 deletions(-)
> create mode 100644 arch/x86/include/asm/zhaoxin-family.h
>
Is there anything that needs to be modified in this patch set? Please
let me know.
Thx.
^ permalink raw reply [flat|nested] 5+ messages in thread