Re: Some questions about using the perf tool in ARM-SPE

[James Clark <james.clark@arm.com>]

On 03/07/2023 09:18, Suzuki K Poulose wrote:
> Hi Leo
> On 14/06/2023 02:21, Leo Yan wrote:
>> Hi,
>>
>> On Tue, Jun 13, 2023 at 09:23:33PM +0800, 蔡沅信 wrote:
>>> OK
>>> I have a new discovery that c2c seems to support only certain Arm
>>> Neoverse (N1/N2/V1) CPUs, I wonder if cortex-X4 could support it?
>>
>> Based on Cortex-X4 TRM [1], we can see Cortex-X4 has the same SPE data
>> source packet format with Neoverse CPUs.  In theory, we can add
>> Cortex-X4's MIDR into the neoverse_spe[] array in
>> tools/perf/util/arm-spe.c to support Cortex-X4.
>>
>> Linux master branch misses the definition for Cortex-X4's MIDR [2],
>> Mark.R / Suzuki / James, could you confirm if Arm has plan or already
>> has patches for enabling Cortex-X4's MIDR?
>>
> 
> Is there a particular reason why need this in the kernel ? Usual
> policy is, kernel needs to distinguish an MIDR, only if it ever
> needs to. e.g, a CPU erratum specific to the MIDR.
> 
> Suzuki>

This is on the tool side rather than in the kernel. But yes, if the data
source encoding is the same as the existing ones please send a patch
adding X4's MIDR to the list.

Thanks
James