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From: Andrew Cooper <andrew.cooper3@citrix.com>
To: Konrad Rzeszutek Wilk <konrad.wilk@oracle.com>,
	"Xin Li (Intel)" <xin@zytor.com>
Cc: linux-kernel@vger.kernel.org, linux-perf-users@vger.kernel.org,
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Subject: Re: [RFC PATCH v1 10/15] KVM: VMX: Use WRMSRNS or its immediate form when available
Date: Mon, 31 Mar 2025 21:41:41 +0100	[thread overview]
Message-ID: <fde11fbb-4b3f-44f1-90cf-6aaefb6bb7c1@citrix.com> (raw)
In-Reply-To: <Z-r6qxmk7niRssee@char.us.oracle.com>

On 31/03/2025 9:27 pm, Konrad Rzeszutek Wilk wrote:
> On Mon, Mar 31, 2025 at 01:22:46AM -0700, Xin Li (Intel) wrote:
>> Signed-off-by: Xin Li (Intel) <xin@zytor.com>
>> ---
>>  arch/x86/include/asm/msr-index.h |  6 ++++++
>>  arch/x86/kvm/vmx/vmenter.S       | 28 ++++++++++++++++++++++++----
>>  2 files changed, 30 insertions(+), 4 deletions(-)
>>
>> diff --git a/arch/x86/include/asm/msr-index.h b/arch/x86/include/asm/msr-index.h
>> index e6134ef2263d..04244c3ba374 100644
>> --- a/arch/x86/include/asm/msr-index.h
>> +++ b/arch/x86/include/asm/msr-index.h
>> @@ -1226,4 +1226,10 @@
>>  						* a #GP
>>  						*/
>>  
>> +/* Instruction opcode for WRMSRNS supported in binutils >= 2.40 */
>> +#define ASM_WRMSRNS		_ASM_BYTES(0x0f,0x01,0xc6)
>> +
>> +/* Instruction opcode for the immediate form RDMSR/WRMSRNS */
>> +#define ASM_WRMSRNS_RAX		_ASM_BYTES(0xc4,0xe7,0x7a,0xf6,0xc0)
>> +
>>  #endif /* _ASM_X86_MSR_INDEX_H */
>> diff --git a/arch/x86/kvm/vmx/vmenter.S b/arch/x86/kvm/vmx/vmenter.S
>> index f6986dee6f8c..9fae43723c44 100644
>> --- a/arch/x86/kvm/vmx/vmenter.S
>> +++ b/arch/x86/kvm/vmx/vmenter.S
>> @@ -64,6 +64,29 @@
>>  	RET
>>  .endm
>>  
>> +/*
>> + * Write EAX to MSR_IA32_SPEC_CTRL.
>> + *
>> + * Choose the best WRMSR instruction based on availability.
>> + *
>> + * Replace with 'wrmsrns' and 'wrmsrns %rax, $MSR_IA32_SPEC_CTRL' once binutils support them.
>> + */
>> +.macro WRITE_EAX_TO_MSR_IA32_SPEC_CTRL
>> +	ALTERNATIVE_2 __stringify(mov $MSR_IA32_SPEC_CTRL, %ecx;		\
>> +				  xor %edx, %edx;				\
>> +				  mov %edi, %eax;				\
>> +				  ds wrmsr),					\
>> +		      __stringify(mov $MSR_IA32_SPEC_CTRL, %ecx;		\
>> +				  xor %edx, %edx;				\
>> +				  mov %edi, %eax;				\
>> +				  ASM_WRMSRNS),					\
>> +		      X86_FEATURE_WRMSRNS,					\
>> +		      __stringify(xor %_ASM_AX, %_ASM_AX;			\
>> +				  mov %edi, %eax;				\
>> +				  ASM_WRMSRNS_RAX; .long MSR_IA32_SPEC_CTRL),	\
>> +		      X86_FEATURE_MSR_IMM
>> +.endm
>> +
>>  .section .noinstr.text, "ax"
>>  
>>  /**
>> @@ -123,10 +146,7 @@ SYM_FUNC_START(__vmx_vcpu_run)
>>  	movl PER_CPU_VAR(x86_spec_ctrl_current), %esi
>>  	cmp %edi, %esi
>>  	je .Lspec_ctrl_done
>> -	mov $MSR_IA32_SPEC_CTRL, %ecx
>> -	xor %edx, %edx
>> -	mov %edi, %eax
>> -	wrmsr
> Is that the right path forward?
>
> That is replace the MSR write to disable speculative execution with a
> non-serialized WRMSR? Doesn't that mean the WRMSRNS is speculative?

MSR_SPEC_CTRL is explicitly non-serialising, even with a plain WRMSR.

non-serialising != non-speculative.

Although WRMSRNS's precise statement on the matter of
non-speculativeness is woolly, given an intent to optimise it some more
in the future.

~Andrew

  parent reply	other threads:[~2025-03-31 20:41 UTC|newest]

Thread overview: 55+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2025-03-31  8:22 [RFC PATCH v1 00/15] MSR refactor with new MSR instructions support Xin Li (Intel)
2025-03-31  8:22 ` [RFC PATCH v1 01/15] x86/msr: Replace __wrmsr() with native_wrmsrl() Xin Li (Intel)
2025-03-31 10:17   ` Ingo Molnar
2025-03-31 20:32     ` H. Peter Anvin
2025-04-01  5:53       ` Xin Li
2025-04-02 15:41         ` Dave Hansen
2025-04-02 15:56           ` H. Peter Anvin
2025-04-09 19:53             ` Ingo Molnar
2025-04-09 19:56               ` Dave Hansen
2025-04-09 20:11                 ` Ingo Molnar
2025-04-01  7:52       ` Ingo Molnar
2025-04-02  3:45         ` Xin Li
2025-04-02  4:10           ` Ingo Molnar
2025-04-02  4:57             ` Xin Li
2025-04-08 17:34             ` Xin Li
2025-04-03  5:09         ` Xin Li
2025-04-03  6:01           ` H. Peter Anvin
2025-04-09 19:17           ` [PATCH] x86/msr: Standardize on 'u32' MSR indices in <asm/msr.h> Ingo Molnar
2025-03-31 21:45   ` [RFC PATCH v1 01/15] x86/msr: Replace __wrmsr() with native_wrmsrl() Andrew Cooper
2025-04-01  5:13     ` H. Peter Anvin
2025-04-01  5:29       ` Xin Li
2025-04-03  7:13     ` Xin Li
2025-03-31  8:22 ` [RFC PATCH v1 02/15] x86/msr: Replace __rdmsr() with native_rdmsrl() Xin Li (Intel)
2025-03-31 10:26   ` Ingo Molnar
2025-03-31  8:22 ` [RFC PATCH v1 03/15] x86/msr: Simplify pmu_msr_{read,write}() Xin Li (Intel)
2025-03-31  8:22 ` [RFC PATCH v1 04/15] x86/msr: Let pv_cpu_ops.write_msr{_safe}() take an u64 instead of two u32 Xin Li (Intel)
2025-03-31  8:22 ` [RFC PATCH v1 05/15] x86/msr: Replace wrmsr(msr, low, 0) with wrmsrl(msr, value) Xin Li (Intel)
2025-03-31  8:22 ` [RFC PATCH v1 06/15] x86/msr: Remove MSR write APIs that take the MSR value in two u32 arguments Xin Li (Intel)
2025-03-31  8:22 ` [RFC PATCH v1 07/15] x86/msr: Remove pmu_msr_{read,write}() Xin Li (Intel)
2025-03-31  8:22 ` [RFC PATCH v1 08/15] x86/cpufeatures: Add a CPU feature bit for MSR immediate form instructions Xin Li (Intel)
2025-03-31  8:22 ` [RFC PATCH v1 09/15] x86/opcode: Add immediate form MSR instructions to x86-opcode-map Xin Li (Intel)
2025-03-31  8:22 ` [RFC PATCH v1 10/15] KVM: VMX: Use WRMSRNS or its immediate form when available Xin Li (Intel)
2025-03-31 20:27   ` Konrad Rzeszutek Wilk
2025-03-31 20:38     ` Borislav Petkov
2025-03-31 20:41     ` Andrew Cooper [this message]
2025-03-31 20:55       ` H. Peter Anvin
2025-03-31 20:45     ` H. Peter Anvin
2025-04-10 23:24   ` Sean Christopherson
2025-04-11 16:18     ` Xin Li
2025-04-11 20:50       ` H. Peter Anvin
2025-04-12  4:28         ` Xin Li
2025-04-11 21:12     ` Jim Mattson
2025-04-12  4:32       ` Xin Li
2025-04-12 23:10         ` H. Peter Anvin
2025-04-14 17:48           ` Xin Li
2025-04-15  6:56             ` H. Peter Anvin
2025-04-15 17:06               ` Xin Li
2025-04-15 17:07                 ` H. Peter Anvin
2025-03-31  8:22 ` [RFC PATCH v1 11/15] x86/extable: Implement EX_TYPE_FUNC_REWIND Xin Li (Intel)
2025-03-31  8:22 ` [RFC PATCH v1 12/15] x86/msr: Use the alternatives mechanism to write MSR Xin Li (Intel)
2025-03-31  8:22 ` [RFC PATCH v1 13/15] x86/msr: Use the alternatives mechanism to read MSR Xin Li (Intel)
2025-04-14 17:13   ` Francesco Lavra
2025-04-17 11:10     ` Xin Li
2025-03-31  8:22 ` [RFC PATCH v1 14/15] x86/extable: Add support for the immediate form MSR instructions Xin Li (Intel)
2025-03-31  8:22 ` [RFC PATCH v1 15/15] x86/msr: Move the ARGS macros after the MSR read/write APIs Xin Li (Intel)

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