From: Colton Lewis <coltonlewis@google.com>
To: kernel test robot <lkp@intel.com>
Cc: kvm@vger.kernel.org, oe-kbuild-all@lists.linux.dev,
pbonzini@redhat.com, corbet@lwn.net, linux@armlinux.org.uk,
catalin.marinas@arm.com, will@kernel.org, maz@kernel.org,
oliver.upton@linux.dev, joey.gouly@arm.com,
suzuki.poulose@arm.com, yuzenghui@huawei.com,
mark.rutland@arm.com, skhan@linuxfoundation.org,
linux-doc@vger.kernel.org, linux-kernel@vger.kernel.org,
linux-arm-kernel@lists.infradead.org, kvmarm@lists.linux.dev,
linux-perf-users@vger.kernel.org,
linux-kselftest@vger.kernel.org
Subject: Re: [PATCH v2 17/23] KVM: arm64: Account for partitioning in PMCR_EL0 access
Date: Mon, 23 Jun 2025 22:11:15 +0000 [thread overview]
Message-ID: <gsntikkm9kho.fsf@coltonlewis-kvm.c.googlers.com> (raw)
In-Reply-To: <202506221711.tFNGpzj4-lkp@intel.com> (message from kernel test robot on Sun, 22 Jun 2025 17:32:31 +0800)
kernel test robot <lkp@intel.com> writes:
> In file included from arch/arm64/include/asm/kvm_host.h:32,
> from include/linux/kvm_host.h:45,
> from arch/arm64/kvm/sys_regs.c:16:
> arch/arm64/include/asm/kvm_pmu.h:236:50: warning: 'struct arm_pmu'
> declared inside parameter list will not be visible outside of this
> definition or declaration
> static inline bool kvm_pmu_is_partitioned(struct arm_pmu *pmu)
> ^~~~~~~
> arch/arm64/include/asm/kvm_pmu.h:241:52: warning: 'struct arm_pmu'
> declared inside parameter list will not be visible outside of this
> definition or declaration
> static inline u64 kvm_pmu_host_counter_mask(struct arm_pmu *pmu)
> ^~~~~~~
> arch/arm64/include/asm/kvm_pmu.h:246:53: warning: 'struct arm_pmu'
> declared inside parameter list will not be visible outside of this
> definition or declaration
> static inline u64 kvm_pmu_guest_counter_mask(struct arm_pmu *pmu)
> ^~~~~~~
> arch/arm64/kvm/sys_regs.c:856:6: warning: no previous prototype
> for 'pmu_access_el0_disabled' [-Wmissing-prototypes]
> bool pmu_access_el0_disabled(struct kvm_vcpu *vcpu)
> ^~~~~~~~~~~~~~~~~~~~~~~
> arch/arm64/kvm/sys_regs.c: In function 'access_pmu_evtyper':
> arch/arm64/kvm/sys_regs.c:1076:7: error: implicit declaration of
> function 'kvm_vcpu_pmu_is_partitioned'; did you
> mean 'kvm_pmu_is_partitioned'? [-Werror=implicit-function-declaration]
> if (kvm_vcpu_pmu_is_partitioned(vcpu))
> ^~~~~~~~~~~~~~~~~~~~~~~~~~~
> kvm_pmu_is_partitioned
> arch/arm64/kvm/sys_regs.c: In function 'set_pmcr':
>>> arch/arm64/kvm/sys_regs.c:1271:33: error: dereferencing pointer to
>>> incomplete type 'struct arm_pmu'
> new_n <= kvm->arch.arm_pmu->hpmn_max))
> ^~
> cc1: some warnings being treated as errors
Looks like the main problem here is struct arm_pmu is not defined if we
don't have CONFIG_ARM_PMU. I'll provide a dummy definition for that case
and swap out the field reference for a function call.
Secondary problem is making sure there is a prototype for
pmu_access_el0_disabled in that instance.
> vim +1271 arch/arm64/kvm/sys_regs.c
> 1253
> 1254 static int set_pmcr(struct kvm_vcpu *vcpu, const struct
> sys_reg_desc *r,
> 1255 u64 val)
> 1256 {
> 1257 u8 new_n = FIELD_GET(ARMV8_PMU_PMCR_N, val);
> 1258 struct kvm *kvm = vcpu->kvm;
> 1259
> 1260 mutex_lock(&kvm->arch.config_lock);
> 1261
> 1262 /*
> 1263 * The vCPU can't have more counters than the PMU hardware
> 1264 * implements. Ignore this error to maintain compatibility
> 1265 * with the existing KVM behavior.
> 1266 */
> 1267 if (!kvm_vm_has_ran_once(kvm) &&
> 1268 !vcpu_has_nv(vcpu) &&
> 1269 new_n <= kvm_arm_pmu_get_max_counters(kvm) &&
> 1270 (!kvm_vcpu_pmu_is_partitioned(vcpu) ||
>> 1271 new_n <= kvm->arch.arm_pmu->hpmn_max))
> 1272 kvm->arch.nr_pmu_counters = new_n;
> 1273
> 1274 mutex_unlock(&kvm->arch.config_lock);
> 1275
> 1276 /*
> 1277 * Ignore writes to RES0 bits, read only bits that are cleared on
> 1278 * vCPU reset, and writable bits that KVM doesn't support yet.
> 1279 * (i.e. only PMCR.N and bits [7:0] are mutable from userspace)
> 1280 * The LP bit is RES0 when FEAT_PMUv3p5 is not supported on the
> vCPU.
> 1281 * But, we leave the bit as it is here, as the vCPU's PMUver might
> 1282 * be changed later (NOTE: the bit will be cleared on first vCPU
> run
> 1283 * if necessary).
> 1284 */
> 1285 val &= ARMV8_PMU_PMCR_MASK;
> 1286
> 1287 /* The LC bit is RES1 when AArch32 is not supported */
> 1288 if (!kvm_supports_32bit_el0())
> 1289 val |= ARMV8_PMU_PMCR_LC;
> 1290
> 1291 __vcpu_assign_sys_reg(vcpu, r->reg, val);
> 1292 kvm_make_request(KVM_REQ_RELOAD_PMU, vcpu);
> 1293
> 1294 return 0;
> 1295 }
> 1296
> --
> 0-DAY CI Kernel Test Service
> https://github.com/intel/lkp-tests/wiki
next prev parent reply other threads:[~2025-06-23 22:11 UTC|newest]
Thread overview: 40+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-06-20 22:13 [PATCH v2 00/23] ARM64 PMU Partitioning Colton Lewis
2025-06-20 22:13 ` [PATCH v2 01/23] arm64: cpufeature: Add cpucap for HPMN0 Colton Lewis
2025-06-21 0:44 ` Oliver Upton
2025-06-23 18:25 ` Colton Lewis
2025-06-24 7:28 ` Oliver Upton
2025-06-24 20:05 ` Colton Lewis
2025-06-20 22:13 ` [PATCH v2 02/23] arm64: Generate sign macro for sysreg Enums Colton Lewis
2025-06-20 22:13 ` [PATCH v2 03/23] arm64: cpufeature: Add cpucap for PMICNTR Colton Lewis
2025-06-21 0:45 ` Oliver Upton
2025-06-23 18:25 ` Colton Lewis
2025-06-20 22:13 ` [PATCH v2 04/23] arm64: Define PMI{CNTR,FILTR}_EL0 as undef_access Colton Lewis
2025-06-20 22:13 ` [PATCH v2 05/23] KVM: arm64: Cleanup PMU includes Colton Lewis
2025-06-21 14:56 ` kernel test robot
2025-06-23 22:04 ` Colton Lewis
2025-06-20 22:13 ` [PATCH v2 06/23] KVM: arm64: Reorganize PMU functions Colton Lewis
2025-06-20 22:13 ` [PATCH v2 07/23] perf: arm_pmuv3: Introduce method to partition the PMU Colton Lewis
2025-06-21 1:06 ` Oliver Upton
2025-06-23 18:26 ` Colton Lewis
2025-06-24 7:05 ` Oliver Upton
2025-06-24 20:05 ` Colton Lewis
2025-06-20 22:13 ` [PATCH v2 07/23] perf: pmuv3: " Colton Lewis
2025-06-20 22:13 ` [PATCH v2 08/23] perf: arm_pmuv3: Generalize counter bitmasks Colton Lewis
2025-06-20 22:13 ` [PATCH v2 09/23] perf: arm_pmuv3: Keep out of guest counter partition Colton Lewis
2025-06-20 22:13 ` [PATCH v2 10/23] KVM: arm64: Correct kvm_arm_pmu_get_max_counters() Colton Lewis
2025-06-20 22:13 ` [PATCH v2 11/23] KVM: arm64: Set up FGT for Partitioned PMU Colton Lewis
2025-06-20 22:13 ` [PATCH v2 12/23] KVM: arm64: Writethrough trapped PMEVTYPER register Colton Lewis
2025-06-20 22:13 ` [PATCH v2 13/23] KVM: arm64: Use physical PMSELR for PMXEVTYPER if partitioned Colton Lewis
2025-06-20 22:13 ` [PATCH v2 14/23] KVM: arm64: Writethrough trapped PMOVS register Colton Lewis
2025-06-20 22:13 ` [PATCH v2 15/23] KVM: arm64: Write fast path PMU register handlers Colton Lewis
2025-06-20 22:13 ` [PATCH v2 16/23] KVM: arm64: Setup MDCR_EL2 to handle a partitioned PMU Colton Lewis
2025-06-20 22:13 ` [PATCH v2 17/23] KVM: arm64: Account for partitioning in PMCR_EL0 access Colton Lewis
2025-06-22 9:32 ` kernel test robot
2025-06-23 22:11 ` Colton Lewis [this message]
2025-06-20 22:13 ` [PATCH v2 18/23] KVM: arm64: Context swap Partitioned PMU guest registers Colton Lewis
2025-06-20 22:13 ` [PATCH v2 19/23] KVM: arm64: Enforce PMU event filter at vcpu_load() Colton Lewis
2025-06-20 22:13 ` [PATCH v2 20/23] perf: arm_pmuv3: Handle IRQs for Partitioned PMU guest counters Colton Lewis
2025-06-20 22:13 ` [PATCH v2 20/23] perf: pmuv3: " Colton Lewis
2025-06-20 22:13 ` [PATCH v2 21/23] KVM: arm64: Inject recorded guest interrupts Colton Lewis
2025-06-20 22:13 ` [PATCH v2 22/23] KVM: arm64: Add ioctl to partition the PMU when supported Colton Lewis
2025-06-20 22:13 ` [PATCH v2 23/23] KVM: arm64: selftests: Add test case for partitioned PMU Colton Lewis
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