From: Colton Lewis <coltonlewis@google.com>
To: "Chen, Zide" <zide.chen@intel.com>
Cc: kvm@vger.kernel.org, alexandru.elisei@arm.com,
pbonzini@redhat.com, corbet@lwn.net, linux@armlinux.org.uk,
catalin.marinas@arm.com, will@kernel.org, maz@kernel.org,
oliver.upton@linux.dev, mizhang@google.com, joey.gouly@arm.com,
suzuki.poulose@arm.com, yuzenghui@huawei.com,
mark.rutland@arm.com, shuah@kernel.org,
gankulkarni@os.amperecomputing.com, james.clark@linaro.org,
linux-doc@vger.kernel.org, linux-kernel@vger.kernel.org,
linux-arm-kernel@lists.infradead.org, kvmarm@lists.linux.dev,
linux-perf-users@vger.kernel.org,
linux-kselftest@vger.kernel.org
Subject: Re: [PATCH 14/21] KVM: arm64: Apply dynamic guest counter reservations
Date: Mon, 17 Aug 2026 22:24:48 +0000 [thread overview]
Message-ID: <gsntv798tmfj.fsf@coltonlewis-kvm.c.googlers.com> (raw)
In-Reply-To: <16296d40-67f3-4e50-923c-5b26fc122121@intel.com> (zide.chen@intel.com)
Hi Zide, thanks for the review.
"Chen, Zide" <zide.chen@intel.com> writes:
> On 6/12/2026 2:29 PM, Colton Lewis wrote:
>> Apply dynamic guest counter reservations by checking if the requested
>> guest mask collides with any events the host has scheduled and calling
>> pmu_perf_resched_update() with a hook that updates the mask of
>> available counters in between schedule out and schedule in.
>> Signed-off-by: Colton Lewis <coltonlewis@google.com>
>> ---
>> arch/arm64/kvm/pmu-direct.c | 69 +++++++++++++++++++++++++++++++++++-
>> include/linux/perf/arm_pmu.h | 1 +
>> 2 files changed, 69 insertions(+), 1 deletion(-)
>> diff --git a/arch/arm64/kvm/pmu-direct.c b/arch/arm64/kvm/pmu-direct.c
>> index 49f1feb5d280c..044f011c9c84b 100644
>> --- a/arch/arm64/kvm/pmu-direct.c
>> +++ b/arch/arm64/kvm/pmu-direct.c
>> @@ -87,6 +87,73 @@ u64 kvm_pmu_direct_pmcr_read(struct kvm_vcpu *vcpu)
>> ARMV8_PMU_PMCR_N);
>> }
>> +/* Callback to update counter mask between perf scheduling */
>> +static void kvm_pmu_update_mask(struct pmu *pmu, void *data)
>> +{
>> + struct arm_pmu *arm_pmu = to_arm_pmu(pmu);
>> + unsigned long *new_mask = data;
>> +
>> + bitmap_copy(arm_pmu->cntr_mask, new_mask, ARMPMU_MAX_HWEVENTS);
>> +}
>> +
>> +/**
>> + * kvm_pmu_set_guest_counters() - Handle dynamic counter reservations
>> + * @cpu_pmu: struct arm_pmu to potentially modify
>> + * @guest_mask: new guest mask for the pmu
>> + *
>> + * Check if guest counters will interfere with current host events and
>> + * call into perf_pmu_resched_update if a reschedule is required.
>> + */
>> +static void kvm_pmu_set_guest_counters(struct arm_pmu *cpu_pmu, u64
>> guest_mask)
>> +{
>> + struct pmu_hw_events *cpuc = this_cpu_ptr(cpu_pmu->hw_events);
>> + DECLARE_BITMAP(guest_bitmap, ARMPMU_MAX_HWEVENTS);
>> + DECLARE_BITMAP(new_mask, ARMPMU_MAX_HWEVENTS);
>> + bool need_resched = false;
>> +
>> + bitmap_from_arr64(guest_bitmap, &guest_mask, ARMPMU_MAX_HWEVENTS);
>> + bitmap_copy(new_mask, cpu_pmu->hw_cntr_impl, ARMPMU_MAX_HWEVENTS);
>> +
>> + if (guest_mask) {
>> + /* Subtract guest counters from available host mask */
>> + bitmap_andnot(new_mask, new_mask, guest_bitmap, ARMPMU_MAX_HWEVENTS);
>> +
>> + /* Did we collide with an active host event? */
>> + if (bitmap_intersects(cpuc->used_mask, guest_bitmap,
>> ARMPMU_MAX_HWEVENTS)) {
>> + int idx;
>> +
>> + need_resched = true;
>> + cpuc->host_squeezed = true;
>> +
>> + /* Look for pinned events that are about to be preempted */
>> + for_each_set_bit(idx, guest_bitmap, ARMPMU_MAX_HWEVENTS) {
>> + if (test_bit(idx, cpuc->used_mask) && cpuc->events[idx] &&
>> + cpuc->events[idx]->attr.pinned) {
>> + pr_warn_once("perf: Pinned host event squeezed out by KVM guest
>> PMU partition\n");
>> + break;
>> + }
>> + }
>> + }
>> + } else {
>> + /*
>> + * Restoring to hw_cntr_impl.
>> + * Only resched if we previously squeezed an event.
>> + */
>> + if (cpuc->host_squeezed) {
>> + need_resched = true;
>> + cpuc->host_squeezed = false;
>> + }
>> + }
>> +
>> + if (need_resched) {
>> + /* Collision: run full perf reschedule */
>> + perf_pmu_resched_update(&cpu_pmu->pmu, kvm_pmu_update_mask, new_mask);
>> + } else {
>> + /* Host was never using guest counters anyway */
>> + bitmap_copy(cpu_pmu->cntr_mask, new_mask, ARMPMU_MAX_HWEVENTS);
>> + }
>> +}
>> +
>> /**
>> * kvm_pmu_host_counter_mask() - Compute bitmask of host-reserved
>> counters
>> * @pmu: Pointer to arm_pmu struct
>> @@ -209,6 +276,7 @@ void kvm_pmu_load(struct kvm_vcpu *vcpu)
>> pmu = vcpu->kvm->arch.arm_pmu;
>> guest_counters = kvm_pmu_guest_counter_mask(pmu);
>> + kvm_pmu_set_guest_counters(pmu, guest_counters);
>> kvm_pmu_apply_event_filter(vcpu);
>> for_each_set_bit(i, &guest_counters, ARMPMU_MAX_HWEVENTS) {
>> @@ -317,7 +385,6 @@ void kvm_pmu_put(struct kvm_vcpu *vcpu)
>> /* Stop guest counters and disable interrupts in hardware. */
>> write_sysreg(mask, pmcntenclr_el0);
>> write_sysreg(mask, pmintenclr_el1);
>> -
>> kvm_pmu_set_guest_counters(pmu, 0);
> I must have missed something.
> Here, vcpu->kvm->arch.arm_pmu->cntr_mask is restored to cntr_mask_impl.
> Is this same struct shared with the perf driver
> (to_arm_pmu(event->pmu)), and shared across other vCPUs as well?
> If so, if another pCPU still has a PMU-partition-enabled vcpu loaded
> with guest-owned counters (MDCR_EL2.HPMN is set), could a host event be
> scheduled onto one of those guest-owned counters, conflicting with the
> guest?
You're correct that is shared more widely than appropriate and could
cause such a conflict.
cntr_mask should be moved to the per-CPU struct pmu_hw_events inside
struct arm_pmu.
>> preempt_enable();
>> }
next prev parent reply other threads:[~2026-08-17 22:24 UTC|newest]
Thread overview: 48+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-06-12 19:28 [PATCH v8 00/21] ARM64 PMU Partitioning Colton Lewis
2026-06-12 19:28 ` [PATCH 01/21] arm64: cpufeature: Add cpucap for HPMN0 Colton Lewis
2026-06-12 19:28 ` [PATCH 02/21] KVM: arm64: Reorganize PMU includes Colton Lewis
2026-06-12 19:28 ` [PATCH 03/21] KVM: arm64: Reorganize PMU functions Colton Lewis
2026-06-12 19:56 ` sashiko-bot
2026-06-12 19:28 ` [PATCH 04/21] perf: arm_pmuv3: Generalize counter bitmasks Colton Lewis
2026-06-12 19:28 ` [PATCH 05/21] perf: arm_pmuv3: Check cntr_mask before using pmccntr Colton Lewis
2026-06-12 19:42 ` sashiko-bot
2026-07-28 15:07 ` Robin Murphy
2026-08-04 21:25 ` Colton Lewis
2026-06-12 19:28 ` [PATCH 06/21] perf: arm_pmuv3: Allocate counter indices from high to low Colton Lewis
2026-06-12 19:28 ` [PATCH 07/21] perf: arm_pmuv3: Add method to partition the PMU Colton Lewis
2026-06-12 19:28 ` [PATCH 08/21] KVM: arm64: Set up FGT for Partitioned PMU Colton Lewis
2026-06-12 19:45 ` sashiko-bot
2026-06-12 19:28 ` [PATCH 09/21] KVM: arm64: Add Partitioned PMU register trap handlers Colton Lewis
2026-06-12 19:51 ` sashiko-bot
2026-06-12 19:28 ` [PATCH 10/21] KVM: arm64: Set up MDCR_EL2 to handle a Partitioned PMU Colton Lewis
2026-06-12 19:52 ` sashiko-bot
2026-06-12 19:28 ` [PATCH 11/21] KVM: arm64: Context swap Partitioned PMU guest registers Colton Lewis
2026-06-12 19:51 ` sashiko-bot
2026-07-20 16:46 ` James Clark
2026-07-21 23:05 ` Colton Lewis
2026-06-12 19:29 ` [PATCH 12/21] KVM: arm64: Enforce PMU event filter at vcpu_load() Colton Lewis
2026-06-12 19:53 ` sashiko-bot
2026-06-12 19:29 ` [PATCH 13/21] perf: Add perf_pmu_resched_update() Colton Lewis
2026-06-12 19:29 ` [PATCH 14/21] KVM: arm64: Apply dynamic guest counter reservations Colton Lewis
2026-06-12 19:50 ` sashiko-bot
2026-08-12 17:27 ` Chen, Zide
2026-08-17 22:24 ` Colton Lewis [this message]
2026-06-12 19:29 ` [PATCH 15/21] KVM: arm64: Implement lazy PMU context swaps Colton Lewis
2026-06-12 19:50 ` sashiko-bot
2026-06-12 19:29 ` [PATCH 16/21] perf: arm_pmuv3: Handle IRQs for Partitioned PMU guest counters Colton Lewis
2026-06-12 19:57 ` sashiko-bot
2026-06-12 19:29 ` [PATCH 17/21] KVM: arm64: Detect overflows for the Partitioned PMU Colton Lewis
2026-06-12 19:58 ` sashiko-bot
2026-06-12 19:29 ` [PATCH 18/21] KVM: arm64: Add vCPU device attr to partition the PMU Colton Lewis
2026-06-12 19:54 ` sashiko-bot
2026-06-12 19:29 ` [PATCH 19/21] KVM: selftests: Add find_bit to KVM library Colton Lewis
2026-06-12 20:01 ` sashiko-bot
2026-06-12 19:29 ` [PATCH 20/21] KVM: arm64: selftests: Add test case for Partitioned PMU Colton Lewis
2026-06-12 19:29 ` [PATCH 21/21] KVM: arm64: selftests: Relax testing for exceptions when partitioned Colton Lewis
2026-07-20 16:46 ` [PATCH v8 00/21] ARM64 PMU Partitioning James Clark
2026-07-21 23:03 ` Colton Lewis
2026-07-22 9:05 ` James Clark
2026-07-23 20:57 ` Colton Lewis
2026-07-27 11:04 ` James Clark
2026-08-04 21:06 ` Colton Lewis
2026-08-05 10:09 ` James Clark
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