measuring offcore events on snb

measuring offcore events on snb

[Yuanfang Chen]

Hi,

I'm trying to measure offcore events on snb. (kernel 3.6.0-rc3).  For example 
OFFCORE_RESPONSE.ALL_CODE_RD.LLC_HIT_N   is  0x10003C0244  according to 
intel manual. so I tried

perf stat -e r1b710003C0244 -- sleep 10
perf stat -e r10003C02441b7 -- sleep 10

both gives me 0, I did something wrong?

thank you so much,
yuanfang

Re: measuring offcore events on snb

[Andi Kleen]

Yuanfang Chen <tabloid.adroit@gmail.com> writes:

> Hi,
>
> I'm trying to measure offcore events on snb. (kernel 3.6.0-rc3).  For example 
> OFFCORE_RESPONSE.ALL_CODE_RD.LLC_HIT_N   is  0x10003C0244  according to 
> intel manual. so I tried
>
> perf stat -e r1b710003C0244 -- sleep 10
> perf stat -e r10003C02441b7 -- sleep 10
>
> both gives me 0, I did something wrong?

OFFCORE requires setting an external MSR. perf currently supports this
for its integrated events, as the support for setting the MSR directly
was not accepted. It works though to write the MSR manually through
/dev/cpu/*/msr, as long as you exclude conflicts manually. 
For details see the Intel SDM.

-Andi

-- 
ak@linux.intel.com -- Speaking for myself only

Re: measuring offcore events on snb

[Vince Weaver]

On Sat, 15 Sep 2012, Andi Kleen wrote:

> OFFCORE requires setting an external MSR. perf currently supports this
> for its integrated events, as the support for setting the MSR directly
> was not accepted. It works though to write the MSR manually through
> /dev/cpu/*/msr, as long as you exclude conflicts manually. 
> For details see the Intel SDM.

no, the kernel has had raw offcore response support since 3.3.  It works
fine.  It's just not easy to get if you use the "perf" tool.  (PAPI and 
libpfm4 support it fine).

as far as I know the only way to do it is to use the rediculous
   -e cpu/cmask=1,event=2,umask=3,config1=3f80408fff
format.

Vince

Re: measuring offcore events on snb

[Andi Kleen]

> the kernel has had raw offcore response support since 3.3.  It works
> fine.  It's just not easy to get if you use the "perf" tool.  (PAPI and 

It is easy. Just write the MSR.

> as far as I know the only way to do it is to use the rediculous
>    -e cpu/cmask=1,event=2,umask=3,config1=3f80408fff
http://www.heise.de/netze/news/foren/S-Europaeischer-IPv4-Adresspool-erreicht-die-Reserve/forum-237910/list/e-22434521/hs-16/

Ah true. Good point. That thing always reminds me of JCL. Setting the MSR is 
probably easier though...

-Andi

-- 
ak@linux.intel.com -- Speaking for myself only.

Re: measuring offcore events on snb

[Yuanfang Chen]

On Sat, Sep 15, 2012 at 9:06 PM, Vince Weaver <vince@deater.net> wrote:
> On Sat, 15 Sep 2012, Andi Kleen wrote:
>
>> OFFCORE requires setting an external MSR. perf currently supports this
>> for its integrated events, as the support for setting the MSR directly
>> was not accepted. It works though to write the MSR manually through
>> /dev/cpu/*/msr, as long as you exclude conflicts manually.
>> For details see the Intel SDM.
>
> no, the kernel has had raw offcore response support since 3.3.  It works
> fine.  It's just not easy to get if you use the "perf" tool.  (PAPI and
> libpfm4 support it fine).
>
> as far as I know the only way to do it is to use the rediculous
>    -e cpu/cmask=1,event=2,umask=3,config1=3f80408fff
> format.

just found that commit in git log also. however, even just with perf version of
that commit, I still get 'invalid or unsupported event' error. Have you been
successful using this option?

thanks,
yuanfang

>
> Vince