From: sashiko-bot@kernel.org
To: "Guixiong Wei" <weiguixiong@bytedance.com>
Cc: linux-perf-users@vger.kernel.org
Subject: Re: [PATCH] perf/x86/intel/uncore: Fix DMR CXL CM invert filter
Date: Thu, 08 Oct 2026 05:33:45 +0000 [thread overview]
Message-ID: <sashiko-outbox-163628@kernel.org> (raw)
In-Reply-To: <20261008051953.6293-2-weiguixiong@bytedance.com>
> The DMR CXL CM PMU places its invert filter at config bit 21 and its
> 9-bit threshold at bits 23-31. However, dmr_uncore_cxlcm uses
> GENERIC_PMON_RAW_EVENT_MASK, which covers the threshold through the
> generic bit 23 invert field and bits 24-31 threshold field, but does not
> include the relocated invert bit. As a result, uncore_pmu_event_init()
> silently clears bit 21 and inv=1 programs the same configuration as
> inv=0.
>
> Add bit 21 to a DMR CXL CM-specific event mask so the requested invert
> filter reaches hardware.
>
> Fixes: 6daf2c35b835 ("perf/x86/intel/uncore: Add IMH PMON support for Diamond Rapids")
> Signed-off-by: Guixiong Wei <weiguixiong@bytedance.com>
Sashiko has reviewed this patch and found no issues. It looks great!
--
Sashiko AI review · https://sashiko.dev/#/patchset/20261008051953.6293-2-weiguixiong@bytedance.com?part=1
next prev parent reply other threads:[~2026-10-08 5:33 UTC|newest]
Thread overview: 3+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-10-08 5:19 [PATCH] perf/x86/intel/uncore: Fix DMR CXL CM invert filter Guixiong Wei
2026-10-08 5:33 ` sashiko-bot [this message]
2026-10-08 15:12 ` Chen, Zide
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