From: sashiko-bot@kernel.org
To: "Zhao Gongyi" <zhaogongyi@bytedance.com>
Cc: linux-perf-users@vger.kernel.org
Subject: Re: [PATCH v2] perf/riscv: Guard PMU counter indices and user access
Date: Mon, 09 Nov 2026 11:52:17 +0000 [thread overview]
Message-ID: <sashiko-outbox-204907@kernel.org> (raw)
In-Reply-To: <20261109113909.38153-1-zhaogongyi@bytedance.com>
> A disabled event may be mmaped before hw.idx is assigned; a userpage
> update with that invalid index can make pmu_sbi_csr_index() access
> pmu_ctr_list[] out of bounds.
>
> Validate indices before publishing or using a CSR, and reject
> out-of-range SBI results before accessing counter state. Keep mmap
> authorization independent of assignment for disabled events.
>
> Reject a zero SBI counter count before allocating counter state. A
> zero-length pmu_ctr_list[] would be dereferenced when a non-sampling
> event selects its initial counter width.
>
> Fixes: cc4c07c89aad ("drivers: perf: Implement perf event mmap support in the SBI backend")
> Signed-off-by: Zhao Gongyi <zhaogongyi@bytedance.com>
Sashiko has reviewed this patch and found no issues.
--
Sashiko AI review · https://sashiko.dev/#/patchset/20261109113909.38153-1-zhaogongyi@bytedance.com?part=1
prev parent reply other threads:[~2026-11-09 11:52 UTC|newest]
Thread overview: 5+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-11-03 9:37 [PATCH] perf/riscv: Guard PMU counter indices and user access Zhao Gongyi
2026-11-03 9:57 ` sashiko-bot
2026-11-03 10:47 ` Zhao Gongyi
2026-11-09 11:39 ` [PATCH v2] " Zhao Gongyi
2026-11-09 11:52 ` sashiko-bot [this message]
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