From: sashiko-bot@kernel.org
To: "Vladimir Kondratiev" <vladimir.kondratiev@mobileye.com>
Cc: linux-rt-devel@lists.linux.dev, devicetree@vger.kernel.org,
linux-perf-users@vger.kernel.org, robh@kernel.org,
conor+dt@kernel.org, linux-kernel@vger.kernel.org
Subject: Re: [PATCH v2 1/6] MIPS: CM: Make cm_core_lock raw spinlocks
Date: Thu, 12 Nov 2026 12:39:56 +0000 [thread overview]
Message-ID: <sashiko-outbox-211101@kernel.org> (raw)
In-Reply-To: <20261112-i6500-cm3-pmu-v2-1-cd2569571819@mobileye.com>
Thank you for your contribution! Sashiko AI review found 1 potential
issue to consider:
- [High] mips: cm: invalid wait context in mips_cpc_lock_other() under
cm_core_lock
--
commit 4e39a6ca6a7f0be5ae6999f6aa8d3e3e05b7551d
Author: Paul Burton <paulburton@kernel.org>
MIPS: CM: Make cm_core_lock raw spinlocks
This commit converts the per-CPU cm_core_lock from spinlock_t to
raw_spinlock_t so that preemption remains disabled while accessing the
core-other CM register block on PREEMPT_RT kernels.
> diff --git a/arch/mips/kernel/mips-cm.c b/arch/mips/kernel/mips-cm.c
> index 7c9c5dc38823f..3bfe85e86a9a5 100644
> --- a/arch/mips/kernel/mips-cm.c
> +++ b/arch/mips/kernel/mips-cm.c
[ ... ]
> @@ -359,8 +359,8 @@ void mips_cm_lock_other(unsigned int cluster, unsigned int core,
> * race with us.
> */
> curr_core = cpu_core(¤t_cpu_data);
> - spin_lock_irqsave(&per_cpu(cm_core_lock, curr_core),
> - per_cpu(cm_core_lock_flags, curr_core));
> + raw_spin_lock_irqsave(&per_cpu(cm_core_lock, curr_core),
> + per_cpu(cm_core_lock_flags, curr_core));
>
> val = FIELD_PREP(CM_GCR_Cx_OTHER_CORENUM, core);
> }
[Severity: High]
Does converting cm_core_lock to raw_spinlock_t without also converting
cpc_core_lock cause an invalid wait context in mips_cpc_lock_other() on
systems with CM < 3?
mips_cpc_lock_other() is always called inside a mips_cm_lock_other() /
mips_cm_unlock_other() section (for example in boot_core() and
mips_smp_send_ipi_mask()). On CM < 3 systems, mips_cpc_lock_other()
acquires cpc_core_lock, which is still a spinlock_t:
arch/mips/kernel/mips-cpc.c:mips_cpc_lock_other() {
if (mips_cm_revision() >= CM_REV_CM3)
/* Systems with CM >= 3 lock the CPC via mips_cm_lock_other */
return;
preempt_disable();
curr_core = cpu_core(¤t_cpu_data);
spin_lock_irqsave(&per_cpu(cpc_core_lock, curr_core),
per_cpu(cpc_core_lock_flags, curr_core));
...
}
Taking spinlock_t cpc_core_lock while holding raw_spinlock_t cm_core_lock
triggers a lockdep invalid wait context warning and sleeps in atomic
context on PREEMPT_RT kernels.
--
Sashiko AI review · https://sashiko.dev/#/patchset/20261112-i6500-cm3-pmu-v2-0-cd2569571819@mobileye.com?part=1
next prev parent reply other threads:[~2026-11-12 12:39 UTC|newest]
Thread overview: 13+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-11-12 12:28 [PATCH v2 0/6] perf: add PMU driver for the MIPS Coherence Manager 3 performance counters Vladimir Kondratiev
2026-11-12 12:28 ` [PATCH v2 1/6] MIPS: CM: Make cm_core_lock raw spinlocks Vladimir Kondratiev
2026-11-12 12:39 ` sashiko-bot [this message]
2026-11-12 12:28 ` [PATCH v2 2/6] MIPS: CM: add CM3 performance counter GCR definitions Vladimir Kondratiev
2026-11-12 12:33 ` sashiko-bot
2026-11-12 12:29 ` [PATCH v2 3/6] MIPS: CM: export the symbols needed to access the GCRs from a module Vladimir Kondratiev
2026-11-12 12:31 ` sashiko-bot
2026-11-12 12:29 ` [PATCH v2 4/6] dt-bindings: mips: mti,mips-cm: add performance counter interrupt Vladimir Kondratiev
2026-11-12 12:32 ` sashiko-bot
2026-11-12 12:29 ` [PATCH v2 5/6] perf: add MIPS Coherence Manager 3 (CM3) PMU driver Vladimir Kondratiev
2026-11-12 13:02 ` sashiko-bot
2026-11-12 12:29 ` [PATCH v2 6/6] MIPS: eyeq6_defconfig: enable the CM3 PMU Vladimir Kondratiev
2026-11-12 12:35 ` sashiko-bot
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