From: Geraldo Nascimento <geraldogabriel@gmail.com>
To: linux-rockchip@lists.infradead.org
Cc: "Shawn Lin" <shawn.lin@rock-chips.com>,
"Lorenzo Pieralisi" <lpieralisi@kernel.org>,
"Krzysztof Wilczyński" <kw@linux.com>,
"Manivannan Sadhasivam" <mani@kernel.org>,
"Rob Herring" <robh@kernel.org>,
"Bjorn Helgaas" <bhelgaas@google.com>,
"Heiko Stuebner" <heiko@sntech.de>,
"Vinod Koul" <vkoul@kernel.org>,
"Kishon Vijay Abraham I" <kishon@kernel.org>,
"Rick wertenbroek" <rick.wertenbroek@gmail.com>,
linux-phy@lists.infradead.org, linux-pci@vger.kernel.org,
linux-arm-kernel@lists.infradead.org,
linux-kernel@vger.kernel.org
Subject: [RFC PATCH v6 2/4] PCI: rockchip: Set Target Link Speed before retraining
Date: Fri, 20 Jun 2025 22:48:30 -0300 [thread overview]
Message-ID: <0afa6bc47b7f50e2e81b0b47d51c66feb0fb565f.1750470187.git.geraldogabriel@gmail.com> (raw)
In-Reply-To: <cover.1750470187.git.geraldogabriel@gmail.com>
Current code may fail 5.0GT/s retraining if Target Link Speed is set to
2.5 GT/s in Link Control and Status Register 2. Set it to 5.0 GT/s
accordingly.
Tested-by: Robin Murphy <robin.murphy@arm.com>
Signed-off-by: Geraldo Nascimento <geraldogabriel@gmail.com>
---
drivers/pci/controller/pcie-rockchip-host.c | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/drivers/pci/controller/pcie-rockchip-host.c b/drivers/pci/controller/pcie-rockchip-host.c
index 65653218b9ab..25890f6c0e17 100644
--- a/drivers/pci/controller/pcie-rockchip-host.c
+++ b/drivers/pci/controller/pcie-rockchip-host.c
@@ -341,6 +341,10 @@ static int rockchip_pcie_host_init_port(struct rockchip_pcie *rockchip)
* Enable retrain for gen2. This should be configured only after
* gen1 finished.
*/
+ status = rockchip_pcie_read(rockchip, PCIE_RC_CONFIG_CR + PCI_EXP_LNKCTL2);
+ status &= ~PCI_EXP_LNKCTL2_TLS;
+ status |= PCI_EXP_LNKCTL2_TLS_5_0GT;
+ rockchip_pcie_write(rockchip, status, PCIE_RC_CONFIG_CR + PCI_EXP_LNKCTL2);
status = rockchip_pcie_read(rockchip, PCIE_RC_CONFIG_CR + PCI_EXP_LNKCTL);
status |= PCI_EXP_LNKCTL_RL;
rockchip_pcie_write(rockchip, status, PCIE_RC_CONFIG_CR + PCI_EXP_LNKCTL);
--
2.49.0
--
linux-phy mailing list
linux-phy@lists.infradead.org
https://lists.infradead.org/mailman/listinfo/linux-phy
next prev parent reply other threads:[~2025-06-21 1:52 UTC|newest]
Thread overview: 7+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-06-21 1:47 [RFC PATCH v6 0/4] PCI: rockchip: Improve driver quality Geraldo Nascimento
2025-06-21 1:48 ` [RFC PATCH v6 1/4] PCI: rockchip: Use standard PCIe defines Geraldo Nascimento
2025-06-21 1:48 ` Geraldo Nascimento [this message]
2025-06-21 1:48 ` [RFC PATCH v6 3/4] phy: rockchip-pcie: Enable all four lanes if required Geraldo Nascimento
2025-06-21 1:49 ` [RFC PATCH v6 4/4] phy: rockchip-pcie: Properly disable TEST_WRITE strobe signal Geraldo Nascimento
2025-06-21 7:39 ` [RFC PATCH v6 0/4] PCI: rockchip: Improve driver quality Heiko Stuebner
2025-06-21 11:33 ` Geraldo Nascimento
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