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Tue, 27 May 2025 10:45:30 +0000 (GMT) From: "Shradha Todi" To: "'Krzysztof Kozlowski'" Cc: , , , , , , , , , , , , , , , , , , , In-Reply-To: <20250521-competent-honeybee-of-will-3f3ae1@kuoka> Subject: RE: [PATCH 09/10] PCI: exynos: Add support for Tesla FSD SoC Date: Tue, 27 May 2025 16:15:29 +0530 Message-ID: <0e2801dbcef4$78fe5ec0$6afb1c40$@samsung.com> MIME-Version: 1.0 X-Mailer: Microsoft Outlook 16.0 Thread-Index: AQKa2HaEso6x90WQFKmaYw3pYxuT6gLGtKN5Ag2CUBUBvBCtG7IzpxAA Content-Language: en-in X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFnrAIsWRmVeSWpSXmKPExsWy7bCSnO7Z6aYZBpcuSVk8mLeNzeLvpGPs FkuaMizW7D3HZDH/yDlWixu/2lgtVnyZyW5xtPU/s8XLWffYLM6f38Bu0dDzm9Vi0+NrrBaX d81hszg77zibxYRV31gszn5fwGTR8qeFxWLtkbvsFndbOlkt/u/ZwW6x884JZgdRj9+/JjF6 7Jx1l91jwaZSj02rOtk87lzbw+bx5Mp0Jo/NS+o9+rasYvQ48nU6i8fnTXIBXFFcNimpOZll qUX6dglcGQcXtTEX7BeueHd1HWsDY6NAFyMHh4SAicTpeaZdjFwcQgK7GSV2H9/H1sXICRSX lPh8cR0ThC0ssfLfc3aIomeMEs2fHjKDJNgEdCSeXPkDZosI6EpsvrEcrIhZYDuLxJmlDxkh Ot4zSrS2bWEFqeIUsJe4NakXrENYwFVix+n3YDaLgKrE0f3TwFbzClhKtBzbygphC0qcnPmE BcRmFtCW6H3YyghjL1v4mhniPAWJn0+XsUJc4SaxYslBqHpxiaM/e5gnMArPQjJqFpJRs5CM moWkZQEjyypGydSC4tz03GLDAsO81HK94sTc4tK8dL3k/NxNjOBEoKW5g3H7qg96hxiZOBgP MUpwMCuJ8G6bYJIhxJuSWFmVWpQfX1Sak1p8iFGag0VJnFf8RW+KkEB6YklqdmpqQWoRTJaJ g1OqgWmnfMa32XIi8zh+mf4yL3j35vz1hfL/Hq3+vzbygrhv/u8ZPSJcH3dqzFy9u+EGA29G fef0lfFCxo8m+E1cvsJ7y6Il+7YZNBfPNTb6fvZMluduXUnjusitiouj815NczijP+fhCjOr e3e85KQ5HU9esMuxWFxnsD/AuUDzZeEUnhsW05Nv7XFb927nW5VrhfXFM5ZpXE4uM3pky+Ih 4eh2NDPD5rHPvcRTFbpSyxLPfMrlepDKYd6ek8n18chzCVUug/VLm/bonDtbftK356/5xIOP JlpfVLU5arQp4Ub836IWdYOVz968dvVcWcB6Y9eJIx4zbFfOdYmaeelhTMFWnsibk/axbnlu O4e99cEbJZbijERDLeai4kQAUGU8LXMDAAA= X-CMS-MailID: 20250527104533epcas5p2ce335b06bb6564469fcfd96786de5cbb X-Msg-Generator: CA X-Sendblock-Type: REQ_APPROVE CMS-TYPE: 105P cpgsPolicy: CPGSC10-541,Y X-CFilter-Loop: Reflected X-CMS-RootMailID: 20250518193300epcas5p17e954bb18de9169d65e00501b1dcd046 References: <20250518193152.63476-1-shradha.t@samsung.com> <20250518193152.63476-10-shradha.t@samsung.com> <20250521-competent-honeybee-of-will-3f3ae1@kuoka> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20250527_215330_427797_58E65FCE X-CRM114-Status: GOOD ( 18.33 ) X-BeenThere: linux-phy@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: Linux Phy Mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-phy" Errors-To: linux-phy-bounces+linux-phy=archiver.kernel.org@lists.infradead.org > -----Original Message----- > From: Krzysztof Kozlowski > Sent: 21 May 2025 15:18 > To: Shradha Todi > Cc: linux-pci@vger.kernel.org; devicetree@vger.kernel.org; linux-arm-kernel@lists.infradead.org; linux-samsung-soc@vger.kernel.or; > linux-kernel@vger.kernel.org; linux-phy@lists.infradead.org; manivannan.sadhasivam@linaro.org; lpieralisi@kernel.org; > kw@linux.com; robh@kernel.org; bhelgaas@google.com; jingoohan1@gmail.com; krzk+dt@kernel.org; conor+dt@kernel.org; > alim.akhtar@samsung.com; vkoul@kernel.org; kishon@kernel.org; arnd@arndb.de; m.szyprowski@samsung.com; > jh80.chung@samsung.com > Subject: Re: [PATCH 09/10] PCI: exynos: Add support for Tesla FSD SoC > > On Mon, May 19, 2025 at 01:01:51AM GMT, Shradha Todi wrote: > > static int exynos_pcie_probe(struct platform_device *pdev) { > > struct device *dev = &pdev->dev; > > @@ -355,6 +578,26 @@ static int exynos_pcie_probe(struct platform_device *pdev) > > if (IS_ERR(ep->phy)) > > return PTR_ERR(ep->phy); > > > > + if (ep->pdata->soc_variant == FSD) { > > + ret = dma_set_mask_and_coherent(dev, DMA_BIT_MASK(36)); > > + if (ret) > > + return ret; > > + > > + ep->sysreg = syscon_regmap_lookup_by_phandle(dev->of_node, > > + "samsung,syscon-pcie"); > > + if (IS_ERR(ep->sysreg)) { > > + dev_err(dev, "sysreg regmap lookup failed.\n"); > > + return PTR_ERR(ep->sysreg); > > + } > > + > > + ret = of_property_read_u32_index(dev->of_node, "samsung,syscon-pcie", 1, > > + &ep->sysreg_offset); > > + if (ret) { > > + dev_err(dev, "couldn't get the register offset for syscon!\n"); > > So all MMIO will go via syscon? I am pretty close to NAKing all this, but let's be sure that I got it right - please post your complete DTS > for upstream. That's a requirement from me for any samsung drivers - I don't want to support fake, broken downstream solutions > (based on multiple past submissions). > By all MMIO do you mean DBI read/write? The FSD hardware architecture is such that the DBI/ATU/DMA address is at the same offset. The syscon register holds the upper bits of the actual address differentiating between these 3 spaces. This kind of implementation was done to reduce address space for PCI DWC controller. So yes, each DBI/ATU register read/write will have syscon write before it to switch address space. > Best regards, > Krzysztof -- linux-phy mailing list linux-phy@lists.infradead.org https://lists.infradead.org/mailman/listinfo/linux-phy