From: Vinod Koul <vkoul@kernel.org>
To: Jonathan Hunter <jonathanh@nvidia.com>, JC Kuo <jckuo@nvidia.com>,
Neil Armstrong <neil.armstrong@linaro.org>,
Thierry Reding <thierry.reding@kernel.org>,
Wei-Cheng Chen <weichengc@nvidia.com>
Cc: Wayne Chang <waynec@nvidia.com>, WK Tsai <wtsai@nvidia.com>,
linux-phy@lists.infradead.org, linux-tegra@vger.kernel.org,
linux-kernel@vger.kernel.org
Subject: Re: [PATCH v2] phy: tegra: xusb: Fix per-pad high-speed termination calibration
Date: Sun, 10 May 2026 17:53:45 +0530 [thread overview]
Message-ID: <177841582520.420676.17804594742388538049.b4-ty@kernel.org> (raw)
In-Reply-To: <20260504033305.2283145-1-weichengc@nvidia.com>
On Mon, 04 May 2026 11:33:05 +0800, Wei-Cheng Chen wrote:
> The existing code reads a single hs_term_range_adj value from bit field
> [10:7] of FUSE_SKU_CALIB_0 and applies it to all USB2 pads uniformly.
> However, on SoCs that support per-pad termination, each pad has its own
> hs_term_range_adj field: pad 0 in FUSE_SKU_CALIB_0[10:7], and pads 1-3
> in FUSE_USB_CALIB_EXT_0 at bit offsets [8:5], [12:9], and [16:13]
> respectively.
>
> [...]
Applied, thanks!
[1/1] phy: tegra: xusb: Fix per-pad high-speed termination calibration
commit: da110228b54f2e2143d97ea7151e0dc22e539d67
Best regards,
--
~Vinod
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prev parent reply other threads:[~2026-05-10 12:23 UTC|newest]
Thread overview: 2+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-05-04 3:33 [PATCH v2] phy: tegra: xusb: Fix per-pad high-speed termination calibration Wei-Cheng Chen
2026-05-10 12:23 ` Vinod Koul [this message]
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