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Thu, 17 Sep 2026 11:28:04 -0700 (PDT) Received: from localhost.localdomain ([94.252.75.113]) by smtp.googlemail.com with ESMTPSA id 5b1f17b1804b1-49fbbd83e39sm126935705e9.4.2026.09.17.11.28.02 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 17 Sep 2026 11:28:03 -0700 (PDT) From: Oleg Keri To: Nabige Aala , Vinod Koul , Neil Armstrong , Manivannan Sadhasivam Cc: linux-arm-msm@vger.kernel.org, linux-phy@lists.infradead.org, linux-kernel@vger.kernel.org, Ritesh Kumar , Mahadevan P Subject: Re: [PATCH v4 4/9] phy: qualcomm: qmp-combo: Add hardware-specific DP PHY config fields Date: Thu, 17 Sep 2026 20:27:54 +0200 Message-ID: <178966967452.3333.16125740437772430030@gmail.com> X-Mailer: git-send-email 2.55.0 In-Reply-To: <20260908-glymur-phy-v3-v4-4-ff22e5150538@oss.qualcomm.com> References: <20260908-glymur-phy-v3-v4-4-ff22e5150538@oss.qualcomm.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.9.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20260917_112806_529227_C66223E1 X-CRM114-Status: GOOD ( 11.60 ) X-BeenThere: linux-phy@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: Linux Phy Mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-phy" Errors-To: linux-phy-bounces+linux-phy=archiver.kernel.org@lists.infradead.org Hi Nabige, On Tue, Sep 08, 2026, Nabige Aala wrote: > Update qmp_combo_configure_dp_mode() to honor dp_mode_ignore_reverse, > so Glymur can bypass TypeC orientation-based lane reversal. This breaks 2-lane DP with a reversed plug on a Lenovo Yoga Slim 7x Gen 11 (Glymur), with the whole v4 series on next-20260916. With dp_mode_ignore_reverse set, qmp_combo_configure_dp_mode() always programs the normal side (DP_PHY_MODE 0x5c, lane 2/3 power bits in DP_PHY_PD_CTL), while qmp_v8_configure_dp_phy() still follows the real orientation and enables TXA for a reversed plug. With fewer than four lanes the two no longer match. On a 2-lane DP + USB3 dock (HBR2, one LTTPR) the reversed plug passes clock recovery and then never reaches channel EQ: the LTTPR reports CR_DONE on both lanes but never EQ_DONE or SYMBOL_LOCKED, walks its pre-emphasis request up to level 3 at swing level 0, and then clock recovery is lost. All four attempts end the same way: [drm:msm_dp_ctrl_link_train_1_2] *ERROR* link training #2 on phy 1 failed. ret=-110 [drm:msm_dp_ctrl_setup_main_link] *ERROR* link training of LTTPR(s) failed. ret=-110 [drm:msm_dp_display_atomic_enable] *ERROR* Failed link training (rc=-104) The same dock trains at once with the plug the other way round. UCSI and pmic_glink_altmode report the same orientation in both cases, so the orientation itself is right. Ignoring the orientation only when all four lanes carry DP fixes it here, both orientations train: - bool reverse = (qmp->orientation == TYPEC_ORIENTATION_REVERSE) && - !cfg->dp_mode_ignore_reverse; const struct phy_configure_opts_dp *dp_opts = &qmp->dp_opts; + bool reverse = (qmp->orientation == TYPEC_ORIENTATION_REVERSE) && + !(cfg->dp_mode_ignore_reverse && dp_opts->lanes == 4); I have no 4-lane sink to check whether 0x5c is really needed for a reversed 4-lane link; could you say what the flag is for? Separately, on 7/9: LN0/LN1_DRV_LVL is now looked up from v/p levels, but only in qmp_v8_configure_dp_clocks(), i.e. at power-on when both are zero. Level changes during training go through configure_dp_tx(), which does not touch these registers, so they stay at the [0][0] entry (0x02 at HBR2) where the old code had 0x1f. I can test a v5 on this machine. Thanks, Oleg -- linux-phy mailing list linux-phy@lists.infradead.org https://lists.infradead.org/mailman/listinfo/linux-phy